JPH11145296A - Semiconductor device layout design method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time required for a layout design without increasing the chip size by a method wherein a bypass wiring has been disposed in advance in a block and a wiring passing through the block is constituted by the bypass wiring. SOLUTION: When an interval between a block 12 and a block 13 which are disposed at a position pinching a block 11 is connected via a wiring 18, the wiring 18 is connected to a pin 16a of a bypass wiring 15 disposed in a low order block. Then, a net name of a pin 16b added to the pin 16a and an end part on the opposite side of the bypass wiring 15 succeeds the net name of the connected wiring is changed to the same net name. The pin 16b on the opposite side of the bypass wiring 15 is further connected to a pin 19 having the same net name as the block 13, so that a wiring of a net name Net1 can be passed into the block 11. For this reason, it is unnecessary to prepare a region of a passing wiring when the wiring passes on the block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design of a semiconductor device such as an LSI, and more particularly, to deciding a wiring route between blocks, eliminating the trouble of changing the arrangement and wiring in the block and verifying the layout again. Related to the technology aimed at.

[0002]

2. Description of the Related Art Conventionally, in the layout design of a semiconductor device such as an LSI, an entire circuit is divided into several layout blocks (hereinafter, blocks), a layout design is performed for each block, and blocks arranged in a layout are further arranged. Wiring them together completes the chip.

FIG. 5 is a conceptual diagram showing an example of a conventional layout design. In FIG. 5, the block 31 and the block 32 can be connected linearly by the wiring 33, but the block 34 and the block 35 cannot be connected linearly. No. However, if the wiring connecting between the block 34 and the block 35 can be passed over the block 37 like the wiring 36, the wiring length can be shortened and the chip size can be reduced.

In order for the wiring to pass over the block 37 as described above, a continuous area in which the wiring can pass within the block 37 is required. However, the design in each block does not take into account the wiring that passes over the block, so that the areas through which the wiring passes are usually not continuous as in the regions 38 and 39 shown in FIG. .

[0005]

Therefore, in the prior art, when it has been decided that the wiring should be passed over a specific block, the layout is returned to the lower hierarchy and the arrangement wiring in the block is changed as shown in FIG. In this case, it is necessary to create the area 40 for the passing wiring.

On the other hand, when layout verification such as design rule verification (DRC) and connection verification (LVS) in a block is performed, even if the verification is performed on the chip after all of the blocks are completed at once, the verification of each block is performed. Many errors are left inside, so a lot of errors are detected. At this point, the layout design of the entire chip has been completed, and there is no space left for expanding the portion where the interval is violated. Therefore, verification is usually performed when layout design of each block is completed, and error correction is completed. By doing so, when verifying the entire chip, there should not be any errors inside the blocks, so the remaining errors are only related to the connection wiring between blocks and the spacing between blocks, making it easy to correct .

However, even in a block whose layout has been verified and errors have been corrected, if the wiring connecting the blocks passes over the block, as shown in FIG. Data area 42
There is a possibility that an interval error may occur between the two. In FIG. 8, a proximity error occurs in the area 43. To check for this type of error, use the entire lower-level block that has already been verified,
The layout must be verified again. this is,
The same is true even when an error occurs between blocks in a higher hierarchy.

In the block configuration as shown in FIG. 5, the layout in the block cannot be changed.
If an area for wiring passing between the block 34 and the block 35 cannot be created in the block 37, the area shown in FIG.
As shown by, wiring is performed around the block 37. However, when the block 37 is bypassed, the wiring length becomes longer, and blocks around the block 37 (for example, the block 31, the block 44, etc.) are moved.
Since a wide wiring area must be secured, the chip size increases.

As described above, in the conventional layout design, when a wiring passes over a block, it is necessary to return to the lower hierarchy and change the arrangement and wiring in the block to create an area for the passing wiring. In addition, even if such a region for passing wiring is created in a block, if a spacing error occurs in the wiring connecting the blocks, the entire lower-level block that has already been verified will be On the other hand, there is a problem that the layout must be verified again. In addition, in the method of wiring around blocks, there is a problem that the wiring length is increased and the chip size is increased.

[0010] The present invention has been made to solve the above-mentioned problems, and without increasing the chip size,
An object of the present invention is to provide a layout design method for a semiconductor device, which can reduce the time required for layout design.

[0011]

According to a first aspect of the present invention, there is provided a layout method for a semiconductor device, comprising: arranging a bypass wiring passing through a layout block in a layout block including circuit elements; When a wiring connecting between two different layout blocks disposed at the sandwiched position passes over the layout block, the wiring is configured by a bypass wiring disposed in the layout block. Features.

According to a second aspect of the present invention, in the semiconductor device layout method according to the first aspect, the end of the bypass wiring is changed to the same net name by inheriting the net name of the connected wiring. It is characterized by adding a variable pin.

According to a third aspect of the present invention, in the semiconductor device layout method according to the first or second aspect, a plurality of the bypass wirings are arranged in a layout block.

According to a fourth aspect of the present invention, in the layout method of the semiconductor device according to the first, second or third aspect, the bypass wiring is branched into a plurality of parts in a layout block.

According to a fifth aspect of the present invention, there is provided a semiconductor device, wherein a layout block composed of circuit elements is provided with a bypass wiring passing through the layout block, and two layout wirings are arranged at positions sandwiching the layout block. A wiring connecting between different layout blocks, wherein a wiring passing over the layout block is constituted by a bypass wiring arranged in the layout block.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device layout designing method and a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a schematic configuration diagram of blocks used in a layout design method of a first embodiment. In block 11 of the first embodiment, the data area 1
4, a wirable area 17 is formed.
The bypass wiring 1 passing through the block 11
5 are arranged. The bypass wiring 15 is arranged so as to connect from one edge of the block 11 to the other edge at a position opposite thereto, and each end inherits the net name of the connected wiring. Pins 16a and 16b are added to change the net name to the same net name. A pin with a variable net name is different from an ordinary pin with a fixed net name and has a special net name (eg, Variable_net) indicating that it is variable. When a wire having net information is connected to this pin, the pin name is changed. It is changed to the net name of the wiring. The function of the pins 16a and 16b with variable net names is
It can be realized on the D tool.

The bypass wiring 15 is provided when the wiring connecting another block is apparently or possibly passed through the block 11 at the stage of the floor plan of the layout design. Or a lower layer below the block 11.

FIG. 2 is a schematic configuration diagram in the case where wiring between blocks is performed using the block 11 configured as shown in FIG. FIG. 2 shows a configuration in which the blocks 12 and 13 are arranged at positions sandwiching the block 11, and the blocks 12 and 13 are connected by the wiring 18. First, when connecting the blocks in the upper hierarchy, the wiring 18 connecting the blocks is connected to the pin 16a of the bypass wiring 15 arranged in the lower block. Then, the net name of the pin 16b (here, Net1) added to the opposite end of the pin 16a and the bypass wiring 15 is changed to the same net name by inheriting the net name of the connected wiring. (It can be confirmed on the display screen what net name the pin 16 has been changed to). Thereafter, by connecting the pin 16b on the opposite side of the bypass wiring 15 to the pin 19 having the same net name of the block 13, the net name Ne is obtained.
The wiring at t1 can be passed through the block 11.

According to the layout design method according to the first embodiment, since the bypass wiring is arranged in advance in the block through which the wiring passes, when the wiring passes over the block as in the conventional case, the lower level is used. It is not necessary to return to the hierarchy and change the placement and routing in the block and create an area for passing wiring.

Further, when the bypass wiring is arranged in the block, the layout can be verified together with other data in the block. Therefore, even when the bypass wiring is connected in a higher hierarchy, an interval error occurs. Nothing. Therefore, it is not necessary to perform layout verification again on the entire block of the lower hierarchy that has already been verified. In other words, in the upper layer, if only the newly inserted wiring is verified as a connection between blocks, there is no need to check whether an interval error or the like has occurred between the lower blocks, and the layout is duplicated. Verification time can be saved.

Furthermore, the blocks can be passed through the blocks without bypassing the blocks on the wiring path, so that the blocks can be connected with a minimum necessary wiring length. Moreover, it is not necessary to secure a wiring area for bypass wiring, and the surrounding blocks can be arranged closer to each other, so that an increase in chip size can be suppressed.

Further, the variable net name pin added to the end of the bypass wiring is changed by inheriting the net name of the connected wiring. Therefore, when placing the bypass wiring in the block, There is no need to set whether to use as name wiring. Moreover, there is no restriction as to whether or not it is actually used as a passing wiring.
The degree of freedom in layout design can be increased.

[Embodiment 2] As a second embodiment, when a layout design of a standard cell block which is highly versatile and is often reused is performed, a wiring is passed through the standard cell block so that the wiring can pass through the standard cell block. A plurality of bypass wirings may be arranged. In this case as well, when connecting between standard cell blocks and other blocks in the layout design of the upper hierarchy, the wiring is connected to the standard cell block by connecting the wiring to both ends of the bypass wiring arranged in the standard cell block. Can be passed through. As described above, when a plurality of bypass wirings are arranged, a plurality of wirings can be passed through one block, or a bypass wiring having a shorter wiring length can be selected. The degree of freedom can be further increased.

[Third Embodiment] FIG. 3 is a schematic block diagram of a block according to a third embodiment. In the block 21 of the third embodiment, the bypass wiring 25 disposed inside is branched into a plurality of parts in the block, and the ends of the wirings extending from the respective branches protrude from the respective sides of the block. In this example, the ends of the bypass wiring 25 protrude from the four sides of the block 21, and each end has a variable net name inheriting the net name of the connected wiring and changing to the same net name. Pin 26
a, 26b, 26c, 26d are added.

FIG. 4 is a schematic configuration diagram in the case where wiring between blocks is performed using the block 21 configured as shown in FIG. In FIG. 4, the blocks 22 and 23 are arranged at positions sandwiching the block 21 as in FIG.
A configuration in a case where the blocks 22 and 23 are connected by a wiring 28 is shown. First, when connecting the blocks in the upper hierarchy, the wiring 28 connecting the blocks is connected to the pin 26a of the bypass wiring 25 arranged in the lower block. Then, the net names (in this case, Net2) of the pins 26b, 26c, and 26d added to each end of the bypass wiring 25 are changed to the same net name by inheriting the net names of the connected wirings (this net name). Also in this case, what kind of net name the pin 26 has been changed can be confirmed on the display screen.) Thereafter, from the pins 26b to 26d added to the end of the bypass wiring 25, the pin at the position most suitable for connection is selected, and
From this pin, pin 2 with the same net name of block 23
9, the wiring of the net name Net2 is
It can be passed through the block 21 with a minimum necessary wiring length.

According to the layout design method according to the third embodiment, it is possible to arbitrarily select where in the block the wiring 28 connected to the bypass wiring 25 passes and from which pin 26. Can be. That is, the wiring can be passed from any pin added to each end of the bypass wiring 25, so that the degree of freedom in layout design can be further increased.

The number of branches of the bypass wiring and the position of the bypass wiring can be set arbitrarily without being limited to the example of this embodiment.

[0029]

As described above, in the layout design method and the semiconductor device of the semiconductor device according to the present invention, the bypass wiring is previously arranged in the block through which the wiring passes, and the wiring passing through the block is connected to the bypass. Since it is configured with wiring, when passing wiring on a block in a higher hierarchy, return to a lower hierarchy to create an area for passing wiring, or re-enter a block that has already been verified Since the work such as the layout verification is not required, the time required for the layout design can be reduced as compared with the related art. In addition, since the block on the wiring route is not bypassed, the wiring length can be minimized, and a wiring area for the bypass wiring is not required, thereby suppressing an increase in chip size. it can.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a block used in a layout design method according to a first embodiment.

FIG. 2 is a schematic configuration diagram when wiring between blocks is performed using the blocks of FIG. 1;

FIG. 3 is a schematic configuration diagram of a block according to a third embodiment.

FIG. 4 is a schematic configuration diagram when wiring between blocks is performed using the blocks of FIG. 3;

FIG. 5 is a conceptual diagram showing an example of a conventional layout design.

FIG. 6 is a schematic configuration diagram of a block in which a routable area is not continuous.

FIG. 7 is a schematic configuration diagram of a block in which a wirable area is created.

FIG. 8 is a schematic configuration diagram of a block in which an interval error has occurred.

FIG. 9 is a schematic configuration diagram when wiring is performed around a block.

[Explanation of symbols]

 11, 12, 13 Block 14 Data area 15 Bypass wiring 16 Pin with variable net name 17 Wiring area 18 Wiring

Claims (5)

[Claims] 1. A layout block comprising circuit elements, a bypass wiring passing through the layout block is arranged, and a wiring connecting two other layout blocks arranged at positions sandwiching the layout block. Wherein the wiring passes through the layout block, the wiring is configured by a bypass wiring arranged in the layout block. 2. A pin having a variable net name which is inherited from a net name of a connected wiring and is changed to the same net name at an end of the bypass wiring.
The layout design method of the semiconductor device described in the above. 3. The layout design method for a semiconductor device according to claim 1, wherein a plurality of said bypass wirings are arranged in a layout block. 4. The apparatus according to claim 1, wherein said bypass wiring branches into a plurality of parts in a layout block.
Or a layout design method for a semiconductor device according to item 3. 5. A layout block composed of circuit elements, a bypass wiring passing through the layout block is arranged, and a wiring connecting two different layout blocks arranged at positions sandwiching the layout block. Wherein the wiring passing over the layout block is
A semiconductor device comprising a bypass wiring disposed in the layout block.