JPH11136098A - Pulse generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a one-shot pulse generating circuit which outputs a pulse safely with a irreducible delay time even when the load is large or when input pulse width is short. SOLUTION: This circuit 10 consists of two-input waveform NAND circuits 11 and 14, an inverter 12, and an inverter delay circuit 15 consisting of an even number of inverters. An input signal is connected to one input of the 1st NAND circuit 11, the P type MOS transistor 16 of the 2nd NAND circuit 14 consisting of one P type MOS transistor 16 and two N MOS transistors 17 and 18, and to the gate input of the 1st N type MOS transistor 17, and the output signal OSOUT of the inverter 12 for waveform shaping is fed back to the gate of the 2nd N type MOS transistor 18. The output signal of the 2nd NAND circuit 14 is connected to the other input of the NAND circuit 11 through the inverter delay circuit 15, and its output is connected to the input of the inverter 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a pulse generation circuit for generating a one-shot pulse signal.

[0002]

2. Description of the Related Art As a conventional one-shot pulse generating circuit, for example, as shown in FIG. 4, one 2-input NAND circuit 41, an odd number of inverters 42 as a delay circuit, and
There is a one-shot pulse generation circuit 40 which is composed of an output waveform shaping inverter 43 and can easily generate a one-shot pulse.

The one-shot pulse generation circuit 4 shown in FIG.
The operation at 0 will be described with reference to the timing chart shown in FIG. First, regarding the output signal OSOUT output via the dummy load 13, when the load capacity of the dummy load 13 is small, the input signal OSI
When N (FIG. 5A) is "L", the contact L1 (FIG. 5B) which is the output of the odd number of inverter delay circuits 42 is "L".
H ”, the output of the two-input NAND circuit 41 is“
H ", and the output signal OSOUT (FIG. 5C) output from the inverter 43 via the dummy load 13 is" H ".
L ”.

Next, an input signal OSIN (FIG. 5A)
Changes from “L” to “H”, the output signal OSOUT
(FIG. 5C) becomes "H". Next, the contact L1
The output signal OSOUT changes from “H” to “L” (FIG. 5).
(C)) changes from “H” to “L” and one “H”
A level pulse is generated.

When the load capacity of the dummy load 13 is small, a one-shot pulse can be output reliably. However, when the load capacity of the dummy load 13 is large, the output signal is affected by the charging and discharging of the load capacity. OSOUT
As shown in FIG. 5D, the output waveform is rounded to a semicircular waveform.

[0006]

In the conventional one-shot pulse generation circuit 40 shown in FIG. 4, when the output load capacitance shown as the dummy load 13 is large, when the pulse width of the input signal OSIN is short, and when the inverter delay is increased. When the delay time of the circuit 42 is small, the output signal OSOUT of the output signal OSOUT is distorted as shown in the timing chart of FIG.
A one-shot pulse that reliably changes to the H level could not be output, causing a malfunction in the next stage circuit. Also, the output signal OSOUT surely has a logic voltage of "".
To obtain the "H" level, it is possible to cope with the problem by increasing the delay time of the inverter delay circuit 42. However, there has been a problem that the pulse width of the output signal OSOUT becomes longer, which becomes a bottleneck in speeding up.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and performs feedback control by detecting the level of an output signal, so that when the load capacity is large, the output signal can be obtained even if the pulse width of the input signal is short. It is an object of the present invention to provide a pulse generation circuit which can output a signal level with a sufficient potential and can obtain a one-shot pulse with a minimum delay time even when an output load capacitance is small.

[0008]

According to the first aspect of the present invention,
An input line to which an input pulse signal is input is connected to one input terminal of a two-input NAND circuit (11), and a plurality of stages of inverters are connected in series between the other input terminal and the branched input line. And an inverter (12) connected to the output terminal of the NAND circuit (11).
Pulse generation for outputting a logical operation result of the input pulse signal directly input to the ND circuit (11) and the input pulse signal delayed and input by the inverter delay circuit through the inverter as a one-shot pulse signal In the circuit, the inverter delay circuit (15) is composed of an even number of stages of inverters, and a second two-input NAND circuit is provided between the branched input line and the input stage of the inverter delay circuit (15). (14), one of its input terminals is connected to a branch input line, the other input terminal is connected to an output feedback line for branching from the output terminal of the inverter (12), and its output terminal is connected to an inverter delay circuit ( 15), the second NAND circuit (14) includes a P-type MOS transistor (16) and a second , A second N-type MOS transistor (17, 18), and the P-type MOS transistor (16) has its drain electrode connected to the first power supply line and its gate electrode connected to the branched input line. And the source electrode is connected to the inverter delay circuit (15).
To the input stage contact (N3),
The N-type MOS transistor (17) has its drain electrode connected to the input stage contact (N3) of the inverter delay circuit (15), its gate electrode connected to the branched input line, and its source electrode connected to the second input line. The second N-type MOS transistor (18) is connected to a contact (N4) with the drain side of the N-type MOS transistor (18).
The drain electrode is connected to a first N-type MOS transistor (1
7) a source electrode to a contact (N4), a gate electrode of which is branched from the output line of the inverter (12) and a contact (N5) from which an output feedback signal is output, and a source electrode of which is connected to a second power supply. It is characterized by being connected to each line.

[0009] In this case, the above object is achieved, for example, in claim 2.
2. The pulse generation circuit according to claim 1, wherein the second NAND circuit (14) is connected to the P-type M circuit.
The OS transistor (16) is replaced with an inverter (19)
And an inverter (19) having an input terminal connected to the branched input line and an output terminal connected to the base of the NPN transistor (110). The NPN transistor (110) has a collector electrode connected to the first power supply line, and an emitter electrode connected to the drain side of the first N-type MOS transistor (17). N3).

Therefore, according to the pulse generating circuit of the first or second aspect of the present invention, regardless of the input pulse width of the input signal, the logic is generated with the minimum delay time set by the inverter delay circuit (15). A one-shot pulse that reliably changes to the "H" level of the voltage can be generated, and when the load capacity is large, the logic voltage can be reduced with the minimum delay time set by the minimum inverter delay circuit (15). , A one-shot pulse that reliably changes to the "H" level can be generated, and when the load capacity is small, the one-shot pulse is generated with a minimum delay time set by the inverter delay circuit (15). Can be.

As a result, the reliability of the circuit operation can be improved by using the pulse generation circuit of the present invention.

Further, as in the invention described in claim 3,
3. The pulse generation circuit according to claim 1, wherein an internal circuit of said inverter (12) comprises an inverter (3).
1), an NPN transistor (33), and an N-type MOS
A transistor (34), and the inverter (31) has an input terminal connected to the NAND circuit (11).
, The output terminal of which is connected to the base electrode of an NPN transistor (33). The NPN transistor (33) has its collector electrode connected to the first power supply line, and its base electrode To the inverter (3
By connecting to the output terminal of 1) and connecting the emitter electrode thereof to the contact (N5) which is the output point of the output feedback signal, the driving capability of the output signal of the inverter (12) is improved and the NAND circuit (14) ), The output feedback operation to the N-type MOS transistor (18) can be performed at higher speed.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIGS. 1 and 2 show one embodiment of a one-shot pulse generation circuit to which the present invention is applied.

First, the configuration will be described.

FIG. 1 is a diagram showing a circuit configuration of a one-shot pulse generation circuit 10 according to the present embodiment. In FIG. 1, one-shot pulse generation circuit 10 includes two 2
Input NAND circuits 11 and 14 and inverter circuit 12
And an inverter delay circuit 15 composed of an even number of inverters. A capacitive dummy load 13 is connected to the output stage.

The NAND circuit 11 has a negative logic of an input signal OSIN input from an input stage to one input terminal and a delay signal input to the other input terminal after being delayed from the output point N1 of the inverter delay circuit 15. The sum is output to the inverter 12. The inverter 12 is connected to the NAND circuit 1
The waveform of the output signal output from 1 is shaped and the inverted signal is output as the output signal OSOUT via the dummy load 13.

The NAND circuit 14 has one P-type MOS transistor (Metal Oxid
e Semiconductor transistor) 16 and two N-type M
An OS transistor 17, 18, an input line branched from an input line to which an input signal OSIN is input is connected to each gate electrode of the P-type MOS transistor 16 and the N-type MOS transistor 17, and a waveform shaping inverter is provided. The contact N5 of the output stage from which the output feedback signal is output from 12 is connected to the gate electrode of the N-type MOS transistor 18.

The source electrode of the P-type MOS transistor 16 and the drain electrode of the N-type MOS transistor 17 are both connected to a contact N3 with the input stage of the inverter delay circuit 15.
, The drain electrode of the P-type MOS transistor 16 is connected to the first power supply line, and the source electrode of the N-type MOS transistor 18 is connected to the second power supply line.

The first power supply in the figure is a predetermined + side DC power supply voltage supplied to the circuit, and the second power supply voltage is a ground line in the circuit.

That is, the NAND circuit 14 has a circuit configuration including a transistor 141, so that an input signal OSIN input to one input terminal and an output feedback signal of the inverter 12 input to the other input terminal are provided. By taking the NOR of the input signal OSIN, "L"
When the output feedback signal from the inverter delay circuit 15 changes from “L” to “H” due to the change from “H” to “H”, the output N3 changes from “H” to “H” within the delay time of the inverter delay circuit 15. The output N1 of the inverter delay circuit 15 is changed from "H" to "H" by changing from high impedance to "L".
By changing from H ”to“ L ”, a one-shot pulse is generated within a minimum delay time.

The inverter delay circuit 15 is configured by connecting an even number of inverters in series. The inverter delay circuit 15 delays the output signal from the output N3 of the NAND circuit 14 by the number of inverter stages, and outputs the NAND signal 11 from the output N1. Output to the other input terminal.

Next, the operation of the one-shot pulse generation circuit 1 of this embodiment shown in FIG. 1 will be described with reference to the timing chart shown in FIG.

FIG. 2A shows an input signal OSIN input to the one-shot pulse generation circuit 1,
(B) is a contact N which is an output stage of the NAND circuit 14 in FIG.
3, (c) is an output signal output to a contact N1, which is an output stage of the inverter delay circuit 15 in FIG. 1, and (d) is an output signal output from the one-shot pulse generation circuit 1. Output signal OSOUT.

In FIG. 2A, first, the input signal OS
When IN is at the “L” level, one input terminal of the NAND circuit 11 to which the input signal OSIN is input is at the “L” level, and the other input terminal connected to the output contact N1 of the inverter delay circuit 15 is Since it is at “H” level,
The output contact N2 is at the "H" level. Then, the contact N5 of the output of the inverter 12 becomes "L" level, the output signal OSOUT shown in FIG. 2D becomes "L" level and is output, and the output of the inverter 12 outputs the NAND circuit 14 The output feedback signal that is fed back to is also at "L" level. When this output feedback signal is at "L" level, the P-type MOS transistor 16 in the internal circuit 141 of the NAND circuit 14 is turned on, the N-type MOS transistors 17 and 18 are both turned off, and the output contact N3 is shown in FIG. It becomes the “H” level as shown in FIG.

Here, when the input signal OSIN changes to the "H" level in the period T21 shown in FIG.
The P-type MOS transistor 16 in the internal circuit 141 of the AND circuit 14 is OFF, and the N-type MOS transistors 17 and 1
8 are both OFF, and the output contact N3 is in a high impedance state. Further, one input terminal of the NAND circuit 11 to which the input signal OSIN is input is also at the “H” level, and the other input terminal connected to the output contact N1 of the inverter delay circuit 15 remains at the “H” level. , The output contact N2 changes to "L" level. Then, the contact N5 of the output of the inverter 12 also becomes the "H" level, and the output signal OSOUT shown in FIG. 2D also changes to the "H" level in the period T21. The output feedback signal that is fed back also changes to “H” level.

When the output feedback signal changes to "H" level, the N-type MO in the internal circuit 141 of the NAND circuit 14 is
The S-transistor 18 is turned on, and subsequently the N-type MOS transistor 17 is also turned on, and the output contact N3 is changed from "H" level to "L" level in a period T21.

Thereafter, a period from the period T21 to the period T22 in FIG. 2 is a delay period by the inverter delay circuit 15, and during the period T21, the output signal level of the output contact N3 of the NAND circuit 14 is at "H" level. From "L"
The change state to the level is determined by the inverter delay circuit 15.
At the time when the period has shifted to the period T22 due to a delay in the circuit,
The output signal level of the output contact N1 shown in FIG. 2C changes from "H" level to "L" level.

The output contact N of the inverter delay circuit 15
1 is changed from the “H” level to the “L” level by the delay period of the inverter delay circuit 15, so that the output signal at the output contact N2 of the NAND circuit 11 is delayed by the delay time. Only for the duration ”
After maintaining the “L” level, the level changes to the “H” level, and the output signal at the output contact N5 of the inverter 12, that is, the output signal OSOUT shown in FIG. The transition to the “L” level is made at the time of transition to the period T22 after the maintenance, so that the output signal OSOUT output from the one-shot pulse generation circuit 10 has its inverter delay regardless of the pulse width of the input signal. A one-shot pulse that changes from “H” level to “L” level can be output in the minimum delay period of the circuit 15.

Therefore, in FIG. 1, even when the load capacitance of the capacitive load shown as the dummy load 13 is large or the input pulse width of the input signal OSIN is short,
A one-shot pulse that reliably changes to the “H” level of the logic voltage can be generated with a minimum delay time set by the inverter delay circuit 15. The one-shot pulse can be generated with the set minimum delay time, and malfunction of the next-stage circuit connected to the output stage of the one-shot pulse generation circuit 10 can be prevented.

The circuit configuration other than the internal circuit 141 of the NAND circuit 14 shown in FIG.
A circuit configuration indicated by reference numeral 42 is also conceivable. In this circuit configuration, the NPN transistor 110 and the inverter 19 are
A BiNMOS (Bipolar Nitride Met) is incorporated in place of the P-type MOS transistor 16 in the circuit configuration 141.
al Oxide Semiconductor) configuration. The circuit operation is similar to that of the circuit 141.

Therefore, even when the circuit configuration of the NAND circuit 14 is 142, the logic voltage "H" is set at the minimum delay time set by the inverter delay circuit 15 regardless of the input pulse width of the input signal OSIN. A one-shot pulse that reliably changes to the level can be generated, and when the load capacity is large, the logic voltage can be reliably increased to the “H” level with the minimum delay time set by the minimum inverter delay circuit 15. Can be generated, and when the load capacity is small, the one-shot pulse can be generated with the minimum delay time set by the inverter delay circuit 15.

As a result, the reliability of the circuit operation can be improved by using the one-shot pulse generation circuit 10 of the present embodiment.

Next, as in the one-shot pulse generation circuit 10 shown in FIG. 1, the circuit configuration of the NAND circuit 14 is devised so that the influence of the input signal OSIN and the influence of the load capacitance are eliminated. In addition to the one in which the generation of the pulse is ensured, the one in which the circuit configuration of the waveform shaping inverter 32 is further devised, as in the one-shot pulse generation circuit 30 shown in FIG. Is also conceivable.

In the inverter 32 shown in FIG. 3, the inverter 31, the NPN transistor 33, and the N-type MOS
This is an example of a BiNMOS configuration including a transistor 34. Thus, the inverter 32 is connected to the BiNMO
With the S configuration, the driving capability of the output signal OSOUT is improved, and the N-type M shown in FIG.
The output feedback operation to the OS transistor 18 can be performed at higher speed.

By further devising the circuit configuration of the inverter 32, the one-shot pulse generation circuit 3
The circuit operation performance at 0 and the reliability can be further improved.

[0037]

According to the pulse generating circuit of the first or second aspect of the present invention, regardless of the input pulse width of the input signal, the logic is generated with the minimum delay time set by the inverter delay circuit (15). A one-shot pulse that reliably changes to the "H" level of the voltage can be generated, and when the load capacity is large, the logic voltage can be reduced with the minimum delay time set by the minimum inverter delay circuit (15). , A one-shot pulse that reliably changes to the "H" level can be generated, and when the load capacity is small, the one-shot pulse is generated with a minimum delay time set by the inverter delay circuit (15). Can be.

As a result, the reliability of the circuit operation can be improved by using the pulse generation circuit of the present invention.

According to a third aspect of the present invention, in the pulse generating circuit of the first or second aspect, the internal circuit of the inverter (12) comprises an inverter (31) and an NPN transistor (33). ) And N-type M
The inverter (31) has an input terminal connected to the NAND circuit (1).
1), the output terminal of which is connected to the base electrode of an NPN transistor (33). The NPN transistor (33) has its collector electrode connected to the first power supply line. By connecting the base electrode to the output terminal of the inverter (31) and connecting the emitter electrode to the contact (N5), which is the output point of the output feedback signal, the driving capability of the output signal of the inverter (12) is improved. The output feedback operation to the N-type MOS transistor (18) in the NAND circuit (14) can be performed at higher speed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a circuit configuration of a one-shot pulse generation circuit according to an embodiment of the present invention;

FIG. 2 is a timing chart showing an operation in the one-shot pulse generation circuit 10 of FIG.

FIG. 3 is a diagram showing a circuit configuration of a one-shot pulse generation circuit 30 according to another embodiment to which the present invention is applied.

FIG. 4 is a diagram showing a circuit configuration of a conventional one-shot pulse generation circuit 40.

FIG. 5 is a timing chart showing an operation in the one-shot pulse generation circuit 40 of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 One-shot pulse generation circuit 11, 14 NAND circuit 12 Inverter 13 Dummy load 15 Inverter delay circuit 16 P-type MOS transistor 17, 18, 34 N-type MOS transistor 19, 31 Inverter 33, 110 NPN transistor

Claims (3)

[Claims] An input line to which an input pulse signal is input is connected to one input terminal of a two-input NAND circuit (11), and a plurality of stages are provided between the other input terminal and the branched input line. An inverter delay circuit (15) configured by connecting inverters in series is connected, and an inverter (12) is connected to an output terminal of the NAND circuit (11). The NAND circuit (11) is directly input. A pulse generation circuit that outputs a logical operation result of the input pulse signal input to the input pulse signal delayed by an inverter delay circuit and a one-shot pulse signal via the inverter (12); The circuit (15) is composed of an even number of stages of inverters, and the divided input line is connected to the input of the inverter delay circuit (15). Between the stage, the second
, One input terminal of which is connected to a branch input line, and the other input terminal of which is connected to an output feedback line that branches from the output terminal of the inverter (12). A terminal is connected to an input stage of the inverter delay circuit (15). The second NAND circuit (14) includes a P-type MOS transistor (16) and first and second N-type MOS transistors (17, 18), wherein the P-type MOS transistor (16) has its drain electrode connected to the first power supply line, its gate electrode connected to the branched input line, and its source electrode connected to the inverter delay circuit ( 15) respectively connected to the contact (N3) of the input stage. The first N-type MOS transistor (17) has a drain electrode connected to the inverter delay circuit (1). ), Its gate electrode is connected to the branched input line, and its source electrode is connected to the contact (N4) with the drain side of the second N-type MOS transistor (18). The second N-type MOS transistor (18) has a drain electrode connected to a contact (N4) with the source side of the first N-type MOS transistor (17), and a gate electrode connected to the inverter (12). The source electrode is connected to the contact (N5) at which the output feedback signal is output by branching from the output line.
A pulse generation circuit connected to each of the power supply lines. 2. The semiconductor device according to claim 1, wherein the second NAND circuit is configured to output the P-type M
The OS transistor (16) is replaced with an inverter (19)
And an inverter (19) having an input terminal connected to the branched input line and an output terminal connected to the base of the NPN transistor (110). The NPN transistor (110) has a collector electrode connected to the first power supply line, and an emitter electrode connected to the drain side of the first N-type MOS transistor (17). 2. The pulse generation circuit according to claim 1, wherein the pulse generation circuit is connected to N3). 3. An internal circuit of the inverter (12),
Inverter (31) and NPN transistor (33)
And an N-type MOS transistor (34).
The inverter (31) has its input terminal connected to the NAN.
D circuit (11) connected to the output stage, and its output terminal
Connected to the base electrode of the N-type transistor (33);
The PN transistor (33) has its collector electrode connected to the first power supply line, its base electrode connected to the output terminal of the inverter (31), and its emitter electrode connected to the output point of the output feedback signal. 3. The pulse generation circuit according to claim 1, wherein the pulse generation circuit is connected to a contact (N5).