JPH11135920A - Printed wiring board and clock skew control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board by which a skew of a clock signal can be regulated. SOLUTION: Dummy pads 3a to 3c which are each mounted with resistors used for regulating the clock skew of a printed wiring board after it is designed are arranged on clock paths 4a to 4c which connect a clock output circuit 2 to clock input circuits 5a to 5c respectively, the waveforms of clock signals are observed with the input terminal and waveform observing terminal 6a of the clock input circuit, and the skew of clock signals is regulated by changing the propagation delay time with a resistor mouthed on the dummy pad.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board, and more particularly, to a printed wiring board capable of adjusting a skew of a clock signal.

[0002]

2. Description of the Related Art In the prior art, clock skew is adjusted using a variable delay line or the like. JP 6
In JP-A-124137, a fuse is connected to each of the inverters or RC networks connected in multiple stages, and the clock skew is adjusted depending on the position at which the fuse is cut.

In Japanese Patent Application Laid-Open No. 4-340485, clock skew is adjusted using a variable delay line.

Further, in Japanese Patent Application Laid-Open No. 4-346111, clock skew is adjusted using a delay circuit comprising a gate and a selection circuit and capable of changing a delay amount of a clock signal.

[0005]

As described above, in the prior art, there have been methods for adjusting clock skew using a variable delay line or the like or adjusting clock skew by cutting fuses. In each case, the adjustment amount of the clock skew is determined before designing the printed wiring board, and there is no method capable of adjusting the clock skew after designing the printed wiring board.

SUMMARY OF THE INVENTION An object of the present invention is to provide a printed wiring board capable of performing clock skew adjustment after designing a printed wiring board and performing clock skew adjustment with a small number of components, and a clock skew adjustment method therefor. is there.

[0007]

A printed wiring board according to the present invention comprises a clock output circuit, a plurality of clock input circuits, and all of a plurality of clock paths connecting between the clock output circuit and the clock input circuit. With dummy pads for mounting resistors,
Further, the clock input circuit is provided with a waveform observation terminal for observing a waveform.

The clock skew adjusting method according to the present invention is characterized in that a waveform is observed at an input terminal and a waveform observing terminal of a clock input circuit of a printed wiring board, and a propagation delay time is changed by a resistor mounted on a dummy pad. It is characterized by adjusting the clock skew.

[0009]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a printed wiring board according to the present invention. In FIG. 1, a clock output circuit 2 is connected to a clock input circuit 5a via a dummy pad 3a on which a resistor for adjusting clock skew is mounted and a clock path 4a. Similarly, the clock output circuit 2 includes a dummy pad 3b for mounting a resistor for adjusting clock skew and a clock path 4b.
The clock output circuit 2 is connected to the clock input circuit 5b via a dummy pad 3c on which a resistor for adjusting clock skew is mounted and a clock path 4c. Have been.

The clock input circuit 5a is provided with a waveform observation terminal 6a for observing a clock input waveform.

Clock output circuit 2 and clock input circuit 5
a is the dummy pad 3 inserted on the clock path 4a.
a, the clock output circuit 2 and the clock input circuit 5b are separated by a dummy pad 3b inserted on the clock path 4b, and the clock output circuit 2 and the clock input circuit 5c are separated by the clock path 4c. Are separated by the dummy pad 3c inserted into the dummy pad 3c.

Therefore, first, the same resistance value is mounted on all the dummy pads 3a to 3c, and the input terminals of the clock input circuits 5b to 5c and the waveform observation terminal 6a
Is observed, and based on this waveform, a clock path with the most delayed phase is determined as a reference.

Second, for a clock path other than the reference clock path, that is, a clock path having a phase advanced from the reference clock path, a resistance having a larger resistance than the resistance mounted on the reference clock path is mounted. Adjust the clock skew.

When the driving ability of the clock output circuit 2 is the same in the clock paths 4a to 4c, the phase of the circuit having the long line length of the clock path and the large input capacitance of the clock input circuit is the most delayed. Therefore, a clock path having a long line length of the clock path and a large input capacitance of the clock input circuit is used as a reference path, and a resistor having a resistance value larger than the resistance mounted on the reference clock path is set to a dummy pad of another clock path. By mounting, clock skew can be adjusted.

The case where the number of clock input circuits 5a and 5b connected to the clock output circuit 2 will be described.

The clock path 4a and the clock path 4b have the same line length, and the clock input circuits 5a and 5b
If the input capacitances of b are the same, the clock skew should theoretically be zero. However, depending on the configuration of the printed wiring board, it is not always zero due to other factors. In this case, a resistor having the same resistance value is arranged on the dummy pads 3a and 3b, or the dummy pads 3a and 3b are respectively short-circuited. Observe the waveforms at the waveform observation terminal 6a and the input terminal of the clock input circuit 5b,
Check the phase shift. If the phase is not shifted, there is no need to change the resistance value. If the phase of the waveform observation terminal 6a is delayed, the resistance mounted on the dummy pad 3a or 3b is set so that the phase of the waveform observation terminal 6a is advanced or the phase of the input terminal of the clock input circuit 5b is delayed. Change the value and adjust the clock skew.

When the clock path 4a is longer than the clock path 4b and the input capacitances of the clock input circuits 5a and 5b are the same, the phase at the waveform observation terminal 6a of the clock input circuit 5a is generally delayed. Therefore, based on the resistance value mounted on the dummy pad 3a, the clock skew can be adjusted by changing the resistance value mounted on the dummy pad 3b.

The clock paths 4a and 4b have the same length, and the clock input circuit 5a is
When the input capacitance is larger than the input capacitance, the phase at the waveform observation terminal 6a of the clock input circuit 5a is generally delayed. Therefore, based on the resistance value mounted on the dummy pad 3a, the clock skew can be adjusted by changing the resistance value mounted on the dummy pad 3b.

In the case of two or more clock paths, the clock skew can be adjusted by providing a dummy pad and mounting a resistor as described above.

[0021]

As described above, according to the present invention, the clock skew is adjusted after designing a printed wiring board for each of a plurality of clock paths connecting a clock output circuit and a clock input circuit. For the purpose, a dummy pad for mounting a resistor is placed, the waveform is observed at the input terminal of the clock input circuit and the waveform observation terminal, and the clock skew is changed by changing the propagation delay time by the resistor mounted on the dummy pad. Can be adjusted.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a printed wiring board of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Printed wiring board 2 Clock output circuit 3a-3c Dummy pad 4a-4c Clock path 5a-5c Clock input circuit 6a Waveform observation terminal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H05K 3/00 H03K 5/00 K

Claims (8)

[Claims] 1. A printed wiring board on which dummy pads for mounting resistors are arranged for the purpose of adjusting clock skew after design. 2. A dummy for mounting a resistor, provided for each of a plurality of clock paths connected to the clock output circuit, for adjusting a clock skew after design. A printed wiring board having pads arranged thereon. 3. A clock skew is adjusted after designing each of a plurality of clock paths connecting the clock output circuit and the clock input circuit, the circuit including a clock output circuit and a plurality of clock input circuits. A printed wiring board, wherein a dummy pad for mounting a resistor is disposed for the purpose of performing the above. 4. The printed wiring board according to claim 3, further comprising a waveform observation terminal for observing a waveform in one of the plurality of clock input circuits. 5. A printed wiring board comprising: a clock output circuit; and a dummy pad for mounting a resistor, which is disposed on each of a plurality of clock paths connected to the clock output circuit. A clock skew adjustment method comprising: adjusting a clock skew by changing a value of a resistor mounted on the clock skew. 6. A clock output circuit, a plurality of clock input circuits, and all of a plurality of clock paths connecting the clock output circuit and the clock input circuit are arranged on a printed wiring board, respectively. A clock skew adjustment method comprising: a dummy pad for mounting a resistor; and adjusting a clock skew by changing a value of the resistor mounted on the dummy pad. 7. The clock skew adjustment method according to claim 5, wherein a waveform is observed by an input terminal of the clock input circuit, and a clock skew is adjusted by changing a propagation delay time by a mounted resistor. 8. A clock observation circuit for observing a waveform in any one of the plurality of clock input circuits, wherein the waveform is observed by an input terminal of the clock input circuit and the waveform observation terminal and propagated by a mounted resistor. 7. The clock skew adjustment method according to claim 6, wherein the clock skew is adjusted by changing a delay time.