[go: up one dir, main page]

JPH11135526A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH11135526A
JPH11135526A JP29923497A JP29923497A JPH11135526A JP H11135526 A JPH11135526 A JP H11135526A JP 29923497 A JP29923497 A JP 29923497A JP 29923497 A JP29923497 A JP 29923497A JP H11135526 A JPH11135526 A JP H11135526A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor element
mounting substrate
recess
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29923497A
Other languages
Japanese (ja)
Inventor
Isao Hirata
勲夫 平田
Takeshi Kano
武司 加納
Hideo Nakanishi
秀雄 中西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP29923497A priority Critical patent/JPH11135526A/en
Publication of JPH11135526A publication Critical patent/JPH11135526A/en
Pending legal-status Critical Current

Links

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method which can prevent warp in a substrate for mounting a semiconductor, crack of semiconductor device or outbreak of micro-cracking, in manufacturing a semiconductor device installed with the semiconductor element having an electrode for connecting in its center part and capable of high integrality. SOLUTION: A recessed part 11 having an open outlet in its back side for a semiconductor mounting substrate 1 on which the surface circuit is formed, and a through hall 12 which goes through the board 1 in the center part, are formed in a semiconductor mounting substrate 1. A semiconductor device 2 having a connecting electrode 21 in the center part of the first main surface in the center of a first main surface of the board 1, inside the recessed part 11 of the board 1 on the surface of which a main circuit is formed is packaged. After installing the semiconductor in the recessed part 11, when the resin is sealed by injecting the sealing compound from the resin injection passage A2 on the mold A by putting the semiconductor mounting substrate 1 between the molds A and B, the supporting part 5 which supports a second main surface of the semiconductor device 2 is provided so that no gap between the semiconductor device 2 and the mold B exists.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、一主表面の中央部
に接続用の電極を有する半導体素子を半導体実装用基板
に搭載し、樹脂封止してなる半導体装置を製造するため
の方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor element having a connection electrode at the center of one main surface is mounted on a semiconductor mounting substrate and sealed with a resin. Things.

【0002】[0002]

【従来の技術】従来から、ICチップなどの半導体素子
を基板に搭載し、樹脂封止して半導体装置として、各種
タイプのパッケージが広く使用されている。従来の半導
体装置としては、表面の周縁近傍にボンディングのため
の接続用電極を有するタイプの半導体素子を実装するも
のが主流である。その一方、半導体素子には表面の中央
部に接続用電極を有するタイプのものもある。このタイ
プの半導体素子を実装する場合に利用される半導体装置
として、TAB(Tape AutomatedBon
ding),SON(Small Outline N
onleaded−Package),LCC(lea
dless chip carrier)などのパッケ
ージがある。
2. Description of the Related Art Conventionally, various types of packages have been widely used as semiconductor devices in which a semiconductor element such as an IC chip is mounted on a substrate and sealed with a resin. As a conventional semiconductor device, a device in which a semiconductor element having a connection electrode for bonding near a peripheral edge of a surface is mounted is mainly used. On the other hand, some semiconductor elements have a connection electrode at the center of the surface. As a semiconductor device used when mounting this type of semiconductor element, TAB (Tape Automated Bonn) is used.
ding), SON (Small Outline N)
onled-Package), LCC (lea
There is a package such as a dress chip carrier.

【0003】[0003]

【発明が解決しようとする課題】ところで近年、マザー
ボード上に実装される電子部品の高密度化にともない、
半導体の高集積化に対する需要が高まってきている。
In recent years, with the increase in the density of electronic components mounted on a motherboard,
Demand for high integration of semiconductors is increasing.

【0004】本願出願人は、このような需要に応えるべ
く、半導体装置自体の取り扱いが比較的容易であり且つ
実装信頼性が高いLCCに注目し、1997年6月13
日に出願された特願平9−157189号において、高
集積化が可能な半導体装置(LCC)を提案している。
その中では、高集積化が可能であり且つ表面の中央部に
接続用電極を有する半導体素子が実装されるタイプの半
導体装置も提案されている。この半導体装置について、
図6〜9に基づいて説明する。
In order to meet such demands, the applicant of the present application has paid attention to an LCC which is relatively easy to handle the semiconductor device itself and has high mounting reliability.
Japanese Patent Application No. Hei 9-157189, filed on Jan. 10, proposes a semiconductor device (LCC) that can be highly integrated.
Among them, there has been proposed a semiconductor device which can be highly integrated and in which a semiconductor element having a connection electrode at the center of the surface is mounted. About this semiconductor device,
This will be described with reference to FIGS.

【0005】当該半導体装置は、相対向する表裏面を有
する絶縁基板10において、その表面に該表面の縁部か
ら中央部に延びる表面回路14が形成され、裏面の縁部
に表面回路14に対応する裏面回路1が形成され、基板
の側端面に表面回路14と裏面回路15とを繋ぐ端面電
極13が形成され、裏面の中央部に半導体素子2を装着
するための凹部11が形成され、該凹部11の底面中央
部の位置に表裏両側に貫通する、凹部11の開口部より
も開口面積が小さい貫通孔12が形成された半導体実装
用基板1が用いられている。そして、該半導体実装用基
板1の凹部11内に、該凹部11の開口部よりも小さく
貫通孔12の開口部よりも大きい外寸を有し、且つ凹部
11の深さよりも小さい厚みを有しており、一主表面の
中央部に接続用電極21を備えた半導体素子2が装着さ
れている。この半導体素子2は、該半導体素子2の中央
部と貫通孔12の開口部とが一致するようにして上記一
表面を凹部11の底面に接着剤30により固定され、貫
通孔12を通して接続用電極21と半導体実装用基板1
の表面電極14とがボンディングワイヤー8で接続され
ている。このボンディングワイヤー8を封止できるよう
に、貫通孔12内とその表面側開口部の周辺部は封止材
6により樹脂封止されている。そして、該半導体装置
は、マザーボードC上の所定位置に載置し、端面電極1
3をマザーボードC上に設けられた電極と一致させて半
田91にて接合することによりマザーボードC上に実装
される。さらに、図8のように、マザーボードC上に実
装された半導体装置の上には、もう1つの半導体装置を
載置して積み重ねることができ、この場合、導電性を有
する接着剤92などにより、上位の半導体装置の裏面電
極15と下位の半導体装置の表面電極14とを接合する
ことで上下の通電性を確保でき、また、下位の半導体装
置にて硬化した封止材6のうち基板表面よりも上に盛り
上がった部分は、上位の半導体装置の凹部11における
半導体素子2の下側の空間に収まるので、高集積化が可
能となっている。
In the semiconductor device, a front surface circuit 14 extending from an edge of the front surface to a central portion is formed on the front surface of an insulating substrate 10 having opposite front and back surfaces. A back surface circuit 1 is formed, an end surface electrode 13 connecting the front surface circuit 14 and the back surface circuit 15 is formed on a side end surface of the substrate, and a concave portion 11 for mounting the semiconductor element 2 is formed in a central portion of the back surface. A semiconductor mounting substrate 1 is used in which a through hole 12 having a smaller opening area than the opening of the concave portion 11 is formed at the center of the bottom surface of the concave portion 11 and penetrates on both sides thereof. The recess 11 of the semiconductor mounting substrate 1 has an outer dimension smaller than the opening of the recess 11 and larger than the opening of the through hole 12, and has a thickness smaller than the depth of the recess 11. A semiconductor element 2 having a connection electrode 21 is mounted at the center of one main surface. The semiconductor element 2 has one surface fixed to the bottom of the recess 11 with an adhesive 30 so that the center of the semiconductor element 2 and the opening of the through hole 12 coincide with each other. 21 and semiconductor mounting substrate 1
Is connected to the surface electrode 14 by a bonding wire 8. In order to seal the bonding wire 8, the inside of the through hole 12 and the peripheral portion of the opening on the front surface thereof are resin-sealed with a sealing material 6. Then, the semiconductor device is placed at a predetermined position on the motherboard C, and the end face electrode 1
3 is mounted on the motherboard C by matching with the electrodes provided on the motherboard C and joining with solder 91. Further, as shown in FIG. 8, another semiconductor device can be placed and stacked on the semiconductor device mounted on the motherboard C. In this case, a conductive adhesive 92 or the like can be used. By joining the back electrode 15 of the upper semiconductor device and the front electrode 14 of the lower semiconductor device, the upper and lower conductive properties can be secured, and the sealing material 6 cured in the lower semiconductor device can be removed from the surface of the substrate. The raised portion also fits in the space below the semiconductor element 2 in the concave portion 11 of the upper semiconductor device, so that high integration is possible.

【0006】ところで、上記半導体装置では、従来の手
法に従って半導体素子2を搭載した半導体実装用基板1
に樹脂封止を施す場合、図9のような手法により行われ
るのが一般的であろう。すなわち、まず半導体素子2を
搭載した半導体実装用基板1を第一および第二の金型
A,Bの間に挟み、半導体実装用基板1の表面側に対応
する第一の金型Aに設けられた樹脂注入路A2から封止
材6を半導体実装用基板1の貫通孔12へと注入するこ
とにより、樹脂封止が行われる。しかしながらこの場
合、半導体実装用基板1の裏面側は凹部11の周囲が第
二の金型Bにより支持されるのであるが、半導体素子2
と第二の金型Bとの間には隙間を生じる。そのため、樹
脂注入路A2から封止材6を注入する際の注入圧が、半
導体素子2や半導体素子2の中央部において凹部11の
ために薄肉となった薄肉部16を押し下げる応力とな
り、この応力に起因して半導体実装用基板1の反り、あ
るいは半導体素子2の亀裂やマイクロクラックなどの問
題を生じるおそれがあった。
In the above-described semiconductor device, a semiconductor mounting substrate 1 on which a semiconductor element 2 is mounted according to a conventional method.
In general, resin sealing is performed by a method as shown in FIG. That is, first, the semiconductor mounting substrate 1 on which the semiconductor element 2 is mounted is sandwiched between the first and second molds A and B, and provided on the first mold A corresponding to the front surface side of the semiconductor mounting substrate 1. The resin sealing is performed by injecting the sealing material 6 into the through hole 12 of the semiconductor mounting substrate 1 from the resin injection path A2 thus obtained. However, in this case, the periphery of the recess 11 on the back side of the semiconductor mounting substrate 1 is supported by the second mold B.
There is a gap between the second mold B and the second mold B. Therefore, the injection pressure at the time of injecting the sealing material 6 from the resin injection path A2 becomes a stress that pushes down the semiconductor element 2 and the thin portion 16 thinned due to the concave portion 11 in the center of the semiconductor element 2, and this stress is generated. As a result, there is a possibility that problems such as warpage of the semiconductor mounting substrate 1 or cracks and microcracks of the semiconductor element 2 may occur.

【0007】本発明は、そのような問題を解決するため
に、上記の如き、中央部に接続用電極を有する半導体素
子を搭載する、高集積化が可能な半導体装置を製造する
にあたり、半導体実装用基板の反り、半導体素子の亀裂
やマイクロクラックの発生を防止できる製造方法を提供
するものである。
In order to solve such a problem, the present invention is directed to manufacturing a semiconductor device capable of high integration in which a semiconductor element having a connection electrode in the center is mounted as described above. An object of the present invention is to provide a manufacturing method capable of preventing the occurrence of warpage of a substrate for use, cracking of a semiconductor element, and microcracks.

【0008】[0008]

【課題を解決するための手段】上記目的を達するため
に、本発明は、相対向する表裏面を有する絶縁基板にお
いて、少なくともその表面に該表面の縁部から中央部に
延びる表面回路を形成し、裏面の中央部には半導体素子
を装着するための凹部を形成し、該凹部の底面中央部の
位置には表裏両側に貫通する、上記凹部の開口部よりも
開口面積が小さい貫通孔を形成してなる半導体実装用基
板と、上記凹部の開口部よりも小さく上記貫通孔の開口
部よりも大きい外寸を有し、且つ上記凹部の深さよりも
小さい厚みを有しており、相対向する第一及び第二主表
面のうち第一主表面の中央部に接続用電極を備えた半導
体素子とを備えて構成され、上記半導体実装用基板の凹
部内に上記半導体素子が、該半導体素子の中央部と上記
貫通孔の開口部とを一致させて上記第一主表面を上記凹
部の底面に固定することにより装着され、上記貫通孔を
通して上記半導体素子の接続用電極と上記半導体実装用
基板の表面電極とが接続され、さらに、上記貫通孔を通
して接続された上記半導体素子の接続用電極と上記半導
体実装用基板の表面電極との接続部が樹脂封止された半
導体装置を製造する方法として、以下の如き態様の製造
方法が提供される。
In order to achieve the above object, the present invention provides an insulating substrate having opposed front and back surfaces, wherein at least the surface is provided with a surface circuit extending from the edge of the surface to the center. A recess for mounting a semiconductor element is formed in the center of the back surface, and a through hole having a smaller opening area than the opening of the recess is formed at the center of the bottom of the recess on both sides of the front and back. A semiconductor mounting substrate, having an outer dimension smaller than the opening of the concave portion and larger than the opening of the through hole, and having a thickness smaller than the depth of the concave portion. A semiconductor element provided with a connection electrode at the center of the first main surface of the first and second main surfaces, and the semiconductor element is provided in a concave portion of the semiconductor mounting substrate. The center and the opening of the through hole The first main surface is mounted by fixing the first main surface to the bottom surface of the concave portion, and the connection electrode of the semiconductor element and the surface electrode of the semiconductor mounting substrate are connected through the through hole. As a method of manufacturing a semiconductor device in which a connection portion between a connection electrode of the semiconductor element connected through a hole and a surface electrode of the semiconductor mounting substrate is resin-sealed, the following manufacturing method is provided. .

【0009】本発明の第一の態様に係る製造方法は、上
記半導体実装用基板の上記凹部内に上記半導体素子を、
該半導体素子の中央部と上記貫通孔の開口部とを一致さ
せて上記第一主表面を上記凹部の底面に固定することに
より装着するとともに、上記貫通孔を通して上記半導体
素子の接続用電極と上記半導体実装用基板の表面電極と
を接続する半導体搭載工程と、上記貫通孔を通して接続
される上記半導体素子の接続用電極と上記半導体実装用
基板の表面電極との接続部を樹脂封止する封止工程と、
を含む半導体装置の製造方法であって、上記封止工程に
おいて、上記半導体素子が装着された上記半導体実装用
基板を、該半導体実装用基板の表面および裏面側にそれ
ぞれ対応する第一および第二の金型の間に挟み、上記半
導体素子における上記第二主表面を上記半導体実装用基
板の裏面側から支持した状態で、上記第一の金型に設け
られた樹脂注入路から封止材を少なくとも上記半導体実
装用基板の上記貫通孔内に注入することにより樹脂封止
が行われるものである。
In the manufacturing method according to a first aspect of the present invention, the semiconductor element is placed in the recess of the semiconductor mounting substrate.
The semiconductor device is mounted by fixing the first main surface to the bottom surface of the recess by aligning the center portion of the semiconductor element with the opening of the through hole, and connecting the connection electrode of the semiconductor element and the electrode through the through hole. A semiconductor mounting step of connecting the surface electrode of the semiconductor mounting substrate, and sealing for resin-sealing a connection portion between the connection electrode of the semiconductor element connected through the through hole and the surface electrode of the semiconductor mounting substrate. Process and
In the method for manufacturing a semiconductor device, the semiconductor mounting substrate on which the semiconductor element is mounted is, in the sealing step, first and second substrates corresponding to the front and back surfaces of the semiconductor mounting substrate, respectively. In a state where the second main surface of the semiconductor element is supported from the back side of the semiconductor mounting substrate, a sealing material is inserted through a resin injection path provided in the first mold. Resin sealing is performed by injecting at least into the through hole of the semiconductor mounting substrate.

【0010】ここで、上記半導体素子の接続用電極と上
記半導体実装用基板の表面電極との接続部には、上記半
導体素子の接続用電極と上記半導体実装用基板の表面電
極とを接続する配線などが含まれる。
The connecting portion between the connection electrode of the semiconductor element and the front surface electrode of the semiconductor mounting substrate has a wiring connecting the connection electrode of the semiconductor element and the front surface electrode of the semiconductor mounting substrate. And so on.

【0011】この第一の態様に係る製造方法では、上記
半導体素子の上記第二主表面を上記半導体実装用基板の
裏面側から支持した状態で、上記第一の金型に設けられ
た樹脂注入路から封止材を少なくとも上記半導体実装用
基板の上記貫通孔内に注入するので、上記半導体素子は
上記封止材の注入圧により押し下げられることが防止さ
れる。従って、半導体実装用基板の反り、半導体素子の
亀裂やマイクロクラックの発生を防止できる。
[0011] In the manufacturing method according to the first aspect, in a state where the second main surface of the semiconductor element is supported from the back side of the semiconductor mounting substrate, the resin injection provided in the first mold is provided. Since the sealing material is injected at least into the through-hole of the semiconductor mounting substrate from the path, the semiconductor element is prevented from being pushed down by the injection pressure of the sealing material. Therefore, it is possible to prevent the warpage of the semiconductor mounting substrate, the generation of cracks and microcracks in the semiconductor element.

【0012】この場合、上記半導体素子の上記第二主表
面を上記半導体実装用基板の裏面側から支持する手法と
しては、上記半導体実装用基板に搭載された上記半導体
素子と上記第二の金型との間にスぺーサーを設けて隙間
を埋める手法、あるいは上記第二の金型に、上記半導体
実装用基板に搭載された上記半導体素子の第二主表面に
当接する凸部を設ける手法が挙げられる。
In this case, as a method of supporting the second main surface of the semiconductor element from the back side of the semiconductor mounting substrate, the semiconductor element mounted on the semiconductor mounting substrate and the second mold are supported. Or a method of providing a spacer between them and filling the gap, or a method of providing a convex portion in contact with the second main surface of the semiconductor element mounted on the semiconductor mounting substrate on the second mold. No.

【0013】また第一の態様においては、上記半導体搭
載工程において、上記半導体実装用基板の凹部底面と上
記半導体素子の第一主表面とを部分的に接着することに
より、それらの間に隙間が存在する状態で上記半導体素
子を上記凹部内に装着すると好ましい。この場合、上記
貫通孔に注入される封止材が上記凹部底面と上記半導体
素子の間の隙間から上記凹部の側壁と上記半導体素子の
側端面との間の隙間に流れ、これら隙間を充填するの
で、上記半導体素子の第一主表面及び側端面を封止でき
る。
In the first aspect, in the semiconductor mounting step, the bottom surface of the concave portion of the semiconductor mounting substrate and the first main surface of the semiconductor element are partially bonded to form a gap between them. It is preferable that the semiconductor element is mounted in the recess in the state where the semiconductor element is present. In this case, the sealing material injected into the through hole flows from the gap between the bottom surface of the recess and the semiconductor element to the gap between the side wall of the recess and the side end face of the semiconductor element, and fills the gap. Therefore, the first main surface and side end surfaces of the semiconductor element can be sealed.

【0014】さらにこの場合、上記半導体搭載工程の
後、液状封止材を用いて上記半導体実装用基板の凹部底
面と上記半導体素子の第一主表面との間の隙間、および
上記半導体素子の外周端面と上記凹部側壁との間の隙間
を充填し、硬化させた後に、上記封止工程として上述し
た樹脂封止操作を行うようにしてもよい。ここで上記液
状封止材とは、常温で流動性を有する封止材のことであ
る。この場合、上記液状封止材は毛細管現象により凹部
底面と上記半導体素子の第一主表面との間の隙間および
上記半導体素子の外周端面と上記凹部側壁との間の隙間
に送り込まれる。
Further, in this case, after the semiconductor mounting step, the gap between the bottom surface of the concave portion of the semiconductor mounting substrate and the first main surface of the semiconductor element and the outer periphery of the semiconductor element are formed using a liquid sealing material. After filling and curing the gap between the end face and the side wall of the concave portion, the resin sealing operation described above may be performed as the sealing step. Here, the liquid sealing material is a sealing material having fluidity at normal temperature. In this case, the liquid sealing material is fed into the gap between the bottom surface of the concave portion and the first main surface of the semiconductor element and the gap between the outer peripheral end surface of the semiconductor element and the side wall of the concave portion by capillary action.

【0015】本発明の第二の態様に係る製造方法は、上
記半導体実装用基板の上記凹部内に上記半導体素子を、
該半導体素子の中央部と上記貫通孔の開口部とを一致さ
せて上記第一主表面を上記凹部の底面に固定することに
より装着するとともに、上記貫通孔を通して上記半導体
素子の接続用電極と上記半導体実装用基板の表面電極と
を接続する半導体搭載工程と、上記貫通孔を通して接続
される上記半導体素子の接続用電極と上記半導体実装用
基板の表面電極との接続部を樹脂封止する封止工程と、
を含む半導体装置の製造方法であって、上記半導体搭載
工程において、上記半導体実装用基板の凹部底面と上記
半導体素子の第一主表面とを部分的に接着することによ
り、それらの間に隙間が存在する状態で上記半導体素子
が上記凹部内に装着され、上記封止工程においては、液
状封止材を用いて上記半導体実装用基板の凹部底面と上
記半導体素子の第一主表面との間の隙間、および上記半
導体素子の外周端面と上記凹部側壁との間の隙間を充填
し、硬化させる第一の封止工程を行った後、上記半導体
素子が装着された上記半導体実装用基板を、該半導体実
装用基板の表面および裏面側にそれぞれ対応する第一お
よび第二の金型の間に挟んで、上記第一の金型に設けら
れた樹脂注入路から封止材を少なくとも上記半導体実装
用基板の上記貫通孔内に注入する第二の封止工程を行う
ことにより樹脂封止が行われるものである。
In the manufacturing method according to a second aspect of the present invention, the semiconductor element is placed in the recess of the semiconductor mounting substrate.
The semiconductor device is mounted by fixing the first main surface to the bottom surface of the recess by aligning the center portion of the semiconductor element with the opening of the through hole, and connecting the connection electrode of the semiconductor element and the electrode through the through hole. A semiconductor mounting step of connecting the surface electrode of the semiconductor mounting substrate, and sealing for resin-sealing a connection portion between the connection electrode of the semiconductor element connected through the through hole and the surface electrode of the semiconductor mounting substrate. Process and
In the method for manufacturing a semiconductor device, the step of mounting the semiconductor includes partially bonding the bottom surface of the concave portion of the semiconductor mounting substrate and the first main surface of the semiconductor element to form a gap between them. In the presence state, the semiconductor element is mounted in the concave part, and in the sealing step, a liquid sealing material is used between the concave bottom surface of the semiconductor mounting substrate and the first main surface of the semiconductor element. The gap, and the gap between the outer peripheral end face of the semiconductor element and the concave side wall is filled, and after performing a first sealing step of curing, the semiconductor mounting board on which the semiconductor element is mounted is A sealing material is interposed between first and second molds respectively corresponding to the front surface and the back surface of the semiconductor mounting substrate, and at least the sealing material is inserted through a resin injection path provided in the first mold. The above penetration of the substrate In which resin sealing is performed by performing a second sealing step of injecting within.

【0016】この第二の態様に係る製造方法では、上記
半導体搭載工程において上記半導体素子が搭載された上
記半導体実装用基板は、上記第一の封止工程において、
上記液状封止材により上記半導体実装用基板の凹部底面
と上記半導体素子の第一主表面との間の隙間、および上
記半導体素子の外周端面と上記凹部側壁との間の隙間を
充填し、該液状封止材を硬化させることにより、上記半
導体素子の第一主表面及び側端面が封止される。このと
き同時に、上記半導体実装用基板の中央部と上記半導体
素子とは硬化した上記液状封止材により一体化して厚み
が大きくなるので、この部分の強度は向上する。したが
って、その後の第二の封止工程においては、上述の第一
の態様の場合のように上記半導体素子を支持する支持部
を設けなくとも、一体となった上記半導体実装用基板の
中央部と上記半導体素子とは上記第一の金型の樹脂注入
路からの封止材の注入圧を幾分加減すればその圧力に十
分耐えることができる。よって、半導体実装用基板の反
り、半導体素子の亀裂やマイクロクラックの発生を防止
できる。
[0016] In the manufacturing method according to the second aspect, the semiconductor mounting board on which the semiconductor element is mounted in the semiconductor mounting step includes:
The gap between the bottom surface of the recess of the semiconductor mounting substrate and the first main surface of the semiconductor element, and the gap between the outer peripheral end face of the semiconductor element and the sidewall of the recess are filled with the liquid sealing material. By curing the liquid sealing material, the first main surface and side end surfaces of the semiconductor element are sealed. At this time, at the same time, the central portion of the semiconductor mounting substrate and the semiconductor element are integrated with the cured liquid sealing material to increase the thickness, so that the strength of this portion is improved. Therefore, in the subsequent second encapsulation step, even if a support portion for supporting the semiconductor element is not provided as in the case of the above-described first aspect, the central portion of the integrated semiconductor mounting substrate can be formed. The semiconductor element can withstand the pressure sufficiently if the injection pressure of the sealing material from the resin injection path of the first mold is slightly increased or decreased. Therefore, it is possible to prevent the warpage of the semiconductor mounting substrate, the occurrence of cracks in the semiconductor element, and the occurrence of microcracks.

【0017】本発明の第三の態様に係る製造方法は、上
記半導体実装用基板の上記凹部内に上記半導体素子を、
該半導体素子の中央部と上記貫通孔の開口部とを一致さ
せて上記第一主表面を上記凹部の底面に固定することに
より装着するとともに、上記貫通孔を通して上記半導体
素子の接続用電極と上記半導体実装用基板の表面電極と
を接続する半導体搭載工程と、上記貫通孔を通して接続
される上記半導体素子の接続用電極と上記半導体実装用
基板の表面電極との接続部を樹脂封止する封止工程と、
を含む半導体装置の製造方法であって、上記半導体実装
用基板は、その表面周縁部の上に、表裏に開口する枠穴
を中央部に有する枠体を備えており、上記半導体搭載工
程において、上記半導体実装用基板の凹部底面と上記半
導体素子の第一主表面とを部分的に接着することによ
り、それらの間に隙間が存在する状態で上記半導体素子
が上記凹部内に装着され、上記封止工程は、第一の液状
封止材を用いて上記半導体実装用基板の凹部底面と上記
半導体素子の第一主表面との間の隙間、および上記半導
体素子の外周端面と上記凹部側壁との間の隙間を充填
し、硬化させる第一の封止工程と、この第一の封止工程
の後、上記枠体の枠穴に第二の液状封止材を流し込み、
硬化させることにより、上記半導体素子の接続用電極と
上記半導体実装用基板の表面電極との接続部を樹脂封止
する第二の封止工程を含むものである。
According to a third aspect of the present invention, in the manufacturing method, the semiconductor element is placed in the recess of the semiconductor mounting substrate.
The semiconductor device is mounted by fixing the first main surface to the bottom surface of the recess by aligning the center portion of the semiconductor element with the opening of the through hole, and connecting the connection electrode of the semiconductor element and the electrode through the through hole. A semiconductor mounting step of connecting the surface electrode of the semiconductor mounting substrate, and sealing for resin-sealing a connection portion between the connection electrode of the semiconductor element connected through the through hole and the surface electrode of the semiconductor mounting substrate. Process and
In the method of manufacturing a semiconductor device, the semiconductor mounting substrate includes a frame body having a center hole with a frame hole opened on the front and back, on a surface peripheral portion thereof, and in the semiconductor mounting step, By partially bonding the bottom surface of the recess of the semiconductor mounting substrate and the first main surface of the semiconductor element, the semiconductor element is mounted in the recess with a gap between them, and the sealing is performed. The stopping step uses a first liquid sealing material to form a gap between the bottom surface of the concave portion of the semiconductor mounting substrate and the first main surface of the semiconductor element, and the outer peripheral end surface of the semiconductor element and the concave side wall. Filling the gap between, the first sealing step to cure, and after this first sealing step, pour a second liquid sealing material into the frame hole of the frame,
The method includes a second sealing step of resin-sealing a connection portion between the connection electrode of the semiconductor element and the surface electrode of the semiconductor mounting substrate by curing.

【0018】この第三の態様に係る製造方法では、上記
半導体搭載工程において上記半導体素子が搭載された上
記半導体実装用基板は、上記第一の封止工程において、
第一の液状封止材を用いて上記半導体実装用基板の凹部
底面と上記半導体素子の第一主表面との間の隙間、およ
び上記半導体素子の外周端面と上記凹部側壁との間の隙
間を充填し、硬化させることにより、上記半導体素子の
第一主表面及び側端面が封止される。その後、上記第二
の封止工程において、上記枠体の枠穴に第二の液状封止
材を流し込み、硬化させることにより、上記半導体素子
の接続用電極と上記半導体実装用基板の表面電極との接
続部が樹脂封止される。このように、樹脂封止する際に
封止材を充填するための注入圧が必要ないため、上記半
導体実装用基板や上記半導体素子は歪むことがなく、従
って、半導体実装用基板の反り、半導体素子の亀裂やマ
イクロクラックの発生を防止できる。
[0018] In the manufacturing method according to the third aspect, the semiconductor mounting board on which the semiconductor element is mounted in the semiconductor mounting step includes:
The gap between the bottom surface of the recess of the semiconductor mounting substrate and the first main surface of the semiconductor element, and the gap between the outer peripheral end face of the semiconductor element and the sidewall of the recess using the first liquid sealing material. By filling and curing, the first main surface and side end surfaces of the semiconductor element are sealed. Thereafter, in the second sealing step, a second liquid sealing material is poured into the frame hole of the frame body and cured, so that the connection electrode of the semiconductor element and the surface electrode of the semiconductor mounting substrate are formed. Is sealed with resin. As described above, since the injection pressure for filling the sealing material is not required at the time of resin sealing, the semiconductor mounting substrate and the semiconductor element are not distorted. The occurrence of cracks and microcracks in the element can be prevented.

【0019】[0019]

【発明の実施の形態】以下、本発明の実施形態について
説明する。
Embodiments of the present invention will be described below.

【0020】図1の(a)〜(f)は、本発明の第一実
施形態に係る半導体装置の製造方法の工程を示す断面図
である。この第一実施形態について、工程順に沿って順
次説明する。
FIGS. 1A to 1F are sectional views showing steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention. The first embodiment will be described sequentially in the order of steps.

【0021】まず、図1(a)に示すような半導体実装
用基板1を準備する。この半導体実装用基板1は、相対
向する表裏面を有する絶縁基板10において、その表面
に該表面の縁部から中央部に延びる表面回路14が形成
され、裏面の縁部に表面回路14に対応する裏面回路1
が形成され、基板の側端面に表面回路14と裏面回路1
5とを繋ぐ端面電極13が形成され、裏面の中央部に後
述する半導体素子2を装着するための凹部11が形成さ
れ、該凹部11の底面中央部の位置に表裏両側に貫通す
る、凹部11の開口部よりも開口面積が小さい貫通孔1
2が形成された構成となっている。そして、次の半導体
搭載工程の前に、凹部11の底面に後述する半導体素子
2を固定するための接着剤3を塗布しておく。この接着
剤3は、凹部11底面の複数箇所に部分的に塗布され
る。この接着剤3を塗布する箇所は、後述する半導体素
子2を固定する考慮して、バランス良く配置するのがよ
く、またその塗布する箇所の数や面積も、半導体素子2
を固定するに十分な接着強度が得られるのであれば余り
大きくなくても良く、むしろ小さい方が好都合である。
また接着剤3の層の厚みは、半導体素子2と凹部11の
底面との間に、後述する封止材6が流入するに十分な隙
間81ができる程度の大きさとされる。なお、接着剤3
は、凹部11の代わりに、図2に示すように半導体素子
2の第一主表面の縁部に塗布するようにしても構わな
い。
First, a semiconductor mounting substrate 1 as shown in FIG. 1A is prepared. In the substrate 1 for mounting a semiconductor, in an insulating substrate 10 having front and back surfaces opposed to each other, a front surface circuit 14 extending from an edge of the front surface to a center portion is formed on the front surface, and the front surface circuit 14 corresponds to an edge of the back surface. Backside circuit 1
Is formed, and the front surface circuit 14 and the back surface circuit 1 are formed on the side end surface of the substrate.
5, a concave portion 11 for mounting a semiconductor element 2 to be described later is formed in the center of the back surface, and the concave portion 11 penetrates the front and back sides at the center of the bottom surface of the concave portion 11. Through hole 1 having an opening area smaller than that of the opening
2 is formed. Then, before the next semiconductor mounting step, an adhesive 3 for fixing a semiconductor element 2 described later is applied to the bottom surface of the concave portion 11. The adhesive 3 is partially applied to a plurality of locations on the bottom surface of the recess 11. The locations where the adhesive 3 is applied are preferably arranged in a well-balanced manner in consideration of fixing the semiconductor element 2 to be described later.
If it is possible to obtain an adhesive strength sufficient to fix the resin, it need not be so large, but a smaller one is more convenient.
In addition, the thickness of the layer of the adhesive 3 is set to be large enough to form a gap 81 between the semiconductor element 2 and the bottom surface of the recess 11 that is sufficient for the sealing material 6 described later to flow. The adhesive 3
May be applied to the edge of the first main surface of the semiconductor element 2 as shown in FIG.

【0022】図1(b)(c)は半導体素子2を半導体
実装用基板1の凹部内に搭載するための半導体搭載工程
を示している。図示のように、半導体素子2は、凹部1
1の開口部よりも小さく貫通孔12の開口部よりも大き
い外寸を有し、且つ凹部11の深さよりも小さい厚みを
有しており、その第一主表面に接続用電極21を備えて
いる。そして半導体素子2は、該半導体素子2の中央部
と貫通孔12の開口部とが一致するようにして第一主表
面を凹部11の底面に接着剤3により固定される。接着
剤3による半導体素子2を固定する強度は、接続用電極
21と半導体実装用基板1の表面電極14との接続作業
を半導体素子2を脱落させることなく行えるレベル以上
の大きさであれば良く、いわゆる仮接着レベルでも差し
支えない。つまり、後述する封止工程において半導体素
子2は支持部5により支持されるからであり、また最終
的には樹脂封止され凹部11内に強固に固定されるから
である。このとき、上記のように凹部11内に固定され
た半導体素子2の第一主表面と凹部11の底面との間に
は、隙間81が形成され、また半導体素子2の側端面と
凹部11の側壁との間にも隙間82が形成される。
FIGS. 1B and 1C show a semiconductor mounting process for mounting the semiconductor element 2 in the recess of the semiconductor mounting substrate 1. FIG. As shown, the semiconductor element 2 is
1 has an outer dimension smaller than the opening of the through hole 12 and larger than the opening of the through hole 12, and has a thickness smaller than the depth of the concave portion 11. I have. The semiconductor element 2 has its first main surface fixed to the bottom surface of the recess 11 with the adhesive 3 such that the center of the semiconductor element 2 and the opening of the through hole 12 coincide with each other. The strength at which the semiconductor element 2 is fixed by the adhesive 3 may be at least a level at which the connection operation between the connection electrode 21 and the surface electrode 14 of the semiconductor mounting substrate 1 can be performed without dropping the semiconductor element 2. However, a so-called temporary adhesion level may be used. In other words, the reason is that the semiconductor element 2 is supported by the support portion 5 in the sealing step described later, and is finally firmly fixed in the concave portion 11 by resin sealing. At this time, a gap 81 is formed between the first main surface of the semiconductor element 2 fixed in the recess 11 as described above and the bottom surface of the recess 11, and a side end face of the semiconductor element 2 and the recess 11 are formed. A gap 82 is also formed between the side walls.

【0023】そして上記のように凹部11内に半導体素
子2が固定された半導体実装用基板1は、貫通孔12を
通して接続用電極21と半導体実装用基板1の表面電極
14における貫通孔12の近傍部とがボンディングワイ
ヤー4で接続される。
The semiconductor mounting substrate 1 in which the semiconductor element 2 is fixed in the concave portion 11 as described above passes through the through-hole 12 in the vicinity of the connection electrode 21 and the through-hole 12 in the surface electrode 14 of the semiconductor mounting substrate 1. The parts are connected by bonding wires 4.

【0024】図1(d)(e)は上記工程で半導体素子
2を搭載した半導体実装用基板1に対し樹脂封止処理を
行うための封止工程を示している。この封止工程におい
ては、すくなくとも貫通孔12を通して接続される半導
体素子2の接続用電極21と半導体実装用基板1の表面
電極14との接続部、すなわちボンディングワイヤー
4、このボンディングワイヤー4の一端と接続用電極2
1との接合部分、およびボンディングワイヤー4の他端
と表面電極14との接合部分が樹脂封止される。従っ
て、封止材により樹脂封止されるエリアは、少なくとも
貫通孔12内とこの貫通孔12から半導体実装用基板1
表面よりも幾分盛り上がる部分とされる。この封止工程
においては、半導体実装用基板1を、該半導体実装用基
板1の表面および裏面側にそれぞれ対応する第一および
第二の金型A,Bの間に挟んで樹脂封止が行われる。第
一の金属Aは、半導体実装用基板1と接触する側に、貫
通孔12と対応する位置にて窪んだ封止材充填用の成形
空間A1を備え、この凹部A1に通じる樹脂注入路A2
を備えている。
FIGS. 1D and 1E show a sealing process for performing a resin sealing process on the semiconductor mounting substrate 1 on which the semiconductor element 2 is mounted in the above process. In this sealing step, at least a connection portion between the connection electrode 21 of the semiconductor element 2 connected through the through hole 12 and the surface electrode 14 of the semiconductor mounting substrate 1, that is, the bonding wire 4, and one end of the bonding wire 4 Connection electrode 2
1 and the joint between the other end of the bonding wire 4 and the surface electrode 14 are resin-sealed. Therefore, the area to be resin-sealed by the sealing material is at least in the through hole 12 and the semiconductor mounting substrate 1 from the through hole 12.
It is a part that rises slightly from the surface. In this sealing step, resin sealing is performed by sandwiching the semiconductor mounting substrate 1 between the first and second molds A and B corresponding to the front and back surfaces of the semiconductor mounting substrate 1, respectively. Will be The first metal A is provided with a molding space A1 for filling a sealing material which is recessed at a position corresponding to the through hole 12 on a side in contact with the semiconductor mounting substrate 1, and a resin injection path A2 communicating with the recess A1.
It has.

【0025】このとき重要なのは、第二の金型Bと対向
する半導体素子2の二主表面を支持する支持部5を設け
ることである。ここでは、この支持部5として半導体素
子2と第二の金型Bとの間に介在するスペーサー5aが
用いられている。このスペーサーとしては、封止材6を
充填する際の成形温度に耐えるように耐熱材料からなる
ものを用いることが好ましく、例えばシリコーンゴムな
どの耐熱性ゴムやフッ素系樹脂からなる板状材、セラミ
ックスなどの無機質材や金属などからなる板状材が例示
される。このスペーサー5aのサイズは、凹部11の開
口部と略同等の大きさとするのが好ましく、その場合、
充填される封止材6が半導体素子2の第二主表面側や半
導体実装用基板1の裏面側に流れ出るのを防止できる。
なお、支持部5としては、スペーサー5aを用いる代わ
りに、図3に示すごとく、第二の金型Bに半導体素子2
の二主表面を支持する凸部B1を設けることもできる。
What is important at this time is to provide a supporting portion 5 for supporting the two main surfaces of the semiconductor element 2 facing the second mold B. Here, a spacer 5 a interposed between the semiconductor element 2 and the second mold B is used as the support portion 5. As the spacer, it is preferable to use a spacer made of a heat-resistant material so as to withstand the molding temperature at the time of filling the sealing material 6. For example, a plate-shaped material made of a heat-resistant rubber such as silicone rubber, a fluorine-based resin, or a ceramic And a plate-like material made of an inorganic material such as a metal or the like. The size of the spacer 5a is preferably substantially equal to the size of the opening of the recess 11, and in this case,
The filled sealing material 6 can be prevented from flowing out to the second main surface side of the semiconductor element 2 or the back side of the semiconductor mounting substrate 1.
In addition, instead of using the spacer 5a as the support part 5, as shown in FIG.
A convex portion B1 for supporting the two main surfaces can also be provided.

【0026】樹脂封止は、第一および第二の金型A,B
間に半導体実装用基板1を挟み、上記のように半導体素
子2の第二主表面を支持した状態で、第一の金型Aの樹
脂注入路A2から封止材6を成形空間A1に注入し硬化
させることにより行われる。このとき半導体素子2は封
止材6の注入圧により押圧力を受けるが、その第二主表
面が支持されているので変形や歪みを生ずることが無
く、その結果、凹部11のため薄肉となっている半導体
実装用基板1の中央部16の反り、半導体素子の亀裂や
マイクロクラックの発生が防止される。上記のように注
入された封止材6は、成形空間A1および半導体実装用
基板1の貫通孔12内を充填し、さらに半導体素子2の
第一主表面と凹部11の底面との間の隙間81および半
導体素子2の側端面と凹部11の側壁との間の隙間82
へと流入し、これら隙間81、82をも充填する。その
結果、半導体素子2の接続用電極21と半導体実装用基
板1の表面電極14との接続部、すなわちボンディング
ワイヤー4が封止されるとともに、半導体素子2の第一
主表面および側端面も封止される。このようにして、図
1(f)に示すように半導体装置が得られる。この半導
体装置は、図9に示す半導体装置と同様に、マザーボー
ドC上に実装することができるものであり、また、図9
に示すように積み重ねて高集積化することも可能であ
る。
Resin sealing is performed by first and second molds A and B.
The sealing material 6 is injected into the molding space A1 from the resin injection path A2 of the first mold A with the semiconductor mounting substrate 1 interposed therebetween and the second main surface of the semiconductor element 2 supported as described above. And hardening. At this time, the semiconductor element 2 receives a pressing force due to the injection pressure of the sealing material 6. However, since the second main surface thereof is supported, there is no deformation or distortion, and as a result, the recess 11 is thin. Warpage of the central portion 16 of the semiconductor mounting substrate 1, cracking of the semiconductor element and generation of microcracks are prevented. The sealing material 6 injected as described above fills the molding space A1 and the inside of the through hole 12 of the semiconductor mounting substrate 1, and further has a gap between the first main surface of the semiconductor element 2 and the bottom surface of the concave portion 11. 81 and a gap 82 between the side end surface of the semiconductor element 2 and the side wall of the recess 11
To fill the gaps 81 and 82 as well. As a result, the connection between the connection electrode 21 of the semiconductor element 2 and the surface electrode 14 of the semiconductor mounting substrate 1, that is, the bonding wire 4 is sealed, and the first main surface and side end faces of the semiconductor element 2 are also sealed. Is stopped. Thus, a semiconductor device is obtained as shown in FIG. This semiconductor device can be mounted on a motherboard C, similarly to the semiconductor device shown in FIG.
It is also possible to stack and highly integrate as shown in FIG.

【0027】図4の(a)〜(f)は本発明の第二実施
形態に係る製造方法を示す断面図である。この第二実施
形態に係る製造方法について、工程順に沿って説明す
る。なお、この第二実施形態において使用される半導体
実装用基板1および半導体素子2は、第一実施形態と同
様であるので、それらについての説明を省略する。
FIGS. 4A to 4F are cross-sectional views showing a manufacturing method according to the second embodiment of the present invention. The manufacturing method according to the second embodiment will be described in the order of steps. Note that the semiconductor mounting substrate 1 and the semiconductor element 2 used in the second embodiment are the same as those in the first embodiment, and a description thereof will be omitted.

【0028】図4(b)(c)は半導体素子2を半導体
実装用基板1の凹部内に搭載するための半導体搭載工程
を示している。この半導体搭載工程も、第一実施形態と
同様に行われるので、ここでの説明を省略する。
FIGS. 4B and 4C show a semiconductor mounting process for mounting the semiconductor element 2 in the concave portion of the semiconductor mounting substrate 1. FIG. Since the semiconductor mounting process is performed in the same manner as in the first embodiment, the description is omitted here.

【0029】図4(d)(e)は上記工程で半導体素子
2を搭載した半導体実装用基板1に対し樹脂封止処理を
行うための封止工程を示している。第二実施形態におい
て、この封止工程は、図4(d)に示す第一の封止工程
と、図4(e)に示す第二の封止工程とに分けられる。
FIGS. 4D and 4E show a sealing step for performing a resin sealing process on the semiconductor mounting substrate 1 on which the semiconductor element 2 is mounted in the above steps. In the second embodiment, this sealing step is divided into a first sealing step shown in FIG. 4D and a second sealing step shown in FIG.

【0030】まず第一の封止工程においては、液状封止
材61を用いて半導体実装用基板1の凹部11の底面と
半導体素子2の第一主表面との間の隙間81、および半
導体素子2の外周端面と凹部11の側壁との間の隙間8
2を充填し、該液状封止材61を硬化させることによ
り、一次封止が行われる。このとき液状封止材61の隙
間81、82への充填は、次のようにして行うことがで
きる。すなわち該液状封止材61を貫通孔12から半導
体素子2上に供給し、毛細管現象により隙間81から隙
間82へと吸い込ませることにより達成される。このと
き液状封止材61の隙間82からの漏れ出しは、液状封
止材61の表面張力により防止されるのであるが、液状
封止材61を過剰に供給すると漏れ出す恐れがあるの
で、液状封止材61の量は、隙間81、82を充填する
に足りる量とするのがよい。この液状封止材61の適切
な量は、貫通孔12の大きさや隙間81、82の大き
さ、液状封止材61の粘度に依存して決まる。
First, in the first sealing step, a liquid sealing material 61 is used to form a gap 81 between the bottom surface of the concave portion 11 of the semiconductor mounting substrate 1 and the first main surface of the semiconductor element 2, A gap 8 between the outer peripheral end surface of the second and the side wall of the concave portion 11
2 and the liquid sealing material 61 is cured to perform primary sealing. At this time, the filling of the gaps 81 and 82 with the liquid sealing material 61 can be performed as follows. That is, this is achieved by supplying the liquid sealing material 61 onto the semiconductor element 2 from the through hole 12 and sucking the liquid sealing material 61 from the gap 81 to the gap 82 by capillary action. At this time, the leakage of the liquid sealing material 61 from the gap 82 is prevented by the surface tension of the liquid sealing material 61. The amount of the sealing material 61 is preferably set to an amount sufficient to fill the gaps 81 and 82. The appropriate amount of the liquid sealing material 61 is determined depending on the size of the through hole 12, the size of the gaps 81 and 82, and the viscosity of the liquid sealing material 61.

【0031】次に第二の封止工程においては、液状封止
材61で一次封止した後の半導体実装用基板1を、第一
実施形態の場合と同様に、該半導体実装用基板1の表面
および裏面側にそれぞれ対応する第一および第二の金型
A,Bの間に挟んで、第一の金型Aの樹脂注入路A2か
ら封止材62を成形空間A1に注入し硬化させることに
より二次封止が行われる。このとき、第一実施形態の場
合と同様に、半導体素子2の第二主表面を支持するため
の支持部5を設けることもできるが、この第二実施形態
では、一次封止により半導体素子2を半導体実装用基板
1の中央部と強固に一体化しているので、上記支持部5
を設けなくとも封止材62の注入圧に耐えうる強度が付
与されており、支持部5を省いて半導体素子2と第二の
金型Bとの間に隙間がある状態で二次封止を行ってい
る。但しこの場合、支持部5を設ける場合に比べて封止
材62の注入圧を弱くして二次封止することが望まし
い。第二実施形態では、一次封止により半導体素子2と
半導体実装用基板1の中央部ととが強固に一体化し、そ
の強度が向上しているので、半導体実装用基板の反り、
半導体素子の亀裂やマイクロクラックの発生を防止でき
る。
Next, in the second sealing step, the semiconductor mounting substrate 1 after the primary sealing with the liquid sealing material 61 is replaced with the semiconductor mounting substrate 1 in the same manner as in the first embodiment. The sealing material 62 is injected into the molding space A1 from the resin injection path A2 of the first mold A and is cured by being sandwiched between the first and second molds A and B respectively corresponding to the front and back surfaces. Thereby, the secondary sealing is performed. At this time, similarly to the first embodiment, a support portion 5 for supporting the second main surface of the semiconductor element 2 can be provided. However, in the second embodiment, the semiconductor element 2 is primarily sealed. Is firmly integrated with the central portion of the semiconductor mounting substrate 1,
Is provided so as to withstand the injection pressure of the sealing material 62 without providing the sealing member 62, and the secondary sealing is performed in a state where the supporting portion 5 is omitted and there is a gap between the semiconductor element 2 and the second mold B. It is carried out. However, in this case, it is desirable that the injection pressure of the sealing material 62 is weakened as compared with the case where the support portion 5 is provided, and the secondary sealing is performed. In the second embodiment, the semiconductor element 2 and the central portion of the semiconductor mounting substrate 1 are firmly integrated by the primary sealing, and the strength is improved.
The generation of cracks and microcracks in the semiconductor element can be prevented.

【0032】第二実施形態では以上のようにして、図1
(f)に示すように半導体装置が得られるものであり、
該半導体装置は、図6に示す半導体装置と同様に、マザ
ーボードC上に実装することができるものであり、ま
た、図9に示すように積み重ねて高集積化することも可
能である。
In the second embodiment, as described above, FIG.
A semiconductor device is obtained as shown in FIG.
The semiconductor device can be mounted on the motherboard C, similarly to the semiconductor device shown in FIG. 6, and can also be stacked and highly integrated as shown in FIG.

【0033】図5の(a)〜(e)は本発明の第三実施
形態に係る製造方法を示す断面図である。この第三実施
形態に係る製造方法について、工程順に沿って説明す
る。
FIGS. 5A to 5E are cross-sectional views showing a manufacturing method according to the third embodiment of the present invention. The manufacturing method according to the third embodiment will be described in the order of steps.

【0034】この第三実施形態に係る製造方法につい
て、工程順に沿って説明する。第三実施形態において
は、第一実施形態と同様の半導体実装用基板1と半導体
素子2が準備されるが、この半導体実装用基板1はその
上に図5(b)に示される如き枠体7を載せた状態で使
用される。この枠体7は、中央部に表裏に開口する枠穴
を中央部に有する枠穴74を備えた絶縁基板70におい
て、その表面に表面回路72が形成され、裏面の縁部に
表面回路73に対応する裏面回路1が形成され、基板の
側端面に表面回路72と裏面回路73とを繋ぐ端面電極
71が形成された構成となっている。枠体7の表面回路
72、裏面回路73および端面電極71はそれぞれ半導
体実装用基板1の表面回路14、裏面回路15および端
面電極13と対応するように形成されている。そして枠
体7は、該枠体7の裏面回路73と半導体実装用基板1
の表面回路14とを一致させて接続した状態で、半導体
実装用基板1上に載置固定される。ここでは、枠体7を
載置した半導体実装用基板1が以降使用されるが、枠体
7を半導体実装用基板1上に設ける時期は、後述する第
二の封止工程より以前であれば特に限定されない。な
お、半導体実装用基板1と半導体素子2についての説明
は、第一実施形態と同様であるので省略する。
The manufacturing method according to the third embodiment will be described in the order of steps. In the third embodiment, a semiconductor mounting substrate 1 and a semiconductor element 2 similar to those of the first embodiment are prepared, and the semiconductor mounting substrate 1 is provided thereon with a frame as shown in FIG. 7 is used. The frame body 7 has a surface circuit 72 formed on the surface of an insulating substrate 70 having a frame hole 74 having a frame hole opened at the center in the center. A corresponding back surface circuit 1 is formed, and an end surface electrode 71 connecting the front surface circuit 72 and the back surface circuit 73 is formed on a side end surface of the substrate. The front surface circuit 72, the back surface circuit 73, and the end surface electrode 71 of the frame 7 are formed so as to correspond to the front surface circuit 14, the back surface circuit 15, and the end surface electrode 13 of the semiconductor mounting substrate 1, respectively. The frame 7 is formed by connecting the back surface circuit 73 of the frame 7 to the semiconductor mounting substrate 1.
The surface circuit 14 is mounted and fixed on the semiconductor mounting substrate 1 in a state where the surface circuit 14 is aligned and connected. Here, the semiconductor mounting substrate 1 on which the frame 7 is mounted is used thereafter, but the timing at which the frame 7 is provided on the semiconductor mounting substrate 1 is before the second sealing step described later. There is no particular limitation. The description of the semiconductor mounting substrate 1 and the semiconductor element 2 is the same as that of the first embodiment, and thus will not be repeated.

【0035】図5(b)(c)は半導体素子2を半導体
実装用基板1の凹部内に搭載するための半導体搭載工程
を示している。この半導体搭載工程についても、枠体7
を設けた半導体実装用基板1を用いる他は第一実施形態
と同様に行われるので、ここでの説明を省略する。
FIGS. 5B and 5C show a semiconductor mounting process for mounting the semiconductor element 2 in the recess of the semiconductor mounting substrate 1. FIG. Also in this semiconductor mounting process, the frame 7
Except for using the semiconductor mounting substrate 1 provided with, the procedure is performed in the same manner as in the first embodiment, and the description is omitted here.

【0036】図5(d)(e)は上記半導体搭載工程で
半導体素子2を搭載した半導体実装用基板1に対し樹脂
封止処理を行うための封止工程を示している。第三実施
形態において、この封止工程は、図5(d)に示す第一
の封止工程と、図4(e)に示す第二の封止工程とに分
けられる。
FIGS. 5D and 5E show a sealing step for performing a resin sealing process on the semiconductor mounting substrate 1 on which the semiconductor element 2 is mounted in the semiconductor mounting step. In the third embodiment, this sealing step is divided into a first sealing step shown in FIG. 5D and a second sealing step shown in FIG.

【0037】まず上記第一の封止工程においては、第一
の液状封止材63を用いて半導体実装用基板1の凹部1
1の底面と半導体素子2の第一主表面との間の隙間8
1、および半導体素子2の外周端面と凹部11の側壁と
の間の隙間82を充填し、該第一の液状封止材63を硬
化させることにより、一次封止が行われる。この第一の
封止工程は、第二実施形態での第一封止工程の手法と同
様に行うことができるので、より詳細な説明は省略す
る。
First, in the first sealing step, the first liquid sealing material 63 is used to form the recess 1 of the semiconductor mounting substrate 1.
1 between the bottom surface of the semiconductor device 1 and the first main surface of the semiconductor element 2
1 and the gap 82 between the outer peripheral end surface of the semiconductor element 2 and the side wall of the concave portion 11 is filled, and the first liquid sealing material 63 is cured to perform primary sealing. Since the first sealing step can be performed in the same manner as the method of the first sealing step in the second embodiment, a more detailed description will be omitted.

【0038】次に第二の封止工程においては、一次封止
した後の半導体実装用基板1について、枠体7の枠穴7
4に第二の液状封止材64を流し込み、硬化させること
により、半導体素子2の接続用電極21と半導体実装用
基板1の表面電極14との接続部、すなわちボンディン
グワイヤー4を樹脂封止するものである。この第二の液
状封止材64による充填量は、ボンディングワイヤー4
を封止できれば必要以上に多くする必要はない。第三実
施形態では、樹脂封止する際に封止材6を充填するため
の注入圧が必要でないため、半導体実装用基板1や半導
体素子2を歪ませることがなく、従って、半導体実装用
基板1の反り、半導体素子2の亀裂やマイクロクラック
の発生を防止できる。
Next, in the second sealing step, the semiconductor mounting board 1 after the primary sealing is
The connection portion between the connection electrode 21 of the semiconductor element 2 and the surface electrode 14 of the semiconductor mounting substrate 1, that is, the bonding wire 4 is resin-sealed by pouring and curing the second liquid sealing material 64 into the substrate 4. Things. The filling amount of the second liquid sealing material 64 is
If it can be sealed, it is not necessary to increase it more than necessary. In the third embodiment, since the injection pressure for filling the sealing material 6 is not required at the time of resin sealing, the semiconductor mounting substrate 1 and the semiconductor element 2 are not distorted. 1 warpage, cracking of the semiconductor element 2 and generation of microcracks can be prevented.

【0039】第二実施形態では以上のようにして半導体
装置が得られるものであり、該半導体装置は、図6に示
す半導体装置と同様に、マザーボードC上に実装するこ
とができるものであり、また、図9に示す場合に準じ
て、下位の半導体装置の枠体7の上に上位の半導体装置
の半導体実装用基板1を積み重ねることで高集積化する
ことも可能である。
In the second embodiment, a semiconductor device is obtained as described above. This semiconductor device can be mounted on a motherboard C, similarly to the semiconductor device shown in FIG. In addition, according to the case shown in FIG. 9, high integration can be achieved by stacking the semiconductor mounting substrate 1 of the upper semiconductor device on the frame 7 of the lower semiconductor device.

【0040】以上、本発明の実施形態について説明した
が、本発明は上記実施形態に限定されないことは言うま
でもない。
Although the embodiment of the present invention has been described above, it goes without saying that the present invention is not limited to the above embodiment.

【0041】[0041]

【発明の効果】以上説明したように、本発明に係る半導
体装置の製造方法は、上述した3つの態様を含んでいる
が、いずれの態様にあっても、半導体実装用基板の反
り、半導体素子の亀裂やマイクロクラックの発生を防止
できるものである。
As described above, the method of manufacturing a semiconductor device according to the present invention includes the above-described three aspects. In any of the aspects, the warpage of the semiconductor mounting substrate and the semiconductor element Cracks and microcracks can be prevented.

【0042】本発明の第一の態様に係る製造方法では、
半導体素子の第二主表面を半導体実装用基板の裏面側か
ら支持した状態で、上記第一の金型に設けられた樹脂注
入路から封止材を少なくとも上記半導体実装用基板の上
記貫通孔内に注入するので、上記半導体素子は上記封止
材の注入圧により押し下げられることが防止される。従
って、半導体実装用基板の反り、半導体素子の亀裂やマ
イクロクラックの発生を防止できる。この第一の態様で
は、上記半導体搭載工程において、上記半導体実装用基
板の凹部底面と上記半導体素子の第一主表面とを部分的
に接着することにより、それらの間に隙間が存在する状
態で上記半導体素子を上記凹部内に装着すると好まし
く、この場合、上記貫通孔に注入される封止材が上記凹
部底面と上記半導体素子の間の隙間から上記凹部の側壁
と上記半導体素子の側端面との間の隙間に流れ、これら
隙間を充填するので、上記半導体素子の第一主表面及び
側端面を封止できる。
In the production method according to the first aspect of the present invention,
In a state where the second main surface of the semiconductor element is supported from the back side of the semiconductor mounting substrate, at least the sealing material is inserted into the through hole of the semiconductor mounting substrate from the resin injection path provided in the first mold. The semiconductor element is prevented from being pushed down by the injection pressure of the sealing material. Therefore, it is possible to prevent the warpage of the semiconductor mounting substrate, the occurrence of cracks in the semiconductor element, and the occurrence of microcracks. In the first aspect, in the semiconductor mounting step, the bottom surface of the concave portion of the semiconductor mounting substrate and the first main surface of the semiconductor element are partially adhered to each other so that a gap exists between them. It is preferable that the semiconductor element is mounted in the recess. In this case, the sealing material injected into the through-hole is formed by a gap between the bottom surface of the recess and the semiconductor element, and a side wall of the recess and a side end face of the semiconductor element. Flows into and fills these gaps, so that the first main surface and side end faces of the semiconductor element can be sealed.

【0043】本発明の第二の態様に係る製造方法では、
半導体搭載工程において半導体素子が搭載された半導体
実装用基板は、第一の封止工程において、液状封止材に
より半導体実装用基板の凹部底面と半導体素子の第一主
表面との間の隙間、および半導体素子の外周端面と凹部
側壁との間の隙間を充填し、該液状封止材を硬化させる
ことにより、半導体素子の第一主表面及び側端面が封止
される。このとき同時に、半導体実装用基板の中央部と
半導体素子とは硬化した液状封止材により一体化して厚
みが大きくなるので、この部分の強度は向上する。した
がって、その後の第二の封止工程においては、一体とな
った上記半導体実装用基板の中央部と上記半導体素子と
は第一の金型の樹脂注入路からの封止材の注入圧に耐え
ることができるようになり、半導体実装用基板の反り、
半導体素子の亀裂やマイクロクラックの発生を防止でき
る。
In the production method according to the second aspect of the present invention,
The semiconductor mounting substrate on which the semiconductor element is mounted in the semiconductor mounting step, the gap between the bottom surface of the concave portion of the semiconductor mounting substrate and the first main surface of the semiconductor element by a liquid sealing material in the first sealing step, By filling the gap between the outer peripheral end face of the semiconductor element and the side wall of the recess and curing the liquid sealing material, the first main surface and the side end face of the semiconductor element are sealed. At the same time, the central portion of the semiconductor mounting substrate and the semiconductor element are integrated with the cured liquid sealing material to increase the thickness, so that the strength of this portion is improved. Therefore, in the subsequent second sealing step, the central portion of the integrated semiconductor mounting substrate and the semiconductor element withstand the injection pressure of the sealing material from the resin injection path of the first mold. And warp of the semiconductor mounting substrate,
The generation of cracks and microcracks in the semiconductor element can be prevented.

【0044】本発明の第三の態様に係る製造方法では、
半導体搭載工程において半導体素子が搭載された半導体
実装用基板は、第一の封止工程において、第一の液状封
止材を用いて半導体実装用基板の凹部底面と半導体素子
の第一主表面との間の隙間、および半導体素子の外周端
面と凹部側壁との間の隙間を充填し、硬化させることに
より、半導体素子の第一主表面及び側端面が封止され
る。そして、第二の封止工程において、枠体の枠穴に第
二の液状封止材を流し込み、硬化させることにより、半
導体素子の接続用電極と半導体実装用基板の表面電極と
の接続部が樹脂封止される。このように、樹脂封止する
際に封止材を充填するための注入圧が必要ないため、半
導体実装用基板や半導体素子は歪むことがなく、従っ
て、半導体実装用基板の反り、半導体素子の亀裂やマイ
クロクラックの発生を防止できる。
In the manufacturing method according to the third aspect of the present invention,
The semiconductor mounting substrate on which the semiconductor element is mounted in the semiconductor mounting step is, in the first sealing step, using the first liquid sealing material and the concave bottom surface of the semiconductor mounting substrate and the first main surface of the semiconductor element. And the gap between the outer peripheral end face of the semiconductor element and the recess side wall are filled and cured, whereby the first main surface and the side end face of the semiconductor element are sealed. Then, in the second sealing step, the second liquid sealing material is poured into the frame hole of the frame body and cured, so that the connection portion between the connection electrode of the semiconductor element and the surface electrode of the semiconductor mounting substrate is formed. It is sealed with resin. As described above, since the injection pressure for filling the sealing material is not required at the time of resin sealing, the semiconductor mounting substrate and the semiconductor element are not distorted, and therefore, the semiconductor mounting substrate is warped and the semiconductor element is not deformed. The occurrence of cracks and microcracks can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(f)は、本発明の第一実施形態に係
る半導体装置の製造方法の工程を示す断面図である。
FIGS. 1A to 1F are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

【図2】同上実施形態にて半導体実装用基板に接合する
ための接着剤を塗布した半導体素子を示す平面図である
FIG. 2 is a plan view showing a semiconductor element coated with an adhesive for bonding to a semiconductor mounting substrate in the embodiment.

【図3】同上実施形態において、封止工程の変形例を示
す断面図である。
FIG. 3 is a cross-sectional view showing a modification of the sealing step in the embodiment.

【図4】(a)〜(f)は、本発明の第二実施形態に係
る半導体装置の製造方法の工程を示す断面図である。
FIGS. 4A to 4F are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

【図5】(a)〜(e)は、本発明の第三実施形態に係
る半導体装置の製造方法の工程を示す断面図である。
FIGS. 5A to 5E are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

【図6】本発明に係る製造方法を適用できる半導体装置
の一例を示す断面図である。
FIG. 6 is a cross-sectional view showing an example of a semiconductor device to which the manufacturing method according to the present invention can be applied.

【図7】図6に示す半導体装置に用いられる半導体実装
用基板の要部斜視図である
FIG. 7 is a perspective view of an essential part of a semiconductor mounting substrate used in the semiconductor device shown in FIG. 6;

【図8】図6に示す半導体装置を積み重ねた実装状態を
示す断面図である
8 is a cross-sectional view showing a mounted state in which the semiconductor devices shown in FIG. 6 are stacked.

【図9】図6に示す半導体装置を製造する際に従来の手
法により樹脂封止する場合を示す樹脂封止途中の半導体
装置の断面図である
9 is a cross-sectional view of the semiconductor device during resin sealing, showing a case where the semiconductor device shown in FIG. 6 is resin-sealed by a conventional method when manufacturing the semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体実装用基板 10 絶縁基板 11 凹部 12 貫通穴 14 表面回路 2 半導体素子 21 接続用電極 3 接着剤 4 ボンディングワイヤー 5 支持部 5a スペーサー 6 封止材 A 第一の金型 A2 樹脂注入路 B 第二の金型 B1 凸部 Reference Signs List 1 semiconductor mounting substrate 10 insulating substrate 11 concave portion 12 through hole 14 surface circuit 2 semiconductor element 21 connecting electrode 3 adhesive 4 bonding wire 5 supporting portion 5a spacer 6 sealing material A first mold A2 resin injection path B first Second mold B1 convex part

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 相対向する表裏面を有する絶縁基板にお
いて、少なくともその表面に該表面の縁部から中央部に
延びる表面回路を形成し、裏面の中央部には半導体素子
を装着するための凹部を形成し、該凹部の底面中央部の
位置には表裏両側に貫通する、上記凹部の開口部よりも
開口面積が小さい貫通孔を形成してなる半導体実装用基
板の上記凹部内に、上記凹部の開口部よりも小さく上記
貫通孔の開口部よりも大きい外寸を有し、且つ上記凹部
の深さよりも小さい厚みを有しており、相対向する第一
及び第二主表面のうち第一主表面の中央部に接続用電極
を備えた半導体素子を、該半導体素子の中央部と上記貫
通孔の開口部とを一致させて上記第一主表面を上記凹部
の底面に固定することにより装着するとともに、上記貫
通孔を通して上記半導体素子の接続用電極と上記半導体
実装用基板の表面電極とを接続する、半導体搭載工程
と、 さらに、上記貫通孔を通して接続される上記半導体素子
の接続用電極と上記半導体実装用基板の表面電極との接
続部を樹脂封止する、封止工程と、を含む半導体装置の
製造方法であって、 上記封止工程においては、上記半導体素子が装着された
上記半導体実装用基板を、該半導体実装用基板の表面お
よび裏面側にそれぞれ対応する第一および第二の金型の
間に挟み、上記半導体素子における上記第二主表面を上
記半導体実装用基板の裏面側から支持した状態で、上記
第一の金型に設けられた樹脂注入路から封止材を少なく
とも上記半導体実装用基板の上記貫通孔内に注入するこ
とにより樹脂封止が行われることを特徴とする半導体装
置の製造方法。
1. An insulating substrate having opposed front and back surfaces, a surface circuit extending from an edge of the front surface to a central portion is formed on at least the front surface thereof, and a concave portion for mounting a semiconductor element is provided in the central portion of the rear surface. The recess is formed in the recess of the semiconductor mounting substrate, wherein a through hole having a smaller opening area than the opening of the recess is formed at the center of the bottom surface of the recess at both the front and back sides. Having an outer dimension smaller than the opening of the through hole and having a thickness smaller than the depth of the concave portion, and having a thickness smaller than the depth of the concave portion; A semiconductor element having a connection electrode at the center of the main surface is mounted by fixing the first main surface to the bottom surface of the recess so that the center of the semiconductor element and the opening of the through hole are aligned. And the half through the through hole A semiconductor mounting step of connecting a connection electrode of a conductor element and a surface electrode of the semiconductor mounting substrate; and a connection electrode of the semiconductor element and a surface electrode of the semiconductor mounting substrate connected through the through hole. And a sealing step of resin-sealing a connection portion with the semiconductor device. In the sealing step, the semiconductor mounting substrate on which the semiconductor element is mounted is mounted on the semiconductor mounting board. Sandwiched between first and second molds respectively corresponding to the front and back sides of the substrate for mounting, and the second main surface of the semiconductor element is supported from the back side of the semiconductor mounting substrate, A method of manufacturing a semiconductor device, wherein resin sealing is performed by injecting at least a sealing material into at least the through hole of the semiconductor mounting substrate from a resin injection path provided in one mold.
【請求項2】 上記封止工程において、上記半導体実装
用基板に搭載された上記半導体素子と上記第二の金型と
の間に、その間に生じる隙間を埋めるスペーサーを設け
ることにより、上記半導体素子の上記第二主表面が上記
半導体実装用基板の裏面側から支持されることを特徴と
する請求項1記載の半導体装置の製造方法。
2. In the encapsulating step, a spacer is provided between the semiconductor element mounted on the semiconductor mounting substrate and the second mold to fill a gap formed therebetween. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said second main surface is supported from a back side of said semiconductor mounting substrate.
【請求項3】 上記封止工程において、上記第二の金型
に、上記半導体実装用基板に搭載された上記半導体素子
の第二主表面に当接する凸部を設けることにより、上記
半導体素子の上記第二主表面が上記半導体実装用基板の
裏面側から支持されることを特徴とする請求項1記載の
半導体装置の製造方法。
3. In the encapsulating step, the second mold is provided with a convex portion that comes into contact with a second main surface of the semiconductor element mounted on the semiconductor mounting substrate, thereby providing a semiconductor element. 2. The method according to claim 1, wherein the second main surface is supported from a back side of the semiconductor mounting substrate.
【請求項4】 上記半導体搭載工程において、上記半導
体実装用基板の凹部底面と上記半導体素子の第一主表面
とを部分的に接着して、それらの間に隙間が存在する状
態で上記半導体素子が上記凹部内に装着されることを特
徴とする請求項1乃至3いずれか記載の半導体装置の製
造方法。
4. In the semiconductor mounting step, the bottom surface of the concave portion of the semiconductor mounting substrate and the first main surface of the semiconductor element are partially adhered, and the semiconductor element is mounted in a state where a gap exists between them. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is mounted in the recess.
【請求項5】 上記封止工程においては、液状封止材を
用いて上記半導体実装用基板の凹部底面と上記半導体素
子の第一主表面との間の隙間、および上記半導体素子の
外周端面と上記凹部側壁との間の隙間を充填し、硬化さ
せた後、上記金型を用いた樹脂封止を行うことを特徴と
する請求項4記載の半導体装置の製造方法。
5. In the sealing step, a gap is formed between a bottom surface of the concave portion of the semiconductor mounting substrate and a first main surface of the semiconductor element and an outer peripheral end face of the semiconductor element by using a liquid sealing material. 5. The method of manufacturing a semiconductor device according to claim 4, wherein after filling and curing the gap between the recess and the side wall, resin sealing is performed using the mold.
【請求項6】 相対向する表裏面を有する絶縁基板にお
いて、少なくともその表面に該表面の縁部から中央部に
延びる表面回路を形成し、裏面の中央部には半導体素子
を装着するための凹部を形成し、該凹部の底面中央部の
位置には表裏両側に貫通する、上記凹部の開口部よりも
開口面積が小さい貫通孔を形成してなる半導体実装用基
板の上記凹部内に、上記凹部の開口部よりも小さく上記
貫通孔の開口部よりも大きい外寸を有し、且つ上記凹部
の深さよりも小さい厚みを有しており、相対向する第一
及び第二主表面のうち第一主表面の中央部に接続用電極
を備えた半導体素子を、該半導体素子の中央部と上記貫
通孔の開口部とを一致させて上記第一主表面を上記凹部
の底面に固定することにより装着するとともに、上記貫
通孔を通して上記半導体素子の接続用電極と上記半導体
実装用基板の表面電極とを接続する、半導体搭載工程
と、 上記貫通孔を通して接続される上記半導体素子の接続用
電極と上記半導体実装用基板の表面電極との接続部を樹
脂封止する、封止工程と、を含む半導体装置の製造方法
であって、 上記半導体搭載工程において、上記半導体実装用基板の
凹部底面と上記半導体素子の第一主表面とを部分的に接
着することにより、それらの間に隙間が存在する状態で
上記半導体素子が上記凹部内に装着され、 上記封止工程は、液状封止材を用いて上記半導体実装用
基板の凹部底面と上記半導体素子の第一主表面との間の
隙間、および上記半導体素子の外周端面と上記凹部側壁
との間の隙間を充填し、硬化させる第一の封止工程と、
この第一の封止工程の後、上記半導体素子が装着された
上記半導体実装用基板を、該半導体実装用基板の表面お
よび裏面側にそれぞれ対応する第一および第二の金型の
間に挟んで、上記第一の金型に設けられた樹脂注入路か
ら封止材を少なくとも上記半導体実装用基板の上記貫通
孔内に注入するして樹脂封止を行う第二の封止工程を含
むことを特徴とする半導体装置の製造方法。
6. An insulating substrate having opposed front and rear surfaces, a surface circuit extending from an edge of the front surface to a central portion is formed on at least the front surface thereof, and a concave portion for mounting a semiconductor element is provided at a central portion of the rear surface. The recess is formed in the recess of the semiconductor mounting substrate, wherein a through hole having a smaller opening area than the opening of the recess is formed at the center of the bottom surface of the recess at both the front and back sides. Having an outer dimension smaller than the opening of the through hole and having a thickness smaller than the depth of the concave portion, and having a thickness smaller than the depth of the concave portion; A semiconductor element having a connection electrode at the center of the main surface is mounted by fixing the first main surface to the bottom surface of the recess so that the center of the semiconductor element and the opening of the through hole are aligned. And the half through the through hole A semiconductor mounting step of connecting a connection electrode of a conductor element and a surface electrode of the semiconductor mounting substrate; and a step of connecting the connection electrode of the semiconductor element and the surface electrode of the semiconductor mounting substrate connected through the through hole. A method of manufacturing a semiconductor device, comprising: sealing a connection portion with a resin; and a sealing step, wherein in the semiconductor mounting step, a bottom surface of the concave portion of the semiconductor mounting substrate and a first main surface of the semiconductor element are partially The semiconductor element is mounted in the concave portion in a state where a gap is present between the semiconductor device and the semiconductor device by using a liquid sealing material. A first sealing step of filling the gap between the first main surface of the semiconductor element and the gap between the outer peripheral end face of the semiconductor element and the side wall of the recess, and curing the gap.
After the first sealing step, the semiconductor mounting substrate on which the semiconductor element is mounted is sandwiched between first and second molds respectively corresponding to the front and back surfaces of the semiconductor mounting substrate. Including a second sealing step of injecting a sealing material at least into the through hole of the semiconductor mounting substrate from a resin injection path provided in the first mold to perform resin sealing. A method for manufacturing a semiconductor device, comprising:
【請求項7】 相対向する表裏面を有する絶縁基板にお
いて、少なくともその表面に該表面の縁部から中央部に
延びる表面回路を形成し、裏面の中央部には半導体素子
を装着するための凹部を形成し、該凹部の底面中央部の
位置には表裏両側に貫通する、上記凹部の開口部よりも
開口面積が小さい貫通孔を形成してなる半導体実装用基
板の上記凹部内に、上記凹部の開口部よりも小さく上記
貫通孔の開口部よりも大きい外寸を有し、且つ上記凹部
の深さよりも小さい厚みを有しており、相対向する第一
及び第二主表面のうち第一主表面の中央部に接続用電極
を備えた半導体素子を、該半導体素子の中央部と上記貫
通孔の開口部とを一致させて上記第一主表面を上記凹部
の底面に固定することにより装着するとともに、上記貫
通孔を通して上記半導体素子の接続用電極と上記半導体
実装用基板の表面電極とを接続する、半導体搭載工程
と、 上記貫通孔を通して接続される上記半導体素子の接続用
電極と上記半導体実装用基板の表面電極との接続部を樹
脂封止する、封止工程と、を含む半導体装置の製造方法
であって、 上記半導体実装用基板は、その表面周縁部の上に、表裏
に開口する枠穴を中央部に有する枠体を備えており、 上記半導体搭載工程において、上記半導体実装用基板の
凹部底面と上記半導体素子の第一主表面とを部分的に接
着することにより、それらの間に隙間が存在する状態で
上記半導体素子が上記凹部内に装着され、 上記封止工程は、第一の液状封止材を用いて上記半導体
実装用基板の凹部底面と上記半導体素子の第一主表面と
の間の隙間、および上記半導体素子の外周端面と上記凹
部側壁との間の隙間を充填し、硬化させる第一の封止工
程と、この第一の封止工程の後、上記枠体の枠穴に第二
の液状封止材を流し込み、硬化させることにより、上記
半導体素子の接続用電極と上記半導体実装用基板の表面
電極との接続部を樹脂封止する第二の封止工程とを含
む、ことを特徴とする半導体装置の製造方法。
7. An insulating substrate having opposing front and back surfaces, a surface circuit extending from an edge of the front surface to a central portion is formed on at least the front surface thereof, and a concave portion for mounting a semiconductor element is provided at a central portion of the rear surface. The recess is formed in the recess of the semiconductor mounting substrate, wherein a through hole having a smaller opening area than the opening of the recess is formed at the center of the bottom surface of the recess at both the front and back sides. Having an outer dimension smaller than the opening of the through hole and having a thickness smaller than the depth of the concave portion, and having a thickness smaller than the depth of the concave portion; A semiconductor element having a connection electrode at the center of the main surface is mounted by fixing the first main surface to the bottom surface of the recess so that the center of the semiconductor element and the opening of the through hole are aligned. And the half through the through hole A semiconductor mounting step of connecting a connection electrode of a conductor element and a surface electrode of the semiconductor mounting substrate; and a step of connecting the connection electrode of the semiconductor element and the surface electrode of the semiconductor mounting substrate connected through the through hole. A method of manufacturing a semiconductor device, comprising the steps of: sealing a connection portion with a resin; and sealing the connection portion with a resin. A frame body, wherein in the semiconductor mounting step, the bottom surface of the concave portion of the semiconductor mounting substrate and the first main surface of the semiconductor element are partially adhered to each other so that a gap exists between them. The semiconductor element is mounted in the recess, the sealing step is a gap between the bottom surface of the recess of the semiconductor mounting substrate and the first main surface of the semiconductor element using a first liquid sealing material, And the above semiconductor element A first sealing step of filling the gap between the outer peripheral end face and the side wall of the concave portion and curing, and after the first sealing step, a second liquid sealing material is inserted into a frame hole of the frame body. Pouring and curing, including a second sealing step of resin-sealing the connection portion between the connection electrode of the semiconductor element and the surface electrode of the semiconductor mounting substrate, Production method.
JP29923497A 1997-10-31 1997-10-31 Manufacture of semiconductor device Pending JPH11135526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29923497A JPH11135526A (en) 1997-10-31 1997-10-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29923497A JPH11135526A (en) 1997-10-31 1997-10-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH11135526A true JPH11135526A (en) 1999-05-21

Family

ID=17869890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29923497A Pending JPH11135526A (en) 1997-10-31 1997-10-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH11135526A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100311826B1 (en) * 1999-12-18 2001-10-17 이형도 Method for hermetic packaging in microsensors
WO2018097410A1 (en) * 2016-11-28 2018-05-31 주식회사 네패스 Semiconductor package having reliability and method for producing same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100311826B1 (en) * 1999-12-18 2001-10-17 이형도 Method for hermetic packaging in microsensors
WO2018097410A1 (en) * 2016-11-28 2018-05-31 주식회사 네패스 Semiconductor package having reliability and method for producing same
WO2018097409A1 (en) * 2016-11-28 2018-05-31 주식회사 네패스 Semiconductor package produced using insulation frame, and method for producing same
WO2018097413A1 (en) * 2016-11-28 2018-05-31 주식회사 네패스 Semiconductor package and method for producing same
WO2018097412A1 (en) * 2016-11-28 2018-05-31 주식회사 네패스 Chip package and method for producing same
KR20180060891A (en) * 2016-11-28 2018-06-07 주식회사 네패스 Semiconductor Package having Reliability and Method of manufacturing the same
KR20180060896A (en) * 2016-11-28 2018-06-07 주식회사 네패스 Chip Package and Method of manufacturing the same
KR101870164B1 (en) * 2016-11-28 2018-07-19 주식회사 네패스 Chip Package and Method of manufacturing the same
US11062990B2 (en) 2016-11-28 2021-07-13 Nepes Laweh Corporation Semiconductor package of using insulating frame

Similar Documents

Publication Publication Date Title
KR100341104B1 (en) semiconductor device assembly method and semiconductor device produced by the method
US6118184A (en) Semiconductor device sealed with a sealing resin and including structure to balance sealing resin flow
US8304883B2 (en) Semiconductor device having multiple semiconductor elements
US6498055B2 (en) Semiconductor device, method of manufacturing semiconductor device, resin molding die, and semiconductor manufacturing system
JP3194917B2 (en) Resin sealing method
JPH08236584A (en) Semiconductor device
JP3683996B2 (en) Semiconductor device and manufacturing method thereof
KR20050063700A (en) A manufacturing method of a semiconductor device
KR20050119414A (en) Stacked package comprising two edge pad-type semiconductor chips and method of manufacturing the same
JP2001203227A (en) Resin sealing method and resin sealing device
JP2002368028A (en) Semiconductor package and manufacturing method thereof
TW201401459A (en) Semiconductor device manufacturing method and semiconductor device
JP2003170465A (en) Semiconductor package manufacturing method and sealing mold therefor
JP2000124344A (en) Resin-sealed semiconductor device and method of manufacturing the same
CN101635280B (en) Window type ball grid array package structure and manufacturing method thereof
JPH11135526A (en) Manufacture of semiconductor device
JP3226244B2 (en) Resin-sealed semiconductor device
JPH07321138A (en) Ultra-thin semiconductor package and manufacturing method thereof
JP2002270627A (en) Method for manufacturing semiconductor device
CN115394743A (en) Semiconductor packaging device, frame product and manufacturing method thereof
JP5058144B2 (en) Resin sealing method for semiconductor element
KR100818530B1 (en) Manufacturing method of semiconductor package mold and semiconductor chip package
JP4408015B2 (en) Manufacturing method of semiconductor device
CN100592506C (en) Non-planar substrate strip and method for packaging semiconductor
JP3272889B2 (en) Method for manufacturing semiconductor device