JPH11135515A - Structure and manufacturing method of semiconductor device - Google Patents

Abstract

(57) Abstract: Provided is a semiconductor device in which the resistance between an emitter and a base in a self-aligned transistor does not increase and the emitter resistance is reduced to improve high frequency characteristics suitable for fine processing of an electrode. An N ⁺ buried layer (2) is formed on a P ^- silicon substrate (1).
N ^- has a collector layer 3 N ^- has a high concentration collector layer 4 to the collector layer N ^- P ⁺ external base 5 to the collector layer, N ⁺ emitter P intrinsic base 6, in P intrinsic base on its inner side 7 and a boron-introduced first polysilicon 10 connecting the P ⁺ external base and the electrode 18, wherein the first polysilicon is P ⁺
100 nm on the external base, otherwise 200 nm. The base extraction electrode polysilicon is thinner near the contact hole where the intrinsic base and the emitter are formed, the silicon oxide film remains on the third polysilicon, and the resistance between the emitter and the base does not increase. Since the third polysilicon has high frequency characteristics and contains a high concentration of N-type impurities, the emitter resistance is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a bipolar transistor.

[0002]

2. Description of the Related Art Devices used for low-noise amplifiers and pre-driver amplifiers in mobile communication terminals such as mobile phones are required to have high gain, low noise, and low price. As a silicon bipolar transistor, in particular, a self-aligned silicon bipolar transistor is often used as a device for high gain and low noise. The structure of a conventional self-aligned bipolar transistor will be described below.

FIG. 6 is a longitudinal sectional view showing a configuration of a semiconductor device described in Japanese Patent Laid-Open No. 8-8351. Referring to FIG. 5, this conventional semiconductor device has an N + buried layer 2 and an N− epitaxial layer 3 on a P− type silicon substrate 1, and the N− epitaxial layer 3 is separated by a field insulating film 32. , N-epitaxial layer 3, a P-type intrinsic base 6 and a first
P + external base 5 for connecting the polysilicon film 10 to the P-type intrinsic base 6 and the second polysilicon film 9, and the first polysilicon film 10 and the first silicon nitride film 11 Has a contact hole for connection with the N + emitter 7 and the P intrinsic base 6, and has a first sidewall 2 on the side wall of the contact hole in the P intrinsic base region 6.
3 has an N + emitter 7 as an isolation film, and has an N + emitter electrode 15 on the contact hole and the first silicon nitride film 11.

In order to further improve the high frequency characteristics of the conventional self-aligned transistor having the configuration shown in FIG.
It is necessary to reduce the size of the emitter contact, reduce the capacitance, and reduce the base resistance. However, in this case, the coverage of the N + -type emitter electrode 33 on the contact hole is deteriorated, the current density flowing through the N + -type emitter electrode 33 at the step is increased, and electromigration is performed.
There is a problem that the device life is shortened.

In order to solve this problem, for example, Japanese Patent Laid-Open No. 5-175206 discloses a method of improving the flatness of an emitter electrode window and improving the step coverage of an emitter electrode wiring film. A self-aligned bipolar transistor as shown in FIG.

Referring to FIG. 6, this bipolar transistor is a self-aligned transistor like the transistor shown in FIG. 5, but has a second polysilicon film 28 buried in a contact hole. An emitter electrode wiring 30 is provided on the third polysilicon film 29. For this reason, the contact hole is flattened,
The increase in current density that shortens the life of the transistor as in the first prior art does not occur.

[0007]

By the way, the above-mentioned Japanese Patent Application Laid-Open No. 8-8351 does not specify a metallizing step, but originally, after the step shown in FIG. In order to connect the transistors and passive elements, an insulating film such as a silicon oxide film should be formed, and a connection hole should be formed on the first polysilicon 10 and the N + emitter electrode 33.

At this time, in the conventional semiconductor device described with reference to FIG. 6, the silicon oxide film on the N + emitter electrode 33 has a first thickness due to the influence of the step of the contact hole.
The step difference of the contact hole becomes thicker than on the polysilicon 10. Therefore, if the connection hole is formed by dry etching at the same time, the first polysilicon 10 is over-etched, the polysilicon in the connection hole portion of the first polysilicon 10 disappears, and a current flows through the P intrinsic base 6. There is a problem that the transistor is not operated because it is not supplied.

When the silicon oxide film is etched so that the polysilicon in the connection hole portion of the first polysilicon 10 is not lost, the silicon oxide film remains on the N + type emitter electrode 33 and the resistance between the emitter and the base is reduced. And the high frequency characteristics are degraded.

On the other hand, Japanese Patent Laid-Open No. 5-175206 discloses
In the semiconductor device proposed in Japanese Patent Application Laid-Open Publication No. H10-260, the contact holes are flattened, so that the problem seen in the conventional semiconductor device shown in FIG. 6 does not occur. However, referring to FIG. 7, an N + impurity is directly introduced into the P intrinsic base region 6 by an ion implantation method, and the second polysilicon film 2 is formed.
Since the second polysilicon film 28 is formed non-doped, the second polysilicon film 28 has a problem that the resistance is extremely high, the emitter resistance is high, and the high frequency characteristics are deteriorated.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above problems, and has as its object the purpose of the present invention.
It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which do not increase the resistance between bases and have good high frequency characteristics. Another object of the present invention is to provide a semiconductor device having a small emitter resistance and improving high-frequency characteristics. Still another object of the present invention is to provide a semiconductor device suitable for fine processing of an electrode.

[0012]

In order to achieve the above-mentioned object, a semiconductor device according to the present invention comprises a first conductive type semiconductor substrate, a second conductive type collector lead region,
A second conductive type collector is drawn over the region serving as a collector drawer.
A conductive type collector region and a base-leading polysilicon having a first conductivity-type impurity introduced on the collector region, and a silicon nitride film on the base-leading polysilicon having the first conductivity-type impurity introduced thereon; A contact hole formed in the base-leading polysilicon and the silicon nitride film into which the impurity of the first conductivity type is introduced, a base region of the first conductivity type formed below the contact hole, and an oxide film on the side wall of the contact hole. In a self-aligned bipolar transistor having a sidewall made of a nitride film, an emitter region of a second conductivity type with a sidewall in a base region, and emitter polysilicon on the emitter region,
The thickness of the base lead-out polysilicon in the contact hole portion is smaller than the thickness of the base lead-out polysilicon other than the contact hole portion.

[0013]

Embodiments of the present invention will be described. In a preferred embodiment of the semiconductor device of the present invention, referring to FIG. 1, a P-silicon substrate (1)
An N + buried layer (2) on the N + buried layer (2), an N-collector layer (3) on the N + buried layer (2), and phosphorus in the N-collector layer (3) for reducing a Kirk effect. Having a high concentration collector layer (4) and an N-collector layer (3).
There is a P + external base (5) for reducing the base resistance inside, and a P-type impurity (boron) containing P-type impurity (boron) inside.
It has an intrinsic base (6). And P intrinsic base (6)
The first polysilicon (base lead) has an N + emitter (7) and has a P-type impurity (boron) introduced by an ion implantation method to connect the P + external base (5) and the electrode (18). The first polysilicon (10) has a thickness of, for example, 100 nm on the P + external base (5), and has a thickness of, for example, 200 nm otherwise.

According to the embodiment of the present invention, since the base extraction electrode polysilicon is thinner near the contact hole for forming the intrinsic base and the emitter than the other portions, the third polysilicon ( 16) The silicon oxide film (17) remains on the surface, the resistance between the emitter and the base does not increase, and the device has good high-frequency characteristics.

Further, since the third polysilicon 16 contains a high concentration of N-type impurities, the emitter resistance can be reduced.

Further, even if the contact hole becomes finer, the thickness of the polysilicon around the contact hole becomes effectively thinner, so that N-type impurities are more easily introduced into the P intrinsic base (6), and the high-frequency characteristics are improved. I do.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a longitudinal sectional view schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention. Referring to FIG. 1, a low resistance N + buried layer 2 is provided on a P− silicon substrate 1, and a specific resistance is 1 to 3Ω on the N + buried layer 2.
The N-collector layer 3 has a thickness of about 1.0 μm in (ohms) · cm. Also, a high-concentration collector layer having a first silicon oxide film 8 for element isolation and containing 1 to 7 × 10 ¹⁵ cm ⁻³ of phosphorus in the N + collector layer 3 for reducing a Kirk effect. A P + external base 5 for reducing base resistance in the N− collector layer 3;
In addition, a P intrinsic base 6 containing boron at a concentration of 1 to 3 × 10 ¹⁸ cm ⁻³ is provided inside.

In the P intrinsic base 6, 1 to 5 × 1 arsenic is contained.
It has an N + emitter 7 containing a concentration of 0 ²⁰ cm ^-3 .

Further, there is provided a low-resistance first polysilicon 10 into which boron is introduced by an ion implantation method for connecting the P + external base 5 and the electrode 18. First polysilicon 1
0 means that the film thickness is 100 n on the P + external base 5
m, otherwise 200 nm.

In order to form the N + emitter 7 as shallow as possible, the third polysilicon 16 and the first polysilicon 10 to be formed by solid layer diffusion, and the side for separating the N + emitter 7 and the P intrinsic base 6 are formed. As a wall, the second silicon oxide film 12 and the second silicon nitride film 1
3, third silicon oxide film 14, third silicon nitride film 1
5. The first silicon nitride film 11 is provided. Further, a fourth silicon nitride film 17 having a thickness of 400 nm is provided on the first silicon nitride film 11 and the third polysilicon 16.

On the first polysilicon 10 and the third polysilicon 16, there is provided an electrode 18 made of an Al—Si—Cu alloy and a barrier metal and having a thickness of 500 nm and a width of 1 μm.

Next, the manufacturing method of the first embodiment shown in FIG. 1 will be described with reference to the drawings.

FIGS. 2 and 3 are longitudinal sectional views showing major steps in the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

First, as shown in FIG. 2A, an oxide film having a thickness of 400 nm is grown on a P-silicon substrate by a thermal oxidation process and patterned by a photolithography process. Arsenic is implanted using the patterned oxide film as a mask,
A heat treatment is performed at 100 degrees for about 20 minutes to activate arsenic, and the oxide film is removed with a hydrofluoric acid-based etchant. Thus, an N + buried layer 2 is formed.

Subsequently, the N-collector layer 3 doped with phosphorus is epitaxially grown.

Next, a silicon oxide film is grown, the oxide film is removed only in a region for connecting the N-collector layer 3 and the substrate surface, phosphorus diffusion is performed, and a collector pulling region is formed.

After removing the entire surface of the oxide film, a first silicon oxide film 8 for device isolation is grown to a thickness of 400 nm again.

Next, the first polysilicon 10 is deposited to a thickness of 20
The first polysilicon 10 is grown by a 0 nm CVD method, and boron is introduced into the first polysilicon 10 by an ion implantation method.

Subsequently, in a photolithography process,
A second base for forming the P intrinsic base 6 and the N + emitter 7
An opening resist pattern having a width of 0.5 μm wider on each side than the contact hole (described later) is formed, and in the dry etching step, as shown in FIG. 2B, half of the thickness of the first polysilicon 10 is formed. Etch only 100 nm
Is formed, and the photoresist 18 is removed.

Thereafter, the first silicon nitride film 11 is
The second contact hole 2 grown by the 20 nm CVD method and having a width of 0.5 μm narrower than that of the first contact hole 19 formed in the step shown in FIG. 2B and having a width of 0.8 μm and a length of 20 μm.
0 is formed by photolithography and dry etching.

Subsequently, phosphorus is ion-implanted with a photoresist mask to form a high concentration collector layer 4.

Further, a first silicon oxide film 12 having a thickness of 10 nm is grown by a thermal oxidation method. At this time, boron of the first polysilicon 10 is thermally diffused to form the P + external base 5.

Subsequently, through the first silicon oxide film 12,
BF ₂ is ion-implanted to form a P intrinsic base 6 (see FIG. 3C).

Next, a second silicon nitride film is grown to a thickness of 120 nm by CVD to form a sidewall.
Etch back by RIE. As a result, sidewalls are formed by the second silicon nitride film 13 and the second silicon oxide film 12. At this time, the third silicon nitride film 15 is also formed.

Subsequently, a third polysilicon is grown to a thickness of 200 nm by a CVD method, arsenic is introduced by an ion implantation method, and a heat treatment is performed at 1000 to 1050 ° C. by a lamp annealing method. Thereby, N + emitter 7 is formed. afterwards,
The third polysilicon is patterned. This situation,
It is shown in FIG.

Further, as shown in FIG. 1, a fourth silicon oxide film 17 and an electrode 18 are formed.

Next, a second embodiment of the present invention will be described. FIG. 4 is a longitudinal sectional view showing the configuration of the semiconductor device according to the second embodiment of the present invention. In this embodiment, the N + emitter 7
Is formed in the contact hole, and has a first buried polysilicon 21.

FIG. 5 is a longitudinal sectional view showing the main steps of a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

As shown in FIG. 5A, the process up to the formation of the side wall is the same as that of the first embodiment.
The thickness of the first buried polysilicon 21 is 3
Then, arsenic is introduced by ion implantation under the same conditions as in the first embodiment, and a second buried polysilicon 22 is grown by 300 nm by LPCVD and arsenic is first implanted by ion implantation. It is introduced under the same conditions as polysilicon, and is etched back by RIE. As a result, the polysilicon is buried as shown in FIG. The subsequent manufacturing method is the same as in the first embodiment.

In the second embodiment of the present invention, the electrode is flattened by the first buried polysilicon, so that the electrode is excellent in fine workability.

[0042]

As described above, according to the present invention, the following effects can be obtained.

The first effect of the present invention is that the base polysilicon for the lead extraction electrode is thinner than the other portions near the contact hole where the intrinsic base and the emitter are formed, so that the third polysilicon is used. That is, since the silicon oxide film remains on the film, the resistance between the emitter and the base does not increase and the device has good high-frequency characteristics.

The second effect of the present invention is that the third polysilicon contains a high concentration of N-type impurities, so that the emitter resistance can be reduced and the contact hole can be reduced even if it becomes fine. Since the thickness of the polysilicon around the contact hole is effectively reduced, N-type impurities are more easily introduced into the P intrinsic base, and the high-frequency characteristics are improved.

Further, a third effect of the present invention is that excellent flatness of electrodes can be achieved because the surface is flattened by the first buried polysilicon.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a configuration of a semiconductor device according to a first example of the present invention.

FIG. 2 is a longitudinal sectional view for explaining a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a longitudinal sectional view for explaining a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a longitudinal sectional view showing a configuration of a semiconductor device according to a second example of the present invention.

FIG. 5 is a longitudinal sectional view for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 6 is a longitudinal sectional view showing a configuration of a conventional semiconductor device.

FIG. 7 is a longitudinal sectional view showing the configuration of another conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 P-silicon substrate 2 N + buried layer 3 N-collector layer 4 high-concentration collector layer 5 P + external base 6 P intrinsic base 7 N + emitter 8 first silicon oxide film 9 second polysilicon 10 first polysilicon 11 first Silicon nitride film 12 Second silicon oxide film 13 Second silicon nitride film 14 Third silicon oxide film 15 Third silicon nitride film 16 Third polysilicon 17 Fourth silicon oxide film 18 Electrode 19 First contact hole 20 First contact hole Reference Signs List 21 first buried polysilicon 22 second buried polysilicon 23 first sidewall 24 fifth silicon oxide film 25 Ti silicide film 27 field oxide film 28 second polysilicon 29 third polysilicon 30 emitter electrode wiring 31 emitter electrode wiring Film 32 field insulating film 33 N + D Jitter electrode

Claims (4)

[Claims] A first conductive type collector lead-out region on the first conductive type semiconductor substrate; and a second conductive type collector lead-out region on the second conductive type collector lead-out region.
A conductive type collector region, a base lead-out polysilicon in which a first conductive type impurity is introduced on the collector region, and a silicon nitride film on the base lead-out polysilicon in which the first conductive type impurity is introduced. A contact hole formed in the base-leading polysilicon doped with the first conductivity type impurity and the silicon nitride film; a first conductivity type base region formed below the contact hole; A self-aligned bipolar transistor having: a sidewall made of an oxide film and a nitride film on the side wall of a hole; an emitter region of a second conductivity type in the base region with the sidewall therebetween; and emitter polysilicon on the emitter region. In the transistor, the thickness of the base-leading polysilicon in the contact hole portion is equal to the thickness of the contact hole. Thinner than the thickness of the base leading poly-silicon other than the minute, and wherein a. 2. The semiconductor device according to claim 1, wherein said emitter polysilicon is buried in said contact hole. 3. A semiconductor device including a self-aligned bipolar transistor, characterized in that the base-leading polysilicon has a smaller thickness near the contact hole where the intrinsic base and the emitter are formed than at other portions. Semiconductor device. (A) forming a second conductivity type buried layer on the first conductivity type semiconductor substrate, forming a second conductivity type collector layer, and then forming a collector pull-up region; b) forming a first polysilicon having a predetermined thickness into which first conductivity type impurities are introduced, and (c) etching a half of the thickness of the first polysilicon to form a first contact hole. (D) forming a first silicon nitride film;
Forming a second contact hole narrower than the opening diameter of the first contact hole at the position of the first contact hole in the silicon nitride film and the first polysilicon; and (e) the second conductivity type collector layer. A high-concentration collector layer is formed therein; (f) a first conductivity type base region is formed below the second contact hole; and (g) a side wall made of an oxide film and a nitride film on the side wall of the second contact hole. (H) forming an emitter region of a second conductivity type in the base region with the side wall therebetween, and (i) forming an emitter polysilicon on the emitter region. A method for manufacturing a semiconductor device.