JPH11135477A - Manufacture of compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a damage to an active layer due to etching upon formation of a gate electrode, by forming a first compound semiconductor layer having a first etching speed on the active layer, and forming a second compound semiconductor layer having a second etching speed higher than the first etching speed. SOLUTION: An nGaAs layer 12 is formed as an active layer on a semi- insulating GaAs substrate, and an n-AlGaAs layer 21 functioning as a protective layer and an etching stopper against dry etching and wet etching is deposited as a first compound semiconductor layer on the nGaAs layer 12. Then, an n-GaAs layer 22 is deposited as a second compound semiconductor layer on the n-AlGaAs layer 21. Here, if the etching speed of the n-AlGaAs layer 21 is referred to as a first etching speed and the etching speed of the n-GaAs layer 22 is referred to as a second etching speed, the second etching speed is higher than the first etching speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a compound semiconductor device.

[0002]

2. Description of the Related Art Generally, a compound semiconductor device of this type is
Compound semiconductor devices having a heterojunction include HEMT (High Electron Mobility Transistor) known as a heterojunction FET and SIS (Semiconductor Ins.)
(Ultor Semiconductor) FETs and the like. In these compound semiconductor devices, a compound semiconductor represented by GaAs has higher electron mobility than silicon, and thus can operate at higher speed than a semiconductor device formed using silicon.

Further, these compound semiconductor devices are usually
On the active layer composed of a compound semiconductor, a gate electrode is provided, and a source and a drain electrode that are in ohmic contact with the active layer are provided.
Many have a structure that forms a channel.

Conventionally, in a compound semiconductor device having such a structure, there is no variation in the threshold voltage at the gate electrode, that is, the threshold voltage, the breakdown voltage at the gate electrode is high, and the capacitance at the gate electrode is small. Are required in terms of speeding up.

However, a compound semiconductor device satisfying all these requirements has not been manufactured and put into practical use.

In order to clarify this, a conventional method for manufacturing a general compound semiconductor device will be described with reference to FIG. First, as shown in FIG. 4A, an nGaAs serving as an active layer is formed on a semi-insulating GaAs substrate 11.
s12 is formed, and an SiO2 film 13 is formed on the surface of the nGaAs layer 12 as a mask layer. In this state, a gate opening 14 for forming a gate electrode is selectively formed in the SiO 2 film 13 by physical etching, that is, dry etching.

As described above, when the SiO 2 film 13 deposited on the surface of the nGaAs 12 is selectively etched by dry etching, the nGaAs layer 1 as an active layer is formed.
It was found that the surface of No. 2 was inevitably damaged by dry etching. Therefore, when the gate electrode 15 is formed on the damaged nGaAs layer 12 as shown in FIG. 4B, the threshold voltage Vt of the compound semiconductor device fluctuates. This is because the damage caused by dry etching itself is
It is not always constant, but changes.

In order to reduce the influence of damage due to dry etching, as shown in FIG.
It is conceivable to form the gate electrode 15 after partially removing the surface of the GaAs 12 by etching.
Reducing the thickness of the nGaAs layer 12, which is the active layer, can prevent the threshold voltage Vt from fluctuating, but lowers the gate breakdown voltage. This is presumably because, for example, the electric field is easily concentrated because a part of the side surface of the gate electrode 12 is in contact with the surface of the nGaAs 12.

On the other hand, Japanese Patent Application Laid-Open No. 1-171279 (hereinafter referred to as Reference 1) discloses that an AlGaAs layer containing high-concentration impurities is provided as a barrier layer on a GaAs layer serving as an active layer, and the barrier layer is provided. A compound semiconductor device provided with a contact layer on a layer is disclosed. The disclosed compound semiconductor device has a structure in which a recess, that is, a recess is provided in a contact layer, and a gate electrode is formed in the recess. In this structure, the yield in the recess step can be increased by providing the barrier layer on the active layer.

The barrier layer has an impurity concentration of 1 × 10
^By increasing the thickness to ¹⁸ / cm ³ -5 × 10 ¹⁸ / cm ³ and reducing the thickness to about 5 nm to 30 nm, the effective carrier concentration of the active layer can be increased, while the transconductance can be increased.

On the other hand, Japanese Patent Application Laid-Open No. Hei 8-116034 (hereinafter referred to as Reference 2) discloses two types, an enhancement type (hereinafter referred to as E type) and a depletion type (hereinafter referred to as D type). And a method for manufacturing the same. In the manufacturing method described in Reference 2, a channel layer, an electron supply layer, a threshold control layer, an etching stop layer, a contact layer, and an insulating layer are sequentially formed in the E-type and D-type element regions. Gate openings are formed in the E-type and D-type element regions by dry etching, that is, physical etching.

The gate opening formed by dry etching is removed to the above-mentioned etching stop layer by removing the insulating layer and the contact layer, thereby forming the gate opening in the E-type element region. Furthermore, D
In the type element region, the etching stop layer is further removed by wet etching, that is, chemical etching, and the threshold control layer is dry etched, so that the D type region reaches the electron supply layer for the D type element. A gate opening is formed.

[0013]

In the cited reference 1, as described above, the recess step can be facilitated by inserting a barrier layer having a high impurity concentration, that is, a high carrier concentration, immediately below the gate. Withstand voltage and transconductance can be improved.

However, the cited reference 1 does not point out any problem in forming the gate electrode after the recess step. Therefore, in the configuration of Reference 1, the barrier layer itself also functions as a part of the active layer, and if the barrier layer itself is damaged during the formation of the gate electrode, the gate breakdown voltage and the mutual conductance vary. There is a disadvantage that it will.

Reference 2 discloses that an etching stop layer is provided, but the etching stop layer is left only in the E-type element region, and the etching stop layer and the etching stop layer in the D-type element region are left. The threshold layer has been removed by etching. As a result, the active layers such as the electron supply layer and the channel layer in the D-type element region are damaged by the etching when forming the gate electrode. Furthermore, the compound semiconductor device shown in Reference 2 has a large gate capacitance and cannot improve high-frequency characteristics because the side surface of the gate electrode is in direct contact with the contact layer and the insulating layer.

In any case, the cited examples 1 and 2 do not suggest that the active layer is damaged or damaged by the etching performed at the time of forming the gate electrode. Also did not point out. Therefore, from the cited examples 1 and 2, it is impossible to find a manufacturing method capable of preventing the active layer from being damaged due to the etching.

An object of the present invention is to provide a method of manufacturing a compound semiconductor device which can prevent an active layer from being damaged or damaged by etching performed when forming a gate electrode.

Another object of the present invention is to provide a method of manufacturing a compound semiconductor device which can prevent a variation in threshold value due to damage when forming a gate electrode.

Still another object of the present invention is to provide a compound semiconductor device having a small gate capacitance and no damage to the active layer, and as a result, having excellent characteristics at high frequencies.

[0020]

According to one embodiment of the present invention, on an active layer formed of a compound semiconductor,
Forming a first compound semiconductor layer having a predetermined first etching rate for etching; and forming a second compound semiconductor layer having a second etching rate higher than the first etching rate for etching. Forming a compound semiconductor layer, a first etching step of etching until reaching the second compound semiconductor layer, and a second etching step of etching the second compound semiconductor layer until reaching the first compound semiconductor layer. A method for manufacturing a compound semiconductor device having an etching step is obtained. Here, the first and second
In the etching step, physical and chemical etching are performed, respectively.

According to another embodiment of the present invention, a first layer having a first etching rate predetermined for etching is formed on an active layer formed of a compound semiconductor.
Forming a compound semiconductor layer, forming a second compound semiconductor layer, and forming the first compound semiconductor layer, before forming the second compound semiconductor layer, and performing first etching Forming a third compound semiconductor layer having an etching rate lower than the rate between the first and second compound semiconductor layers, and performing a first etching step until the third compound semiconductor layer is reached; When,
And a second etching step of etching the third compound semiconductor layer.

According to still another embodiment of the present invention, there is provided a compound semiconductor device comprising: an active layer formed of a compound semiconductor; and a region including a gate electrode and formed on the active layer. A first compound semiconductor layer formed in the region on the active layer and exhibiting a first etching rate for etching; and a first compound semiconductor layer formed in the region on the first compound semiconductor layer for etching. A second compound semiconductor layer having a second etching rate higher than that of the first compound semiconductor, the first compound semiconductor layer acting as a protective layer of the active layer against etching, and an etching stopper. It has an impurity concentration and a thickness that also operate as a layer, and the gate electrode includes:
A compound semiconductor device having a side surface exposed in the region is obtained.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a compound semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

Referring to FIGS. 1A, 1B, and 1C, a method of manufacturing a compound semiconductor device according to a first embodiment of the present invention is shown in the order of steps. Here,
An HFET including a gate electrode, a source electrode, and a drain electrode is illustrated as a compound semiconductor device.

First, in FIG. 1A, semi-insulating Ga
An As substrate 11 is used, and an nGaAs layer 12 is formed on the semi-insulating GaAs substrate as an active layer by MOCV.
D, MBE and the like. Illustrated nGa
The As layer 12 has, for example, a carrier concentration of 2 × 10 ¹⁷ cm ⁻³ and a thickness of 160 nm.
Here, as is well known, a buffer layer (not shown) such as an undoped AlGaAs layer is disposed between the semi-insulating GaAs substrate 11 and the nGaAs layer 12 forming the active layer. good.

Further, on the nGaAs layer 12, the surface of the nGaAs layer 12 as an active layer is etched by functioning as a protective layer and an etching stopper for physical and chemical etching such as dry etching and wet etching. N-AlGa to prevent from damage
An As layer 21 is applied as a first compound semiconductor layer by MBE or the like. N-AlGa shown in this example
The As layer 21 has, for example, a carrier concentration of 5 × 10 ¹⁶ cm ⁻³ and a thickness of 10 nm. As is apparent from this, the carrier concentration of the n-AlGaAs layer 21 is lower than the carrier concentration of the nGaAs layer 12 provided as the active layer, and thus the illustrated n-AlG
It can be seen that the aAs layer 21 does not function as a part of the active layer.

In the illustrated example, the n-AlGaAs layer 2
An nGaAs layer 22 is deposited on 1 as a second compound semiconductor layer in the same manner as the other nGaAs layers 12 and n-AlGaAs layers 21. Illustrated nGaAs
The s layer 22 has, for example, a carrier concentration of 2 × 10 ¹⁷ cm ⁻³ and a thickness of 5 nm in a region where a gate electrode is to be formed later.

In this case, the n-GaAs layer 22 is made of n-Al
Compared to the GaAs layer 21, it has a higher etching rate for dry etching and wet etching. Here, if the etching rate of the n-AlGaAs layer 21 is the first etching rate and the etching rate of the n-GaAs layer 22 is the second etching rate, the second etching rate is compared with the first etching rate. NGaAs layer 14 is n-AlGaAs layer 21
Is etched more quickly than

The n-AlGaAs layer 21 is made of n-G
Since it has a wider band gap than the aAs layer 22, the gate withstand voltage of the manufactured compound semiconductor device can be increased.

In the example shown in FIG. 1A, n-GaAs
The s layer 22 is provided with a recess region in advance,
The AlGaAs layer 21 is formed in the recess region described above.
It has a thickness of 5 nm.

As shown, the n-GaAs layer 2
2, a SiO2 film 23 having a thickness of 500 nm is deposited. After the SiO2 film 23 is applied, dry etching (physical etching) is selectively performed on a region corresponding to the recess region, as in FIG. This dry etching step is referred to herein as a first etching step. As a result of the dry etching, the SiO2 film 2
3 is removed to form a gate opening. At the time of dry etching, the n-GaAs layer 22 is damaged by the dry etching, but the n-AlGaAs layer 21 disposed under the n-GaAs layer 22 is the n-GaAs layer 2.
2 protects and does not take any damage.

The nGaAs layer 14 at the gate opening damaged by the dry etching is selectively etched with, for example, a mixed solution of a citric acid aqueous solution and a hydrogen peroxide solution. As a result, the n-AlGaAs layer 21 in the recess region is formed.
Will be exposed.

In this state, as shown in FIG. 1B, a gate electrode 15 made of metal is attached to the gate opening. The gate electrode 15 is made of, for example, WSi
A structure in which a plurality of metal layers are stacked, such as / Ti / Pt / Au, may be used.

Next, as shown in FIG.
After the film 23 is removed by etching, the nGaAs layer 22 is also selectively etched using an etchant,
That is, n-AlGaAs is removed by chemical etching.
The surface of the s layer 21 is exposed. This etching process
Here, this is called a second etching step, and the n-AlGaAs layer 21 is not substantially etched during the second etching step. This means that the etching rate of the nGaAs layer 22 with respect to the etching solution is n-AlGaAs.
This means that it is faster than the etching rate of the s layer 21. As a result of the second etching step, the side surface and the periphery of the gate electrode 15 have a configuration that does not contact the nGaAs layer 22 and other insulating films.

Thereafter, by forming a source electrode 25 and a drain electrode 26 on the nGaAs layer 22,
ET is configured. In the HFET having such a configuration, since the side surface of the gate electrode 16 is not covered with an insulating film or the like, the gate capacitance is small, so that characteristics at high frequencies can be improved.

With reference to FIGS. 2A and 2B, a method for manufacturing a compound semiconductor device according to the second embodiment of the present invention will be described. Also in FIG. 2, the same reference numerals are shown in portions corresponding to FIG. In FIG. 2A,
As shown in FIG. 1B, the state after the gate electrode 15 is formed and subsequently the SiO2 film 23 is removed is shown. In this state, the nGaAs layer 24 surrounds the gate electrode 15 on the n-AlGaAs layer 21.
Is left. NGaAs layer 2 around gate electrode 15
2A, the periphery of the gate electrode 15 is masked with a resist 30 so that only the nGaAs layer 22 around the gate electrode 15 is etched in the example shown in FIG. I have.

As described above, the nGaAs in the recess region
By etching a part of the layer 22 with the resist 30 masked, as shown in FIG.
The distance between the GaAs layer 22 and the gate electrode 15 can be reduced, and as a result, the parasitic resistance can be reduced.

Referring to FIGS. 3A, 3B and 3C, a compound semiconductor device according to a third embodiment of the present invention will be described.
The method of manufacturing the device will be described in the order of steps. The example shown in FIG. 3 shows an n-AlGaAs layer 21 as a first compound semiconductor layer and an nGaAs layer 2 as a second compound semiconductor layer.
2 is different from the example shown in FIG. 1 in that an nInGaP layer 35 is provided as a third compound semiconductor layer between the second compound semiconductor layer and the second compound semiconductor layer.

More specifically, as shown in FIG. 3A, a semi-insulating GaAs substrate 11 is
As in the case of (A), the nGaAs layer 12 is used as an active layer.
Are formed. Further, on the surface of the nGaAs layer 12, an n-AlGaAs layer 21 and an nInGaP layer 3 are formed.
5 are sequentially applied by MBE or the like. Furthermore, nI
On the surface of the nGaP layer 35, as in FIGS.
A GaAs layer 22 is deposited.

In FIG. 3A, by etching the nGaAs layer 22 as the second compound semiconductor layer,
A recess region is formed. Therefore, the nInGaP layer 35 as the third compound semiconductor layer is formed in the recess region.
Is exposed. Therefore, nInGa
It can be seen that the P layer 35 functions as an etching stopper when etching the nGaAs layer 22.

The nInGaP layer 35 and the nGaAs layer 22
Are exposed, a SiO2 film 23 is applied to these exposed surfaces. Also, the illustrated SiO2 film 2
A gate opening 14 is formed in the recess region 3 by dry etching. As a result of the dry etching, the nInGaP layer 35 is damaged by the dry etching.
5 does not extend to the n-AlGaAs layer 21 arranged below. Therefore, the nInGaP layer 35 serves as a protective layer for the n-AlGaAs layer 21 during dry etching.

The damaged nInGaP layer 35 is
It is removed by the same etchant as in FIG.
-The AlGaAs layer 21 is exposed. At this time,
The n-AlGaAs layer 21 is not substantially etched by the etchant. In other words, n-Al
The etching rate of the GaAs layer 21 is the same as that of the nInGaP layer 3.
5 is slower than the etching rate of 5.

Next, as shown in FIG.
A gate electrode 15 is formed in the exposed gate opening 14 of the GaAs layer 21. At this time, as shown in FIG. 3B, the gate electrode 15 is connected to the surface of the n-AlGaAs layer 21 and the side surface thereof is
Is in contact with In this example, the gate electrode 15 is not in contact with the nGaAs layer 22.

After the formation of the gate electrode 15, as shown in FIG. 3C, first, the SiO2 film 23 is removed by wet etching, and the nInGaP layer 35 deposited around the gate electrode 15 is also wet etched. To be removed. As a result, a gate electrode 15 that is not surrounded by an insulating film or the like, that is, does not contact the other layer on the side surface, is formed in the recess region as illustrated in FIG.

[0045]

According to the present invention, FIG. 1 (C), FIG.
With the structure of FIG. 3B and FIG. 3C, damage due to etching immediately below the gate electrode can be prevented, so that a compound semiconductor device with no variation in threshold can be manufactured. Further, since the compound semiconductor device according to the present invention includes the gate electrode which is not in contact with the insulating film, the GaAs layer, or the like, there is also an effect that the gate breakdown voltage does not decrease.

[Brief description of the drawings]

1 (A), (B) and (C) show the first embodiment of the present invention.
FIG. 5 is a cross-sectional view for describing the method for manufacturing the compound semiconductor device according to the embodiment in the order of steps.

FIGS. 2A and 2B are cross-sectional views illustrating steps in a method for manufacturing a compound semiconductor device according to a second embodiment of the present invention.

FIG. 3 (A), (B) and (C) show a third embodiment of the present invention.
FIG. 5 is a cross-sectional view for describing the method for manufacturing the compound semiconductor device according to the embodiment in the order of steps.

FIGS. 4A and 4B are cross-sectional views illustrating an example of a conventional method for manufacturing a compound semiconductor device in the order of steps.

5 is a cross-sectional view for explaining a conventional method for improving the manufacturing method shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Semi-insulating GaAs substrate 12 nGaAs layer 13 SiO2 film 14 Gate opening 15 Gate electrode 21 n-AlGaAs layer 22 nGaAs layer 23 SiO2 film 25, 26 Source electrode, drain electrode 30 Resist 35 nInGaP layer

Claims (18)

[Claims] 1. A step of forming a first compound semiconductor layer having a first etching rate predetermined for etching on an active layer formed of a compound semiconductor; Forming a second compound semiconductor layer having a second etching rate higher than the etching rate of the first, a first etching step of etching until reaching the second compound semiconductor layer, and the second compound semiconductor A second etching step of etching the layer until the layer reaches the first compound semiconductor layer. 2. The method according to claim 1, wherein physical etching and chemical etching are performed in the first and second etching steps, respectively. 3. The method according to claim 2, wherein after the step of forming the second compound semiconductor layer and before the first etching step,
A mask layer is formed so as to cover the second compound semiconductor layer, and the mask layer is selectively and physically removed in the first etching step. Production method. 4. The method according to claim 3, wherein the mask layer is formed of an insulator layer. 5. The semiconductor device according to claim 4, wherein after the first and second etching steps, an etched portion formed in the insulator layer and the second compound semiconductor layer is in contact with the first compound semiconductor layer. A method for manufacturing a compound semiconductor device, comprising the step of forming a gate electrode layer to be formed. 6. The method for manufacturing a compound semiconductor device according to claim 5, further comprising a step of removing the insulator layer after the step of forming the gate electrode layer. 7. The active layer, the first compound semiconductor layer, and the second compound semiconductor layer according to claim 6, wherein the active layer, the first compound semiconductor layer, and the second compound semiconductor layer are a GaAs layer, an AlGaAs layer, and a G layer, respectively.
A method for manufacturing a compound semiconductor device, which is an aAs layer. 8. A step of forming a first compound semiconductor layer having a predetermined first etching rate for etching on an active layer formed of a compound semiconductor, and forming the second compound semiconductor layer on the active layer. Forming, and the first
After the step of forming the compound semiconductor layer, and before the step of forming the second compound semiconductor layer, the third compound semiconductor layer having an etching rate lower than the first etching rate is formed by combining the first and second compound semiconductor layers with each other. Forming the first compound semiconductor layer and etching the first compound semiconductor layer until reaching the third compound semiconductor layer.
And a second etching step of etching the third compound semiconductor layer. 9. The method according to claim 8, wherein in the first and second etching steps, physical etching and chemical etching are performed, respectively. 10. The method according to claim 9, wherein the second compound semiconductor layer formed on the third compound semiconductor layer before the first etching step.
Wherein the recessed portion exposing the third compound semiconductor layer is formed in the compound semiconductor layer, and the second and third compound semiconductor layers are covered with an insulating layer. Of manufacturing a compound semiconductor device. 11. The method according to claim 10, wherein, in the first etching step, the insulating layer is selectively removed by physical etching until the insulating layer reaches the third compound semiconductor layer, and then the third etching step is performed in the second etching step. Wherein the compound semiconductor layer is etched until it reaches the first compound semiconductor layer. 12. The method according to claim 11, wherein the first and second etching steps include:
A method for manufacturing a compound semiconductor device, comprising a step of forming a gate electrode. 13. A compound semiconductor device comprising: an active layer formed of a compound semiconductor; and a region including a gate electrode and formed on the active layer, wherein the compound semiconductor device is formed in the region on the active layer and etched. A first compound semiconductor layer exhibiting a first etching rate with respect to the first compound semiconductor layer, and a second etching formed in the region on the first compound semiconductor layer and having a higher etching rate than the first compound semiconductor. A second compound semiconductor layer having a velocity, wherein the first compound semiconductor layer acts as a protective layer of the active layer against etching, and the gate electrode is a side surface exposed in the region. A compound semiconductor device comprising: 14. The method according to claim 13, wherein the first compound semiconductor layer substantially prevents damage due to dry etching.
A compound semiconductor device characterized by not receiving the compound semiconductor device. 15. The active layer, the first compound semiconductor layer, and the second compound semiconductor layer according to claim 14, wherein the active layer, the first compound semiconductor layer, and the second compound semiconductor layer are a GaAs layer, an AlGaAs layer, and a G layer, respectively.
A compound semiconductor device comprising an aAs layer. 16. The compound semiconductor device according to claim 13, wherein an impurity concentration of the first compound semiconductor layer is lower than an impurity concentration of the active layer and the second compound semiconductor layer. 17. The semiconductor device according to claim 13, wherein a third compound semiconductor layer is provided in the region between the first compound semiconductor layer and the second compound semiconductor layer. Wherein the compound semiconductor layer has a higher etching rate for the second etching than the first compound semiconductor layer. 18. The semiconductor device according to claim 17, wherein the active layer, the first compound semiconductor layer, the second compound semiconductor layer, and the third compound semiconductor layer are a GaAs layer,
A compound semiconductor device comprising an AlGaAs layer, a GaAs layer, and an InGaP layer.