JPH11134256A - Address conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption in an address conversion circuit used at the time of using an associative memory and converting a virtual address into a physical address or the like. SOLUTION: This circuit is provided with a virtual address register 14 for holding the virtual address at the time of the conversion of a previous time, a comparator 15 for comparing the present virtual address with the virtual address inside the virtual address register 14, a physical address register 17 for holding the physical address outputted from a TLB 11 corresponding to a register write signal and a selector 18 for selecting one of the physical address outputted from the TLB 11 and the physical address inside the physical address register 17. When the virtual address matches between the previous time and this time, the converted result of the previous time stored in the physical address register 17 is outputted from the selector 18 without performing an address comparison operation in the TLB 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address conversion circuit for converting a first address into a second address using a content addressable memory or the like and outputting the converted address.

[0002]

2. Description of the Related Art Content addressable memories (CAMs)
For example, an address conversion circuit that converts a given first address to a second address at high speed and outputs the second address using a CPU (Central Processing Unit) in a computer system employing virtual memory Is used to convert the virtual address output by the to a physical address used for actual memory access. Hereinafter, in order to make the description easy to understand, a TLB (Table Lockasid) for converting a virtual address to a physical address is used as an address conversion circuit.
e Buffer) will be described.
FIG. 8 is a block diagram showing a configuration of an address conversion circuit based on TLB.

[0003] The TLB 81 shown in FIG.
The upper bits of the physical address 83 are output using the upper 2 bits as a tag, and a PFN (Physical Frame Number) which is a RAM (random access memory) for storing the upper bits of the physical address.
r) a VPN (virtual page number) CA that holds the upper bits of the virtual address corresponding to the physical address stored in the RAM 84 for PFN and compares with the upper bits of the virtual address 82 input from the outside.
M (associative memory) 85. VPN
The CAM 85 entry and the PFN RAM 84 entry form a set in one-to-one correspondence.
A plurality of virtual addresses 82 provided and input in the LB 81
Of the RAM 84 for PFN corresponding to the entry that matches in the CAM 85 for VPN,
81. This output is the upper bits of the physical address 83. It is to be noted that a computer system employing virtual memory generally employs the concept of a page in a memory address, and the correspondence between a virtual address and a physical address is determined for each page. Therefore, the high-order bit portion corresponding to each page in the virtual address 82 is input to the TLB 81 as described above, and is subjected to address conversion.
Are used as they are as the lower bits of the physical address 83.

A CAM 85 for VPN, which is an associative memory,
It has a plurality of associative memory cells each storing data for one hit and comparing with input bits. Then, the CAM 85 for VPN, for each entry,
When all the bits held in the associative memory cell belonging to the entry match the input bits, a match signal is output. In response to the coincidence signal, the PFN RAM
From 84, the physical address (upper bits of the physical address) is output.

FIG. 9 is a circuit diagram showing an example of the configuration of an associative memory used as a VPN CAM. Here, the configuration for one entry of the associative memory is shown.

This associative memory has a capacity of one bit.
A function that stores data and compares it with input bits.
Number of associative memory cells 91₁~ 91_nAnd each associative memory
Cell 91₁~ 91_n, A word line 92, a comparison control line
96 and a coincidence signal line 97 are provided. These words
Line 92, comparison control line 96 and match signal line 97 are shown
It extends in the horizontal direction (row direction). Top address of virtual address
These associative notes correspond to each bit of the
Recell 91₁~ 91_nIs provided. Match signal line 97
Indicates that gate control is not performed by the precharge control line 94.
Connected to the power supply via the transistor T0
You. Each associative memory cell 91₁~ 91_nThen, two inva
Data I0 and I1 are connected to each other,
With the construction of a static type storage element,
8 transistors for input / output of data to storage device
Terminals T1 to T8 are provided. Each associative memory cell
91 ₁~ 91_nInput bit data to be held
Bit lines 93, 93 'for comparison and the bit data to be compared.
Bit lines 95 and 95 'for inputting data
Have been. The data on the bit line 93 'is
The above data is inverted by the inverter I2,
The data on the comparison bit line 95 ′ is
Is inverted by the inverter I3.

In each of the associative memory cells 91 _{1 to} 91 _n ,
The transistor T1 is inserted between the comparison bit line 93 'and the input of the inverter I0 (output of the inverter I1), and the transistor T2 is inserted between the comparison bit line 93 and the output of the inverter I0 (input of the inverter I1). The gates of these transistors T1 and T2 are connected to a word line 92. Also, transistors T3, T5,
T7 is connected between the match signal line 97 and the ground potential so that the channel is connected in series and the transistor T3 is on the match signal line 97 side. Similarly, the transistor T
4, T6 and T8 are connected in series, and the matching signal line 97 is set so that the transistor T4 is on the matching signal line 97 side.
And ground potential. Transistor T
The bases of T3 and T4 are connected to the input and output of the inverter I0, respectively, and the bases of the transistors T5 and T6 are connected to comparison bit lines 95 and 95 ', respectively. The bases of the transistors T7 and T8 are connected to the comparison control line 96.

In such an associative memory cell, when the word line 92 goes high (hereinafter simply referred to as high), the transistors T1 and T2 are turned on, and the bit lines 93 and 93 'are connected to the storage element. become,
Data can be written or read. In addition, only one of the transistor T3 and the transistor T4 is turned on in accordance with the content stored in the storage element portion (the value stored in the memory cell).

The actual associative memory operation is performed by comparing control line 96
At a low level (hereinafter simply referred to as low), first, the precharge signal line 94 is set high to turn on the transistor T0, and the match signal line 97 is connected to the power supply line to store electric charges. The operation is started from an operation (precharge operation) for setting the potential of the high state to a high state. When the precharge ends, the precharge signal line 94 goes low, the transistor T0 transitions to off, and the supply of charges to the match signal line 97 stops. Even when the supply of the electric charge is stopped, the coincidence signal line 97 can maintain the high state for a certain period of time because there is no discharge path other than the leakage.

Next, an address to be compared is set by the comparison bit line 95. Then, the comparison bit line 95,
The signal on 95 'turns on only one of the transistors T5 or T6. In this state, when the comparison control line 96 is set high, the transistor T
7 and T8 are both turned on, and a current path (transistors T3 and T5) is provided between the coincidence signal line 97 and the ground potential according to the storage content of the storage element portion and the data content on the comparison bit lines 95 and 95 '. , T7 and transistors T4, T6, T8) are opened or closed. When the current path is formed, the charge stored in the match signal line 97 is discharged, and the potential of the match signal line 97 changes to low. When the current path is cut off, the coincidence signal line 97 keeps a high state.

Such associative memory cells 91 _{1 to} 91
_n is the number of bits to be compared in the horizontal direction (row direction)
That is, the number of bits is set corresponding to the number of higher-order bits of the virtual address, and only when the comparisons of all the bits match, the discharge path of the match signal line 97 is cut off, and the potential becomes high. If there is a mismatch even in one bit, the charge is discharged from the discharge path of the mismatched associative memory cell, and the potential of the match signal line 97 becomes low.

In the above-described TLB 81, the comparison bit line 9
5, the virtual address is converted from the virtual address to the physical address by connecting the word line of the RAM 84 for PFN composed of a normal semiconductor memory to the match signal line 97 of the CAM 85 for VPN. Can be done easily.

The above-described conventional TLB 81
Is applied to a computer that performs multi-task processing, the task cannot be identified as it is. Therefore, when a context switch occurs, the TLB8
In some cases, it is necessary to invalidate all the contents of 1 and load the virtual address and the physical address in the new task into the TLB 81. Therefore, in Japanese Patent Application Laid-Open No. 63-81548, a task identifier (process number, that is, a process ID) is introduced, a process ID for specifying a task is assigned to each task, and the process ID and the virtual address are assigned. A technology for generating a physical address using tags as tags has been disclosed.

[0014]

The above-described address conversion circuit uses an associative memory composed of a large number of associative memory cells.
(Static random access memory) or DR
Unlike an AM (Dynamic Random Access Memory), it has a circuit for comparison, so that the power consumption required to simply hold the stored contents is SR
Although it is similar to AM and the like, if the comparison operation is performed for address conversion, for example, the charge / discharge of the coincidence signal line is involved, so that the power consumption becomes considerably large. As a result, the power consumption of the address conversion circuit itself increases, which is a disadvantage when configuring an LSI (large-scale integrated circuit) in which the address conversion circuit is incorporated together with other circuits.

An object of the present invention is to provide an address conversion circuit capable of reducing power consumption.

[0016]

An address conversion circuit according to the present invention is an address conversion circuit for converting a first address into a second address. The address conversion circuit performs an address comparison operation in accordance with a conversion start signal. Output information which is the address of
Address conversion means for converting the first address, an address holding means for holding the first address at the time of the previous conversion, and a comparison between the current first address and the first address held in the address holding means. A comparison unit, an output information holding unit that captures and holds output information output by the address conversion unit in response to a write signal, and a current output information from the address conversion unit and an output information held by the output information holding unit. And selecting means for selecting and outputting any of them according to the selection signal, and when the conversion means determines that they match, the conversion information is held in the output information holding means without outputting a conversion start signal. When the output signal is controlled by the selection signal so that the output information is output from the selection means, and when the conversion means requests, the comparison means determines that they do not match. Outputs a conversion start signal and a write signal, and a control means for controlling the selection signals as the current output information from the address translation means is output from the selecting means.

That is, in the present invention, when the first address, which is, for example, a virtual address, is converted into the second address, which is, for example, a physical address, by an address conversion means typically constituted by an associative memory, the address conversion is performed. The power consumption of the entire address conversion circuit is reduced by reducing the number of address comparison operations by the means. Specifically, assuming that the conversion request is input as a conversion request signal, the comparison address (first address) at the time of the previous conversion is held in an address holding unit such as a virtual address register, and the comparison unit such as a comparator is stored. To compare the previous virtual address with the current virtual address. When they match, that is, when the previous address conversion result can be used, address comparison in the associative memory is suppressed, and instead, output information holding means such as a physical address register (or second address holding means) is used. Means), the previous conversion result (physical address) stored in the address conversion circuit is selected by a selection means such as a selector and output from the address conversion circuit. In order to execute such processing, the control circuit (control means) generates a conversion start signal, a register write signal, and a selection signal according to the conversion request signal and the coincidence signal.

[0018]

Next, an embodiment of the present invention will be described with reference to the drawings.

<< First Embodiment >> FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an address conversion circuit according to the embodiment. Here, CPU in the virtual storage system
An address conversion circuit used to convert a virtual address output from a (not shown) side into a physical address will be described as an example. This address conversion circuit converts a virtual address to a physical address when a conversion request signal is output from the CPU. In the figure, although they are simply described as “virtual address” and “physical address”, these are, of course, the upper bits of the virtual address and the upper bits of the physical address, respectively. In this type of address conversion circuit, control when there is no entry matching the input virtual address and control for storing address data in the address conversion circuit in advance are necessary, and a control mechanism for this is provided. However, such a control mechanism is not shown here for the sake of simplicity.

As in the conventional address conversion circuit shown in FIG. 8, a TLB 11 is provided.
CAM 12 and PFN RAM 13 are provided.
Here, the same as the conventional one is used as the VPN CAM 12 and the PFN RAM 13. Among them, the VPN CAM 12 performs an address comparison operation for the first time upon input of the conversion start signal, and outputs the conversion start signal. As long as there is no input, one that performs only the operation of retaining the stored contents without performing the address comparison operation is used. Such a V
As the PN CAM 12, for example, the above-described associative memory shown in FIG. 9 can be used. If the associative memory shown in FIG. 9 is used, before the conversion start signal is input, the word line 92, the precharge control line 94, and the comparison control line 96 are all held at a low level so that each associative memory cell Only the operation of retaining the stored contents is performed, and the levels of the word line 92, the precharge control line 94, and the comparison control line 96 are changed according to the above-described procedure according to the input of the conversion start signal, so that the address comparison operation is performed. I just need.

Further, the address conversion circuit includes a CPU
The virtual address register 14 that latches the virtual address in response to the conversion request signal input from the side and the current virtual address and the virtual address held by the virtual address register 14 are compared. A comparator 15 that outputs a coincidence signal, a control circuit 16 that receives a conversion request signal and a coincidence signal as input, and outputs a conversion end signal, a conversion start signal, a register write signal, and a selection signal, and outputs from the PFN RAM 13 A physical address register 17 for latching a physical address according to a register write signal;
A selector 18 is provided for selecting a physical address currently output by the PFN RAM 13 and a physical address held in the physical address register 17 in accordance with a selection signal. The selector 18 outputs a physical address as an output of the address conversion circuit. The selector 18
When the selection signal is output (in the case of “1”), the physical address register 17 is selected.

In this address conversion circuit, an external CPU
The virtual address output from such as CAM1 for VPN
2. It is supplied to the virtual address register 14 and the comparator 15. Then, the virtual address is latched in the virtual address register 14 in response to the conversion request signal, so that the content of the virtual address register 14 is the virtual address at the time of the previous output of the conversion request signal. Therefore, the comparator 1
5, the previous virtual address is compared with the current virtual address, and when they match, that is, when the previous address conversion result can be used, the address comparison in the VPN CAM 12 is suppressed, and the physical address is replaced. The previous conversion result (physical address) stored in the register 17 is selected by the selector 18 and output from the address conversion circuit. To execute such a process, the control circuit 16 generates a conversion start signal, a register write signal, and a selection signal according to the conversion request signal and the coincidence signal. The control circuit 16 also generates a conversion end signal. This conversion end signal is used to notify the CPU that the address conversion has been completed.

FIG. 2 is a circuit diagram showing the internal configuration of the control circuit 16. In the following description, it is assumed that the circuit operates according to positive logic, and the high level corresponds to "1" and the low level corresponds to "0".

The control circuit 16 calculates the logical product of the inverter 21 for inverting the coincidence signal and the conversion request signal and the output of the inverter 21 and outputs the logical product as the conversion start signal.
Gate 22 and a second AND gate 23 for calculating the logical product of the conversion request signal and the output of the coincidence signal
And a first D-type flip-flop 24 for latching a conversion start signal based on a predetermined clock signal CLK and outputting it as a register write signal, and latching an output of a second AND gate 23 based on the clock signal CLK. It comprises a second D-type flip-flop 25 that outputs as a selection signal, and an OR (or) gate 26 that obtains a logical sum of the register write signal and the selection signal and outputs it as a conversion end signal.

By configuring the control circuit 16 in this manner, even if the conversion request signal is input, the coincidence signal is "1",
That is, when the virtual address is the same in the previous time and this time,
The conversion start signal is not output, and the address comparison operation in the VPN CAM 12 is not performed. Instead, the selection signal is output as "1" with a delay of one clock,
The content of the physical address register 17 is output from the selector 18 as a physical address. On the other hand, when the match signal is “0”, that is, when the virtual address is different between the previous time and the current time, when the conversion request signal is input, the conversion start signal is output from the first AND gate 22, whereby the V
An address comparison operation is performed in the PN CAM 12, and one clock (delay time from input to output in the TBL 11)
After that, the converted physical address is stored in the PFN RAM 13.
Output from At this time, since the selection signal has not been output, this physical address is output as it is from the selector 18 to the outside, and a register write signal is generated, and the physical address is changed when the next virtual address matches the current one. This physical address is latched in the physical address register 17 for output.

FIG. 3 is a timing chart summarizing the above operation. In FIG. 3, “at the time of non-match” and “at the time of match” represent the time when the current virtual address does not match and the time when the previous virtual address stored in the virtual address register 14 matches, respectively. I have. A physical address corresponding to the virtual address A is represented by A '.

In the address conversion circuit of the present embodiment described above, the previous virtual address is compared with the current virtual address, and when they match, the address comparison in the VPN CAM 12 is suppressed. The previous conversion result (physical address) stored in the register 17 is selected. As a result, when address conversion is performed continuously in the same page of the virtual address, the address comparison operation in the VPN CAM 12 is required only once, but the address comparison operation is performed after the second time. Operation is not required, and the VPN CAM 12 can be set to a low power consumption state (a state in which only stored contents are held).
In general, since the local referability of a software program is large, by appropriately designing the page size and performing appropriate programming, the transition of addresses to different pages can be significantly reduced. In such a case, the configuration of the address conversion circuit according to the present embodiment achieves a significant reduction in power consumption as compared with the conventional address conversion circuit.

Also, in this address conversion circuit, when the previous virtual address and the current virtual address match, the CAM 12 for VPN and the RAM 13 for PFN are not used, so that the physical address is faster than in the conventional address conversion circuit. Can be obtained.

<< Second Embodiment >> FIG. 4 shows a second embodiment of the present invention.
3 shows a configuration of an address conversion circuit according to the embodiment. Here, T associated with a context switch (task switching)
In order to prevent invalidation of the LB, a process ID (process number) is held in the TLB itself, and conversion to a physical address is performed using the process ID and the virtual address as tags.

As the TLB 31, in addition to the VPN CAM 12 and the PFN RAM 13, a process I as a tag is performed.
A memory having a PRID CAM 32 which is an associative memory for D is used. The CAM for PRID 32 is a VPN
Address comparison operation is performed integrally with the CAM 12 for use, a conversion start signal is provided separately from the CAM 12 for VPN, and the address conversion operation is performed one clock earlier than the address conversion operation in the CAM 12 for VPN. It is configured as follows. Specifically, in the associative memory as shown in FIG. 9 described above, one word line region to which a plurality of associative memory cells are connected is divided into a portion for the CAM 32 for PRID and a portion for the CAM 12 for VPN. In addition, a latch circuit may be provided at the boundary between the coincidence signal lines, and the comparison control line may be separately provided for both. The PRID CAM 32 stores a process ID from a process ID register 33 provided in the CPU.
D is supplied. In this address conversion circuit,
The conversion start signals (PRID conversion start signal, VP respectively) are separately provided for the CAM 32 for PRID and the CAM 12 for VPN.
In the case where the internal configuration of the control circuit is the address conversion circuit shown in FIG. 1 (see FIG. 2)
Is different. FIG. 5 shows the internal configuration of the control circuit 34. In other respects, this address conversion circuit is the same as the address conversion circuit shown in FIG.

The control circuit 34 inverts the coincidence signal, an AND gate 42 for calculating the logical product of the conversion request signal and the output of the inverter 41, and calculates the logical product of the conversion request signal and the output of the coincidence signal. A second AND gate 43 to be obtained, a first D-type flip-flop 44 for latching an output of the first AND gate 42 based on a predetermined clock signal CLK and outputting the same as a VPN conversion start signal, and a clock signal CLK A second D-type flip-flop 45 that latches the output of the second AND gate 43 and outputs the selected signal as a selection signal;
A third D-type flip-flop 46 that latches the PN conversion start signal and outputs the same as a register write signal, and a fourth D-type flip-flop 45 that latches the output of the second D-type flip-flop 45 based on the clock signal CLK and outputs the same as a selection signal. D-type flip-flop 47, and an OR gate 48 that calculates the logical sum of the register write signal and the selection signal and outputs the result as a conversion end signal. The conversion request signal is
As it is, it is also output as a PRID conversion start signal.

By configuring the control circuit 34 in this manner, when a conversion request signal is input, it immediately
The signal is output to the PRID CAM 32 as a RID conversion start signal. Therefore, each time a conversion request signal is generated, the PRI
The address comparison operation is performed in the D CAM 32. The bit width of the PRID CAM 32 (the bit width of the process ID) is smaller than the input bit width of the VPN CAM 12, that is, the bit width of the virtual address (upper bit of the virtual address). And the PRID is generated every time a conversion request signal is generated.
Even if the CAM 32 performs the address comparison operation, the increase in power consumption is small. The reason why the address comparison operation using the process ID is performed prior to the address comparison operation using the virtual address is that the CPU outputs the process ID prior to the virtual address in order to guarantee the operation during the context switch. That's why.

The control circuit 34 generates a VPN conversion start signal (corresponding to the conversion start signal in the control circuit of FIG. 2), a register write signal, a selection signal, and a conversion end signal. It is the same as the control circuit shown in FIG. Therefore, depending on whether or not the virtual address at the time of the previous conversion matches the current virtual address, the physical address in the physical address register 17 is output without performing the address comparison of the virtual address portion, or the virtual address is output. It is determined whether to compare the addresses of the parts and output the result. The operation timing of this address conversion circuit is shown in the timing chart of FIG.

Also in the present embodiment, when address conversion is continuously performed in the same page of the virtual address, a significant reduction in power consumption can be achieved.

<< Third Embodiment >> Next, a third embodiment of the present invention will be described with reference to FIG. Each of the embodiments described above shows a case where a virtual address is converted into a physical address by TLB.
An example in which the present invention is applied to a cache memory using the two-way set associative method will be described.

This address conversion circuit realizes a set associative cache operation, instead of providing a TLB in the address conversion circuit shown in FIG.
A decoder 51 for decoding a virtual address, and a set #
0 and set # 1 VPN virtual address RAM 52,
53, PFN physical address RAM 54, and set #
The comparator 55 compares the address output from the virtual address RAM 52 for VPN with the input virtual address and outputs a set # 0 match signal, and the virtual address input from the virtual address RAM 53 for set # 1 and the input virtual address. The configuration includes a comparator 56 that compares an address and outputs a set # 1 coincidence signal, and a selector 57 controlled by the set # 0 coincidence signal and the set # 1 coincidence signal. In order to make the explanation easy to understand, each RAM
A mechanism for writing data to 52 to 54 and a mechanism for performing processing when a cache miss occurs are not shown.

The decoding result of the decoder 51 is given to the virtual address RAMs 52 and 53 for VPN and the physical address RAM 54 for PFN. The PFN physical address RAM 54 has a storage area for set # 0 and a storage area for set # 1.
And a physical address is output from each of them and input to the selector 57. Selector 57
Is equal to PF when the set # 0 coincidence signal is output.
The storage area for the set # 0 of the physical address RAM 54 for N is selected, and when the set # 1 coincidence signal is output, the storage area for the set # 1 of the physical address RAM 54 for PFN is selected and selected. The physical address is output to the physical address register 17 and the selector 18. The conversion start signal output from the control circuit 16 includes the virtual address RAMs 52 and 53 for VPN and the physical address RA for PFN.
It is provided to each storage area of M54.

In this address conversion circuit, the supply of the conversion start signal to each RAM is suppressed when the previous virtual address matches the current virtual address, as in the address conversion circuits of the above-described embodiments. . Each RAM 52-54
When a virtual address corresponding to the previous virtual address coincides with the current virtual address, the RAMs 52 to 5 are used.
4 can remain in the low power consumption mode,
Compared with the conventional address conversion circuit in which each RAM is set to the operation mode each time a conversion request signal is output, it is possible to significantly reduce power consumption.

[0039]

As described above, according to the present invention, when performing address conversion from a first address (for example, a virtual address) to a second address (for example, a physical address) using an associative memory or the like, While holding the first address and the second address at the time of conversion, it is determined whether the first address is the same between the previous time and the current time,
If they match, the stored second address at the previous conversion is output as it is without performing the address comparison operation in the associative memory or the like. As a result, when the previous address conversion result can be used, the address comparison operation is not performed, and the power consumption of the address conversion circuit can be reduced accordingly. In the case of a software program, the local addressability is generally considered to be large, so that in the majority of scenes requiring address translation, the first address is the same between the previous translation and the current translation. According to the present invention, it is possible to greatly reduce the power consumption of the address conversion circuit. Further, according to the present invention, if the first address is the same between the previous time and the present time, the first address is not passed through the associative memory or the like, so that the second address can be obtained more quickly.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an address conversion circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a control circuit in the address conversion circuit of FIG.

FIG. 3 is a timing chart illustrating an operation of the address conversion circuit of FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of an address conversion circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a control circuit in the address conversion circuit of FIG. 2;

FIG. 6 is a timing chart illustrating the operation of the address conversion circuit of FIG. 2;

FIG. 7 is a block diagram illustrating a configuration of an address conversion circuit according to a third embodiment of the present invention configured as a set associative cache memory;

FIG. 8 is a block diagram showing a configuration of a conventional address conversion circuit.

FIG. 9 is a circuit diagram showing an example of a configuration of a VPN CAM.

[Explanation of symbols]

 11,31 TLB 12 CAM for VPN 13 RAM for PFN 14 Virtual address register 15,55,56 Comparator 16,34 Control circuit 17 Physical address register 18,57 Selector 21,41 Inverter 22,23,42,43 AND gate 24 , 25,44-47 D-type flip-flop 26,48 OR gate 32 CAM for PRID 33 Process ID register 51 Decoder 52,53 Virtual address RAM for VPN 54 Physical address RAM for PFN

Claims (7)

[Claims] 1. An address conversion circuit for converting a first address into a second address, performing an address comparison operation in response to a conversion start signal, and adding the first address to the output information as the second address. Address translation means for translating an address; address retention means for retaining the first address at the time of previous translation; current first address; and the first address retained in the address retention means. Comparing means for comparing the output information output from the address conversion means with a write signal in accordance with a write signal, and holding the output information; and holding the current output information and the output information from the address conversion means. Selecting means for selecting and outputting any of the output information held in the means in accordance with a selection signal, and matching in the comparing means when there is a conversion request When it is determined that the conversion start signal is not output, the output information held by the output information holding means is controlled by the selection signal so that the output information is output from the selection means. When the comparison means determines that there is no match, the conversion start signal and the write signal are output, and the selection is made so that the current output information from the address conversion means is output from the selection means. Control means for controlling with a signal. 2. The address conversion circuit according to claim 1, wherein said address conversion means is a set associative cache memory. 3. An address conversion circuit for converting a first address to a second address, comprising an associative memory, performing an address comparison operation in response to a conversion start signal, and converting the first address to the first address. Address conversion means for converting the first address and the second address, the first address holding means for holding the first address at the time of the previous conversion, and the current first address and the address held by the address holding means. Comparing means for comparing the first address with the first address; second address holding means for receiving and holding the second address output by the address conversion means in accordance with a write signal; Selecting means for selecting and outputting any one of the second address and the second address held in the second address holding means in accordance with a selection signal; If it is determined by the comparing means that there is a match, the second address held in the second address holding means is output from the selecting means without outputting the conversion start signal. The output of the address is controlled by the selection signal, and when it is determined by the comparing means that there is no match when there is a conversion request, the conversion start signal and the write signal are output. And control means for controlling the second address according to the selection signal so as to output the second address from the selection means. 4. The first control means for calculating an AND of a conversion request signal and an output of the inverter, wherein the control means obtains a logical product of a conversion request signal and the output of the inverter, and outputs the result as the conversion start signal. An AND gate, a second AND gate for obtaining the logical product of the conversion request signal and the output of the coincidence signal, and a first AND gate for latching the conversion start signal based on a predetermined clock signal and outputting the conversion start signal as the register write signal 4. The address conversion circuit according to claim 3, further comprising: a D-type flip-flop that latches an output of the second AND gate based on the clock signal and outputs the selected signal as the selection signal. . 5. The address conversion means comprises: the associative memory having a plurality of entries using the first address as a tag; and a random access memory holding a second address corresponding to each of the entries. 5. The address conversion circuit according to claim 3, wherein the second address corresponding to an entry that matches in the address comparison operation in the associative memory is output from the address conversion unit. 6. 6. An address conversion circuit for converting the first address into a second address using a first address and a process number as tags, wherein the first address is converted to a first conversion start signal. A first associative memory that performs an address comparison operation in response to the process number, and a second associative memory that performs an address comparison operation in accordance with a second conversion start signal for the process number.
Address conversion means for converting the first address to the second address by using the address and the process number as tags, and first address holding means for holding the first address at the time of the previous conversion. Comparing means for comparing the current first address with the first address held in the address holding means; and changing the second address output by the address conversion means in response to a write signal. A second address holding unit that captures and holds, and any one of the current second address from the address conversion unit and the second address held by the second address holding unit is used as a selection signal. Selecting means for selecting and outputting the first conversion start signal in response to a request for conversion when the comparison means determines that they match. The selection signal is controlled by the selection signal so that the second address held in the second address holding means is output from the selection means, and when there is a conversion request, the comparison means determines that they do not match. Control is performed by outputting the first conversion start signal and the write signal, and controlling the selection signal so that the current second address from the address conversion means is output from the selection means. And an address conversion circuit. 7. A conversion request signal is supplied to the second associative memory as the second conversion start signal, and the control means inverts a coincidence signal output from the comparison means; A first AND gate for calculating the logical product of the request signal and the output of the inverter; and a second AND gate for calculating the logical product of the conversion request signal and the output of the coincidence signal
An AND gate, and a first D-type flip-flop that latches an output of the first AND gate based on a predetermined clock signal and outputs the latched output as the first conversion start signal,
A second D-type flip-flop for latching an output of the second AND gate based on the clock signal and outputting the output as the selection signal; and a register for latching the first conversion start signal based on the clock signal. A third D-type flip-flop that outputs as a write signal, and a fourth D-type flip-flop that latches an output of the second D-type flip-flop based on the clock signal and outputs the same as the selection signal. 7. The address conversion circuit according to claim 6, comprising: