JPH11134172A - Data modulation method, data modulation device thereof, data demodulation method and data demodulation device thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize data demodulation even when a reading error occurs by shortening a maximum inversion interval to facilitate clock reproduction and limiting worst error propagation. A parameter of a variable length code (d, k; m, n; r) is set to (1, 6; 2, 3; 5). A code having a predetermined number of 0s consecutive from the least significant bit to the high-order bit side, with the bit being an indeterminate bit, and the number of 0s and the most significant bit of the next following code to the low-order bit side. A bit at a predetermined position of a code in which the sum of the number of consecutive 0s and the maximum value is larger than the maximum run k is set as an uncertain bit, and when the constraint length r is even, a code string ((r
A conversion table 13i in which a code string in which / 2) × 3) bits do not form a repetitive pattern is used. Using this conversion table, m-bit data is converted into an n-bit code.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data modulation method and data modulation device, and a data demodulation method and data demodulation device. Specifically, among variable-length codes, a data modulation method that enables high-density recording and enables good clock reproduction is adopted, and code words that can continue error propagation indefinitely are not used. The present invention relates to a data modulation method and a data modulation device suitable for data transmission and data recording with few data errors, and a data demodulation method and a data demodulation device for reproducing data by demodulating a modulation code obtained by the data modulation.

[0002]

2. Description of the Related Art When data is transmitted using a predetermined transmission line or recorded on a recording medium such as a magnetic disk, an optical disk, or a magneto-optical disk, the data is generally transmitted in a manner suitable for the transmission or recording. Modulation is performed.

[0003] As one of such data modulation methods,
Block codes are known. The block code divides a data sequence into units of m × i bits (hereinafter referred to as data words) and converts the data words into code words of n × i bits according to an appropriate coding rule. .

This code word is a fixed-length code when i = 1, and when a plurality of i can be selected, that is, 1 to imax
When a predetermined i within the range of (maximum i) is selected and converted, a variable length code is obtained. As is well known, the block-coded codeword is a variable-length code (d, k; m,
n; r).

Here, i is the constraint length, and imax is the maximum constraint length r. d indicates the minimum continuous number of the same symbol, for example, the minimum run of 0 (zero), and k indicates the maximum continuous number of the same symbol, for example, the maximum run of 0.

In a compact disk, a mini disk, and the like, the NRZI (Non-Non-Inverting) is set such that the variable-length code obtained as described above is inverted with "1" and is not inverted with "0".
Return to Zero Inverted) modulation is performed, and an NRZI-modulated variable-length code (hereinafter, also referred to as a recording waveform sequence) is recorded.

The minimum inversion interval of the recording waveform sequence is Tmin,
When the maximum reversal interval is Tmax, the longer the minimum reversal interval Tmin is, the higher the reversal interval Tmin is to perform high-density recording in the linear velocity direction.
That is, the larger the minimum run d, the better. From the viewpoint of clock reproduction, it is desirable that the maximum inversion interval Tmax is short, that is, the maximum run k is small, and various modulation methods satisfying these are proposed.

Specifically, RLL (2) is used as a data modulation method used for a magnetic disk or a magneto-optical disk.
-7) There is modulation. The parameters of this modulation scheme are (2,
7; 1, 2; 3), and the bit interval of the recording waveform sequence is T
Then, the minimum inversion interval Tmin becomes Tmin = (d + 1) T = 3T. Assuming that the bit interval of the data string is Tdata, the minimum inversion interval Tmin is as follows: Tmin = (m / n) × Tmin = {(1/2) × 3} Tdata = 1.5Tdata

The maximum inversion interval Tmax is as follows: Tmax = (k + 1) T = (7 + 1) T = {(m / n) × Tmax} Tdata = (1/2) × 8Tdata = 4.0Tdata Further, the detection window width Tw is as follows: Tw = (m / n) T = (1/2) Tdata = 0.5Tdata

In addition, RLL (1-7) modulation is known as a modulation method used for a magnetic disk or a magneto-optical disk. The parameter of the RLL (1-7) modulation is (1, 7; 2, 3; 2), and the minimum inversion interval Tmi
n, the maximum inversion interval Tmax, and the detection window width Tw are as follows: Tmin = (1 + 1) T = (2/3) × 2 Tdata = 1.33 Tdata Tmax = (7 + 1) T = (2/3) × 8Tdata = 5.33Tdata Tw = (2/3) Tdata = 0.67Tdata.

Here, RLL (2-7) modulation and RLL (1
-7) Comparing the modulations, for example, in a magnetic disk system or a magneto-optical disk system, in order to increase the recording density in the linear velocity direction, the minimum inversion interval Tmin is 1.33 Tdat.
RLL (2-7) modulation of 1.5 Tdata is more preferable than RLL (1-7) modulation of a.

However, actually, RLL (2-
7) RLL (1-7) modulation, which is said to have a larger detection window width Tw and a larger tolerance for jitter than modulation, is often used.

However, in this RLL (1-7) modulation, the maximum inversion interval Tmax is 5.33 Tdata, and the RLL (2-
7) It is considerably larger than the 4.0 Tdata of the modulation, and therefore RLL (1-7)
Modulation is not always advantageous.

By the way, the applicant of the present invention has previously described “Japanese Patent Application No. 08-084
956, the minimum inversion interval Tmin (minimum run) and the conversion rate m are smaller than those of the RLL (1-7) modulation.
RLL (1-6) modulation in which the maximum inversion interval Tmax (maximum run k) is reduced while / n remains unchanged. This is a code word as shown in (Table 1).

(Table 1) Data code i = 1 1 11 10 × 10 010 01 00x i = 2 0011 100 010 0010 100 00x 0001 000 010 i = 3 00000 001 001 010 0000 00000 001 001 00x 00000 0001 0000 001 001 0001 001 0001 001 000 010 0000 0010 000 001 000 00x 0000 001 101 000 000 10x 0000 0000 001 000 000 10x

In the conversion table shown in Table 1, a bit at a predetermined position of a code at which the maximum run k becomes infinite when continuous is defined as an uncertain bit x. A codeword having a predetermined number of 0s consecutive from the least significant bit (LSB) to the high-order bit, and the number of 0s and the least significant bit (MSB) of the next codeword following the LSB. The bit at a predetermined position of the code word where the sum of the maximum value of 0s consecutive on the bit side is larger than the maximum run k is regarded as an uncertain bit.

The bit at the predetermined position is, for example, a bit at a position from the LSB to the d bit of the code. When the bit is set to 1, the maximum inversion interval Tma
x is the smallest bit. In the embodiment shown in Table 1, the LSB of the code word is an indeterminate bit.

The uncertain bit "x" is set to "1" or "0" depending on the number of consecutive 0s. That is,
When the number of 0s in the succeeding code word is less than the minimum run d, the uncertain bit x is set to "0", otherwise, it is set to "1". In the case of (Table 1), since d = 1, when the number of subsequent 0s is 0, that is, when the MSB of the following code is “1”, “x” becomes “1”.
It is set to "0", otherwise it is set to "1".

Assuming that the bit interval of the NRZI-modulated variable-length code (recording waveform sequence) is T, the minimum inversion interval Tmin of the variable-length code (1, 6; 2, 3; 4) in this embodiment is 2 ( = 1 + 1) T The maximum inversion interval Tmax is 7 (= 6 + 1) T The detection window width Tw is 0.67 (= ２) T The ratio of the maximum inversion interval to the minimum inversion interval Tmax / Tmin
Is 3.5 (= 7T / 2T).

That is, the variable length code (1, 6; 2,
3; 4) is RLL (1-7) modulation ｛variable length code (1,
7; 2, 3; 2) While the maximum inversion interval Tmax of｝ is 8T, the maximum inversion interval Tmax can be shortened to 7T, so that the clock can be easily reproduced.

Also, the margin for jitter is increased,
The design of the recording / reproducing device can be simplified. Further, the ratio Tmax / Tmin of the maximum inversion interval to the minimum inversion interval is:
The ratio of the (1-6) code is 3.5 with respect to the RLL (1-7) code of 4.0, and the ratio can be reduced, so that a stable code can be read. For this reason, (1-6) modulation is preferable.

[0022]

However, in Table 1, when considering the error propagation characteristics due to the bit shift of the code "1", it has been found that there is a possibility of infinite propagation. This error propagation will be described next.

For example, the data sequence is modulated into a code sequence according to (Table 1), and recording and reproduction are performed on a medium. When a reading error occurs during this recording / reproducing, it is demodulated from a code string to a data string according to the rules of (Table 1), and how many bits the error propagates and returns to the original is represented by the number of bits.

A reading error is generally expressed in an RLL code as follows:
It can be considered as a bit shift error in which the edge bit is shifted forward or backward, respectively. It is desirable that error propagation be as low as possible and therefore be recovered with as few bits as possible.

For example, as shown in FIG.
"001-000-000-10x" (x is an indeterminate bit) that encodes "0000" causes a bit shift error,
For example, consider a case in which “001-000-001-00x” is read as shown in the figure.

In this case, when decoding with reference to (Table 1), first, since there is a data string corresponding to the first code word "001", decoding is performed with this code word "001". Since a data string corresponding to “000-001-00x” exists in the following code word, decoding is performed in units of these 9 bits.
After all, the code word "001-000-000-10x" is converted to the data string "01-000".
010 ".

Since the original data string is "00000000", when the decoded data finally obtained is compared with the original data string, the second "1" to the seventh "1" span 6 bits. As a result, a bit shift error propagates and converges on the eighth data. Whether or not the convergence has occurred is determined based on whether or not a break in data at the time of decoding data has become equal to the number of original codewords (the number of data). This is because if the same code word is used as the original code word, subsequent decoding is performed in units of the same data group.

Similarly, another bit shift error mode will be described with reference to FIG. "00" as a data string
00000010 "continues, that is," 000000 "
When the data string of "10-00000010-00000010 -..." is encoded, "000-001-000-00x = 000-001"
-000-00x = 000-001-000-00x = ... ".

According to the conversion rule of (Table 1), "1" is given to the uncertain bit "x". Therefore, when encoded, "000-001-000-001 = 000-001" -000-001 = 000-001-000-0
01 = 000-001-000-001 = ... ". Assume that the following bit shift error has occurred in this code string.

"000-001-000-000 = 100-001-000-001 = 0
00-001-000-001 = 000-001-000-001 = ... "This is an example of an error in which" 1 "representing the second edge is bit-shifted backward.

When decoding with reference to (Table 1), first, decoding is performed with "000-001-000-000" at the beginning, and then "100-001".
Decryption is performed. After that, decoding is sequentially performed at the joints in the original data string in units of "000-001 = 000-001".

After all, the demodulated data when the above-mentioned bit shift error occurs is "00000010-0010-00000010-000".
00010-... ", And the error propagation due to the bit shift continues indefinitely.

As described above, even with the variable length code RLL (1-6) which enables high-density recording and good clock reproduction, an infinite continuous demodulation error due to a bit shift error may occur. In the actual data sequence, it is generally considered that the same pattern as described above does not continue forever, and since the middle of the data sequence is often delimited by Sync information or ECC data, one bit shift It is rare that demodulation errors continue indefinitely due to errors. However, the possibility of such error propagation is not desirable.

Therefore, in order to increase the density of a recording medium such as a magnetic disk or a magneto-optical disk, the detection window width Tw is increased, and the maximum inversion interval Tmax is reduced as much as possible so that an allowable amount of jitter can be secured. In the RLL (1-6) code, which facilitates clock recovery,
There is a possibility that an error propagates indefinitely due to a bit shift error of a specific bit.

Therefore, the present invention solves such a conventional problem. In the modulation using a variable-length code such as an RLL (1-6) code with good clock reproduction, error propagation is infinite. A data modulation method that removes a conversion code string that may be generated in advance and prevents infinite error propagation so that more stable data demodulation can be performed for an error caused by noise or the like. A data demodulation method for demodulating a modulation code obtained by the data modulation and reproducing data by reproducing the data.

[0036]

According to a first aspect of the present invention, there is provided a data modulation method, comprising: transmitting data having a basic data length of m bits; , K; m, n; r), when the minimum run d is 1, the code string to be converted into the variable length code, and when the same code string continues, the maximum run A bit at a predetermined position of a code where k is infinite is regarded as an uncertain bit, and the number of 0s in a code string having a predetermined number of 0s consecutive from the least significant bit to the high order bit, The sum of the number of consecutive 0s from the most significant bit to the least significant bit of the following code string is
In the first code string that is larger than the maximum run k, the bit at a predetermined position of 0 consecutive from the least significant bit to the higher bit is set as an uncertain bit, and the code “1” included in the selected code string is set. Is selected such that a decoding error does not occur indefinitely even when a bit shift error occurs in "".

In the data modulator according to the present invention, the data having the basic data length of m bits is converted into the variable length code (d, k; m, m) having the basic code length of n bits.
n; r), when the minimum run d is 1, the code sequence is converted to the variable length code, and when the same code sequence continues, the maximum run k is infinite. The bit at a predetermined position of the code is an uncertain bit, and the number of 0s in a code string having a predetermined number of 0s consecutive from the least significant bit to the high-order bit, and the most significant bit of the code string following the code string In the first code string in which the sum of the number of 0s consecutive from the upper bit to the lower bit side and the maximum value is larger than the maximum run k, a predetermined position of 0 consecutive from the least significant bit to the upper bit side is determined. There is a conversion table with bits as indeterminate bits.
It is characterized in that a code string pattern is selected so as not to cause an infinite decoding error even when a bit shift error occurs in the code "1" included in the selected code string.

In the data demodulation method according to the present invention, the minimum run d is 1 and the basic code length is an n-bit variable length code (d, k; m, n; r). When a bit shift error occurs in the code "1", a pattern of a code string that does not cause a decoding error indefinitely is selected as a selected code string, and a bit value at a predetermined position is continuous with this bit. Determining the constraint length i of the variable length code having uncertain bits determined by the number of 0s,
The variable length code of n × i bits is inversely transformed into m × i data based on the determined constraint length i.

According to a fifteenth aspect of the present invention, the minimum run d is 1, and the basic code length is an n-bit variable length code (d, k; m, n; r). When a bit shift error occurs in the code “1”, a code string pattern that does not cause an indefinite decoding error is selected as a selected code string, and the value of a bit at a predetermined position is
A constraint length determining means for determining a constraint length i of a variable length code having an uncertain bit determined by the number of 0s consecutive to this bit, and an n × i bit variable length code in an m × i data sequence An inverse conversion unit for inversely converting a variable length code into data based on the constraint length i from the constraint length determination unit by an inverse conversion table for performing an inverse conversion is provided.

In the data modulation method according to the present invention, the basic data length is m bits,
Variable-length code (d, k; m, n;
In the data modulation method for converting to r), when the minimum run d is 1, the code string is converted to the variable length code, and the maximum run k becomes infinite when the same code string continues. A bit at a predetermined position of an uncertain bit, and the number of consecutive 0s in a code string that continues from the least significant bit to the high-order bit, and a code word to be converted into a variable length code following the number, In the code word to be converted whose sum with the maximum value of the number of 0s consecutive from the most significant bit to the low order bit is larger than the maximum run k, a predetermined value of 0s consecutive from the most significant bit to the low order bit side The bit at the position is set as an uncertain bit, and even when a bit shift error occurs in the code “1” included in the selected code string,
It is characterized by selecting a code string pattern that does not cause decoding errors indefinitely.

Further, in the data modulation apparatus according to the present invention, the basic data length is m bits of data, and the basic code length is n bits of variable length codes (d, k;
m, n; r), when the minimum run d is 1, the code string to be converted into the variable length code, and when the same code string continues, the maximum run k
Is a bit at a predetermined position of a code in which is infinite, and the number of consecutive 0s in a code string continuous from the least significant bit to the high order bit, and a code to be converted into a variable length code following this A code word to be converted whose sum with the maximum value of the number of 0s consecutive from the most significant bit to the least significant bit is greater than the maximum run k, from the most significant bit to the least significant bit , And a conversion table in which bits at predetermined positions of 0 which are consecutive to are uncertain bits, and the conversion table includes codes included in the selected code string.
It is characterized in that a code string pattern that does not cause an infinite decoding error even when a bit shift error occurs in 1 ”is selected.

According to the present invention, a codeword at the time of (1-6) modulation is selected so that a demodulation error does not continue indefinitely even when a bit shift error occurs. By employing such modulation, more stable data demodulation can be realized.

As a code word pattern for which the demodulation error does not continue to infinity, such a pattern does not exist when the constraint length r is an odd number. Since there is a pattern in which the demodulation error continues infinitely when the constraint length r is an even number, a conversion rule that does not have such a pattern in the code word is defined. When imax = 5, r =
At 2, r = 4, a codeword pattern in which the demodulation error continues to infinity may appear.

[0044]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a data modulation method, a data modulation apparatus and a data demodulation method according to the present invention;

FIG. 1 shows a case where data is represented by variable-length codes (d, k; m,
1 shows an embodiment of the data modulation device 10 that converts the data into n; r).

The input data is supplied to the encoder processing unit 11, and first, the constraint length i (i = 1, 2, 3,.
.., r), and also detects data that has been converted to a code word containing an uncertain bit (hereinafter referred to as an uncertain code). Thereafter, the input data is supplied to the selector 12 and distributed to the necessary conversion tables 13a to 13r.

The conversion tables 13a to 13r have the minimum run d
Is 1 and the basic data length is m-bit data, and the basic code length is n-bit variable length code (d, k; m, n;
r), which has a conversion table as shown in Table 2 below.

The conversion table 13i (i = 1, 2, 3,...)
.., R), for example, the code value corresponding to the data is stored in advance at the address corresponding to the data. This conversion table 13i can be constituted by a ROM or the like. The selector 12 selects a conversion table 13i based on the constraint length i supplied from the encoder processing unit 11, and supplies m × i-bit data to the conversion table 13i. The conversion table 13i converts m × i-bit data into n
It is converted into a code of × i bits and output.

When an uncertain code is detected by the encoder processing unit 11, the selector 14i selects the subsequent uncertain bit processing unit 15i, and the corresponding conversion table 13
The code (including the uncertain code) from i is supplied to the uncertain bit processing unit 15i. The uncertain bit processing unit 15i, when 0 consecutively continues d or more bits before or after the uncertain bit in the code supplied from the conversion table 13i,
A process for setting the value to 1 is performed. This processing is not performed when an indeterminate code is not included.

The multiplexer 16 selects either the code from the selector 14i or the code from the uncertain bit processing unit 15i according to the uncertain code flag and the constraint length i, and outputs it as serial data. The buffer 17 temporarily stores the variable-length code from the multiplexer 16 and outputs it as a modulation code at a predetermined transfer rate.

The clock circuit (CLK) 18 generates a clock and outputs it to the timing management unit 19. The timing management unit 19 generates a timing signal in synchronization with the clock input from the clock circuit 18 and supplies the timing signal to the encoder processing unit 11 and the buffer 17.

When the variable length code (d, k; m, n; r) is, for example, a variable length code (1, 6; 2, 3; 5), that is, d which is the minimum run of 0 is 1 bit. , 0, the maximum run, is 6 bits, and the basic data length, m, is 2
When the bit and the basic code length n are 3 bits and the maximum constraint length r is 5, the conversion table 13
i is, for example, a conversion table as shown in (Table 2).

(Table 2) Data code i = 1 1 11 10 × 10 010 01 00x i = 2 0011 100 010 0010 100 00x 0001 000 010 i = 3 00000 001 001 010 0000 0000 001 001 0000 00000 0001 001 001 0001 001 0001 001 000 010 000 010 101 000 000 10 x 0000 001 001 000 000 10 xi i = 5 00000 0011 101 000 000 100 010 00000 0010 101 000 000 100 00 000 000 0001 001 000 000 100 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000

In this conversion table, the maximum constraint length imax is set to 5 in order to obtain the number of code words required for converting the input data word. The code string of the conversion table does not include a conversion code (codeword) that may propagate an error indefinitely when a bit shift error occurs. According to experiments performed by the present applicant, among the constraint lengths i included up to the maximum constraint length, there is no conversion code that can cause infinite error propagation in the conversion code when i is an odd number.

However, if i is even, ie i
= 2 or i = 4, ｛(i / 2 ×
3) Since a｝ -bit code string can be a conversion code that can cause error propagation infinitely, a conversion code in which such a code string is repeated is excluded from (Table 2). . Specifically, for example, since i = 4000 001 000 001 i = 4000 001 000 00x may have an infinite demodulation error due to a bit shift error, it is not converted to such a codeword (Table 2). ) Conversion table is selected. That is, such a conversion code is not included in the conversion table.

The order of the array may be different within each constraint length of the data string and the code string in (Table 2). For example, in the portion of Table 2 where the constraint length i = 1, Is May be replaced so as to form a sequence of code strings as shown in FIG.

In FIG. 1, the conversion table 13a has a constraint length i of 1 and converts 2 (= m × i = 2 × 1) bit data into a 3 (= n × i = 3 × 1) bit code. Is a conversion table (2-3 conversion table). Similarly, the conversion table 13b indicates that the constraint length i is 2,
6 is a 4-6 conversion table for converting (= 2 × 2) bit data into 6 (= 3 × 2) bit code. Similarly, the conversion table 14c has a 6-9 conversion table, and the conversion table 14d is an 8-12 conversion table.

In the conversion table of (Table 2), the bit at a predetermined position of the code where the maximum run k becomes infinite when the codes are continuous is regarded as the uncertain bit x. A code word having a predetermined number of 0s consecutive from the least significant bit (LSB) to the high order bit, and the number of 0s and the most significant bit (MSB) of the next succeeding code word to the low order bit The bit at a predetermined position of the code word in which the sum of the maximum values of 0s successive to the second word is larger than the maximum run k is regarded as an uncertain bit.

The bit at the predetermined position is, for example, a bit at a position from the LSB to the d bit of the code, and when the bit is set to 1, the bit at which the maximum inversion interval Tmax becomes the smallest (Table 2). In this embodiment, the LSB bit is set to #.

The uncertain bit x is set to “1” or “0” according to the number of consecutive 0s. In other words, the uncertain bit x is set to “0” when the number of subsequent 0s is less than the minimum run d, and is set to “1” otherwise. In the case of (Table 2), since d = 1, the uncertain bit x is “0” when the MSB of the following code is “1”.
And "1" otherwise.

For example, in the 2-3 conversion table 13a, a code “00x” exists. This code “00x”
When x is 0 and this code is continued, infinite number of 0s continues. That is, the maximum run k becomes infinite. Therefore, the LSB of this code is an indefinite bit x.

In the case of this embodiment, the uncertain code “00”
Since data "01" is associated with "x", data "01" is converted to a code of "000" or "001".

In this embodiment, the maximum run k
From the MSB, the maximum number of consecutive 0s is five. Therefore, if a code is used in which the number of consecutive 0s from the LSB to the upper bit side is 2 or more, if the code is followed by a code consisting of 5 consecutive 0s from the MSB, the number of consecutive 0s will be It becomes seven, which is larger than the maximum run k (= 6).

A specific example is as follows. In Table 2, i = 1
Is assumed to be "100", and for example, a code word "0000001010" of i = 3 follows this code word, seven 0s are continuous, and the maximum run k
= 6.

Therefore, the LSB of the code word “100” is set as an uncertain bit, and is set as the code word “10x”. When the MSB of the code word following the uncertain code “10x” is 1, the uncertain code “10x” is set to “100”. When the MSB of the subsequent code word is 0, the uncertain code “10x” is changed. "
101 ". (Table 2) indicates that the indeterminate code is" 10x ".
Corresponds to the input data “11”.

Similarly, in a code in which two or more 0s continue from the LSB to the upper bits, the LSB is an indefinite bit. That is, as shown in (Table 2), "10x" and "00x" at i = 1, "10000x" at i = 2, "0000100100x" at i = 3, "10100000010x" at "i = 4"
"0010000000010x""1010000010000x" and "00100000000100000x" at i = 5 are each an uncertain code.

Assuming that the bit interval of the NRZI-modulated variable length code (recording waveform sequence) is T, the minimum inversion interval Tmin = (1 + 1) for the variable length code (1, 6; 2, 3; 5) in this embodiment. ) T = 2T Maximum inversion interval Tmax = (6 + 1) T = 7T Detection window width Tw = (2/3) T = 0.67T. The ratio of the maximum inversion interval to the minimum inversion interval (Tmax / Tmin) is Tmax / Tmin = (7T / 2T) = 3.5.

Therefore, this RLL (1-6) modulation {variable length code (1, 6; 2, 3; 5)} is equal to RLL (1-6).
7) While the maximum inversion interval Tmax of the modulation {variable length code (1, 7; 2, 3; 2)} is 8T, the maximum inversion interval Tmax can be shortened to 7T, whereby the clock Reproduction is easy, the margin for jitter is large, and the design of the device is easy.

The ratio Tmax / Tmin of the maximum inversion interval to the minimum inversion interval is 4.0 in RLL (1-7) modulation and 3.5 in RLL (1-6) modulation. Since the size can be reduced, a stable code can be read.

Further, an example as shown in FIG. 3, that is, the code string is “000-001-000-001 = 000-001-000-001 = 0”
Since there is no conversion pattern "00-001-000-001 = ...", infinite propagation does not occur at the time of a bit shift error.

As described above, by performing the conversion processing shown in (Table 2) and performing the above-mentioned uncertain code processing, the worst error propagation can be made finite. As a result, it is possible to obtain a code string that can perform more stable data demodulation even when a reading error (bit shift error) due to noise or the like occurs.

Next, the operation of the data modulator 10 will be described. 1 determines the constraint length i of the input data. Therefore, the encoder processing unit 11 has a built-in table having the contents shown in (Table 2), and compares patterns of input data with reference to this table.

Referring to FIG. 4, when the input data is any of "11", "10", and "01",
It is determined that the constraint length i is 1.

The input data is "11", "10", "0"
If the data pattern does not correspond to any one of “1”, the data pattern is expanded, and it is determined whether the data pattern corresponds to any of “0011”, “0010”, and “0001”. Judge as 2.

If the input data does not correspond to the data pattern with the constraint length i = 2, the data pattern further contains "00001".
It is determined whether any one of "1", "000010", and "000001" matches, and when they match, the constraint length i is determined to be 3.

If the input data does not match the data pattern of the constraint length i = 3, the input data further becomes "00".
0000011 "," 00000010 "," 00000
001 "is determined, and if they match, the constraint length i is determined to be 4.

If the input data does not match the data pattern of the constraint length i = 4, the input data further becomes "00".
00000011 "," 00000000010 "," 0
000000001 "or" 000000000000 "is determined, and if they match, the constraint length i
Is determined to be 5. If it does not match any of these patterns, the input data is determined to be an error. By reversing the above constraint length determination processing, for example, as shown in FIG.
5, i = 4, i = 3, i = 2, i = 1. In the encoder processing unit 11, the determination result of the constraint length i is determined by the selector 12 and the multiplexer 16.
Output to When the input data matches any of the following data strings “11”, “01”, “0010”, “000010”, “00000010”, “00000001”, “00000000010”, and “00000000”, Is converted to an indeterminate code as shown in (Table 2).

Therefore, when the input data is data to be converted into an uncertain code, the encoder processing unit 11 sets the uncertain code flag to 1 and uses the flag information as the selector 14i and the multiplexer 16 Output to

The uncertain bit x is set to “1” when the MSB of the code following the uncertain bit x is “0”,
It is set to "0" when it is "1". Therefore, it is determined whether the MSB of the code following the uncertain bit x is "0" or "1", and the determination result is used as uncertain bit determination information. , To the uncertain bit processing unit 15i.

That is, as shown in (Table 2), the input data is “10”, “01”, “0001”, “00001”.
1 ”,“ 000010 ”,“ 00000011 ”,“ 0 ”
000000001 "," 0000000000001 "," 00
00000000 ", the MSB of the code to be converted is" 0 ".
Becomes When the input data is other data, that is, when the input data is “11”, “0011”, “0010”, “0000”
1 "," 00000010 "," 000000001
When these are "1" and "00000000010", they are converted into codes whose MSB is "1".

Therefore, the encoder processing section 11 sets “0” as uncertain bit determination information when the MSB of the code following the uncertain code is “0”, and sets “0” when the MSB of the code is “1”.
1 "is output to the uncertain bit processing unit 15i.

The selector 12 outputs the data supplied from the encoder processing unit 11 to the conversion table 13i corresponding to the constraint length i also supplied from the encoder processing unit 11. For example, when the constraint length i of the input data is 1, 2-bit data is output to the conversion table 13a. When the constraint length i is 2, 4-bit data is output to the conversion table 13b. When the length i is 3,
The 6-bit data is output to the conversion table 13c. When the constraint length i is 4, the 8-bit data is output to the conversion table 13d. When the constraint length i is 5, the 10-bit data is output to the conversion table 13e. Output to

The conversion table 13i stores the conversion table information shown in (Table 2). For example, the conversion table 13a stores the conversion table with the constraint length i = 1 shown in (Table 2), and the conversion table 13b stores the conversion table with the constraint length i = 2.

In each conversion table 13i, the code stored at the address specified by the input data is read. For example, in the conversion table 13a, when data "11" is input, the code "100"
Is output. Similarly, data "10" or "0"
When "1" is input, a code "010" or "000" is output, respectively.

Here, the codes “10x” and “00x” are
Although it is an uncertain code, it is assumed that it is output as “100”, “000” (x = 0) in the output stage from the conversion table.

When a code is input from the corresponding conversion table 13i, if the code is an uncertain code, the selector 14i outputs it to the corresponding uncertain bit processing unit 15i. , And output it directly to multiplexer 16. Whether the code is an uncertain code is determined based on the uncertain code flag supplied from the encoder processing unit 11.

The uncertain bit processing section 15i is connected to the selector 1
When an uncertain code is input from 4i, a process for determining the uncertain bit is executed. That is, when "0" is input as uncertain bit determination information from the encoder processing unit 11, a process of rewriting the uncertain bit to "1" is executed, and when the uncertain bit determination information is "1", A process for setting the determined bit to “0” is executed. In the above-mentioned example, the conversion table 13i is set as x = 0 for the uncertain bit x.
, The substantive processing is not performed when the uncertain bit determination information is “1”.

The multiplexer 16 outputs the code supplied from the selector 14i or the indeterminate bit processing unit 15i to the buffer 17 as serial data. The buffer 17 temporarily stores the variable length code supplied from the multiplexer 16. This variable length code is read out as a modulation code at a predetermined transfer rate and output. After the variable length code is further subjected to, for example, NRZI modulation, it is sent out to a transmission path or recorded on a recording medium.

Next, the data demodulation device 20 will be described with reference to FIG. The data demodulation device 20 receives the signal transmitted from the transmission line and the signal reproduced from the recording medium for two times.
It has an A / D converter 21 for converting into a value. The constraint length determination unit (decoder processing unit) 22 converts the digital signal into an NRZ signal based on the signal digitized by the A / D conversion unit 21.
When I-modulation is performed, this is demodulated and the constraint length i of the uncertain code or other codes is determined. Then, it outputs the demodulated signal and data indicating the constraint length to the selector (demultiplexer) 23.

The selector 23 selects one of the plurality of inverse conversion tables 24i (24a to 24r) based on the constraint length i, and adds n × n to the selected inverse conversion table 24i.
Provides an i-bit variable length code. Inversion table 24
“i” is a ROM table for inversely converting an n × i-bit variable length code into m × i-bit data, and has substantially the same conversion table as the conversion table shown in (Table 2).

The multiplexer 25 includes an inverse conversion table 24
The data from i is switched and selected and output as serial data. The buffer 26 temporarily stores the data from the multiplexer 25 and outputs the data as reproduction data. The timing circuit 27 generates a timing signal and supplies it to the A / D converter 21, the constraint length determiner 22, and the buffer 26.

Next, the operation of the data demodulation device 20 thus configured will be described with reference to FIG.

The transmission signal and the reproduction signal from the storage medium are A /
The signal is input to the D conversion unit 21 and A / D converted. The output signal from the A / D converter 21 is input to the constraint length determiner 22. If the output signal is subjected to NRZI modulation, the output signal is demodulated, and the data modulator 10 shown in FIG.
Is restored to the output modulation code. Then, determination processing of the constraint length of the modulation code is performed.

The constraint length determination unit 22 has an inverse conversion table (substantially the same as the conversion table) shown in (Table 2).
A determination is made as to whether the input modulation code is an uncertain code and a determination is made as to the constraint length of the modulation code.

First, the determination of an uncertain code will be described. For example, when the input code is “100”, the code is “10x” with the constraint length i = 1, “100010”, “10000” with the constraint length i = 2.
x ”is any one of the codes“ 1000000010 ”with the constraint length i = 3, and it cannot be determined from only the 3-bit code.

Therefore, the constraint length determination unit 22 further receives the input of a 3-bit code, and when the input code of a total of 6 bits is "1".
00010 "and" 100001 ", it is determined that the constraint length i is 2.

When the input code of 6 bits does not match the code of i = 2, or when it is "100000",
Further, a 3-bit code is received, and it is determined whether or not the total 9-bit code matches "10000000010". If they match, it is determined that the constraint length i of the code is 3.

If they do not match, the first 6 bits are "1".
If it is 00000 ", it is determined that the constraint length i = 2; otherwise, it is determined that the code is composed of the first three bits, and it is determined that the constraint length i = 1.

Similarly, when code "101" is input, the input code is code "101" with constraint length i = 1, code "101000000010x" with constraint length i = 4, and code "10100000010001" with constraint length i = 5.
0 "or" 1010000010000x "It is impossible to determine which of the four codes is received at the stage of receiving the input of the 3-bit code.

Therefore, also in this case, the constraint length determining unit 22 further receives a 9-bit code and determines whether or not the total 12-bit code matches "1010000001101". If they match, it is determined that the constraint length i = 4.

The code of 12 bits in total is "1010000".
00101 ”or“ 10100 ”
0000100 ", a further 3-bit code is input, and a total of 15-bit code is" 101000 ".
000100010 "or" 1010000001 "
0000x ″ is determined. In the case of a match, it is determined that the constraint length i of the code is 5.

If they do not match, the first 12 bits are "
If it is 10100000100 ", it is determined that the constraint length i = 4; otherwise, the code of the first three bits is" 10 ".
1 "is a code having a constraint length i = 1.

When the input 3-bit code is “000”, the input code is a code “000” with a constraint length i = 1, a code “000010” with a constraint length i = 2, and a code with a constraint length i = 3. “0000001010”, “000”
00100x ”, which is one of the codes“ 00000010000110 ”with the constraint length i = 4.In this case, as in the case described above, the input of the 3-bit code is followed by the input of the 3-bit code, and 6-bit code is "00"
0010 "is determined, and if so,
It is determined that i = 2, and if they do not match, a further 3-bit code is input.

The code of 9 bits in total is "0000".
01010 "," 0000001001 "
It is determined that the constraint length i = 3. If they do n’t match, or
000001000 ", a further 3-bit code is input, and a total of 12-bit code is" 000000 ".
1000010 "is determined, and if they match, it is determined that i = 4.

If they do not match, the first 9 bits are "0".
00001000 ", it is determined that the constraint length i = 3, otherwise, the first three-bit code" 000 "is one codeword and i = 1.

When the input 3-bit code is “001”, the input code is a code “001” with a constraint length i = 1, a code “0010000000010x” with a constraint length i = 4, and a code with a constraint length i = 5. "00100000010001
In this case, the constraint length determination unit 22 further receives an input of a 9-bit code, and determines whether or not the total 12-bit code matches “0010000000101”. If they match, it is determined that i = 4, and if they do not match, or if they are "00100000100100", a further three-bit code is input.
It is determined whether or not they match 0 "or" 001000000001000000x ". If they match, it is determined that the constraint length i = 5.

If they do not match, if the first 12 bits are “00100000100”, the constraint length i =
4; otherwise, the first 3-bit code
001 "is determined to be one codeword, and i = 1.

When the input code is "100000", this input code is one of a code "100000" with a constraint length i = 2 and a code "1000000010" with a constraint length i = 3. In this case as well, an input of a 3-bit code is further received, and a total of 9-bit code is "10000001".
0 ", and if they match, it is determined that i = 3. If they do not match, the first 6-bit code" 10 "is determined.
0000 "is determined to be one codeword, and i = 2.

When the input code is "100001", it can be immediately determined that the input code is a code of i = 2.

Further, the uncertain code “00000100”
When "0" is input, the input code is one of a code "000010001000" with a constraint length i = 3 and a code "00000010001010" with a constraint length i = 4. In this case, a code of a total of 12 bits is input. And the code is "000000100001"
0 "is determined, and when they match, i = 4
Is determined, and if they do not match, it is determined that i = 3.

The input code is an indeterminate code “0000”.
If it is 01001 ", there is no other such codeword, and it can be immediately determined that the constraint length i at that time is 3.

Uncertain code "10100000100"
Is input, the code with the constraint length i = 4 is “10100000100” The code with the constraint length i = 5 is “10100000010001”
0 ”or“ 1010000010000x. ”Also in this case, a code of a total of 15 bits is received, and the code is“ 101000001000 ”.
It is determined whether or not they match 10 "or" 1010000010000x ". When they match, it is determined that i = 5, and when they do not match, it is determined that i = 4.

The uncertain code "00100000100"
Is input, the code with the constraint length i = 4 is “00110000000100” The code with the constraint length i = 5 is “0010000000010001”
0 ”or“ 00100000000100000x. ”Also in this case, a code of a total of 15 bits is received, and the code is“ 00100000000001000 ”.
It is determined whether or not they match 10 "or" 00100000000100000x ". If they match, it is determined that i = 5, and if they do not match, it is determined that i = 4.

The input code is an indeterminate code "1010
If it is "000000101" or "0010000000101", it can be immediately determined from the bit arrangement that the constraint length i is 4.

Uncertain code "1010000000000"
When 0x "and" 00100000001000000x "are input, it is possible to immediately determine that i = 5 because there is no constraint length longer than that.

In addition to the above, for codes other than the uncertain code, when the bits constituting one code are input, the constraint length i can be immediately determined from the number of bits. That is, code “010”, “100010”, “000010” code “0000001010”, “10000000010” code “00000010001010”, “1010000”
For the code "0010001000100010", the constraint length can be immediately determined at the stage when these codes are input.

The above processing is summarized as shown in FIG. In this case, as shown in FIG.
The determination processing can be performed in the order of 5, i = 4, i = 3, i = 2, and i = 1. The selector 23 shown in FIG. 6 selects the inverse conversion table 24i according to the constraint length determination result of the constraint length determination unit 22, and supplies the code from the constraint length determination unit 22 to the corresponding inverse conversion table 24i.

That is, when the constraint length i is 1, the selector 23 supplies a 3-bit code to the inverse conversion table 24a. When i = 2, the selector 23 supplies a 6-bit code to the inverse conversion table 24b. , I = 3, a 9-bit code is supplied to the inverse conversion table 24c. Similarly, i = 4
, The 12-bit code is converted to the inverse conversion table 24d.
And when i = 5, supplies a 15-bit code to the inverse conversion table 24e.

In the reverse conversion table 24a, data "11" is written at addresses "100" and "101", data "10" is written at address "010", and data "01" is written at addresses "000" and "001". Are written respectively. Therefore, the input code "
When the input code is "100" or "101", data "11" is output, when the input code is "010", the data "10" is output, and when the input code is "000" or "001",
Data “01” is output. The other inverse conversion table 24i also stores data for inverse conversion processing as shown in (Table 2), and outputs data at the corresponding address.

The multiplexer 25 includes an inverse conversion table 24
The data supplied from i is output to the buffer 26 as serial data. The buffer 26 temporarily stores the input data, reads out the data at a predetermined transfer rate, and outputs the data.

FIG. 9 shows another embodiment of the data demodulator. In FIG. 9, the uncertain code constraint length determination unit 51
Based on the digital signal (code) input from the D conversion unit 21, the indeterminate code and the constraint length are determined. The indeterminate code flag corresponding to the determination result is output to the selector (multiplexer) 23, and the constraint length i corresponding to the determination result is output to the selectors 55A and 55B.

In the selector 23, the uncertain code constraint length determining unit 5
Both the indeterminate code and the non-indeterminate code output from 1 are given and distributed to the selectors 55A and 55B based on the indeterminate flag. If the input code is an uncertain code, the selector 5
5A, and to the selector 55B if the code is not an uncertain code.

The selector 55A selects the inverse conversion table 24i based on the constraint length i, and supplies an indeterminate code (a variable length code of n × i bits) corresponding to the constraint length i. The inverse conversion table 24i stores n × i-bit variable-length codes in m × i bits.
In the conversion table shown in (Table 2), the indeterminate code having the constraint length i is inversely converted.

The multiplexer 25A connected downstream of the inverse conversion table 24i selects data from the inverse conversion table 24i and outputs the data to the multiplexer 25C.

On the other hand, the selector 55B selects the inverse conversion table 24i 'based on the constraint length i, and supplies an uncertain code (a variable length code of n × i bits) corresponding to the constraint length i. The inverse conversion table 24i 'is for inversely converting an n.times.i-bit variable length code into m.times.i data. In the conversion table shown in (Table 2), the uncertainty of the constraint length i is determined. Inversely converts codes other than codes.

The other multiplexer 25B also selects the data from the inverse conversion table 24i ', and
Output to 5C.

The multiplexer 25C selects the data from the multiplexers 25A and 25B and outputs it to the buffer 26 as serial data. The buffer 26 temporarily stores the data from the multiplexer 25C and outputs it as reproduction data. The timing circuit 27 generates a timing signal in the same manner as in FIG. 6 and supplies it to the A / D converter 21, the uncertain code constraint length determining unit 51, and the buffer 26, respectively.

Inverse conversion table 24i and inverse conversion table 2
4i 'is an inverse conversion table corresponding to the 2-3 conversion table shown in (Table 2), that is, an inverse conversion table in which the constraint length i is 1 and a 3-bit code is inversely converted into 2-bit data. (3-2 reverse conversion table).
Therefore, the inverse conversion table 24a has an indeterminate code of the 3-2 inverse conversion table, that is, the three bits from the MSB are "000", "001", "100", "".
It consists of an inverse conversion table for the code 101 ",
The inverse conversion table 24a 'has other codes, that is, M
It becomes an inverse conversion table for a code whose 3 bits are “010” from SB.

The inverse conversion tables 24b and 24b 'are both inverse conversion tables corresponding to the 4-6 inverse conversion table shown in (Table 2), that is, the constraint length i is 2, and the code of 6 bits is converted into 4 bits. And a 6-4 inverse conversion table for performing an inverse conversion to the above data. Therefore, the reverse conversion table 24b
Is an uncertain code of the 6-4 inverse conversion table, that is, 6 bits from the MSB are “10000”.
This is an inverse conversion table for the code of "0", "100001", and the other inverse conversion table 24b 'has the other code, that is, 6 bits from the MSB, "10001".
This is an inverse conversion table for codes “0” and “000010”.

Similarly, the inverse conversion tables 24c, 24
c 'has a constraint length i of 3 and constitutes a 9-6 inverse conversion table for inversely converting a 9-bit code into 6-bit data. The next inverse conversion tables 24d and 24d' have a constraint length i of 4 and 1
Inverse conversion of 2-bit code to 8-bit data 12-
8 constitute an inverse conversion table. The reverse conversion table 24e,
24e 'has a constraint length i of 5 and constitutes a 15-10 inverse conversion table for inversely converting a 15-bit code into 10-bit data.

Next, the operation of the data demodulation device 20 will be described.

The uncertain code constraint length determining unit 51 first sets the A /
It is determined whether the modulation code input from the D conversion unit 21 includes an uncertain code. Uncertain code constraint length determination unit 51
Has the conversion table (inverse conversion table) shown in (Table 2), and determines whether or not the input code is an uncertain code with reference to the conversion table. The determination process is performed in the order shown in FIG. 7 or FIG. 8 as in the case of the constraint length determination unit 22 in FIG.

The detailed description thereof will be omitted, and the above-mentioned inverse conversion table 24a has the code “100” or “1”.
When "01" is input, data "11" is output, and when code "000" or "001" is input, data "01" is output.

The inverse conversion table 24b has a code “1000”.
When "00" or "100001" is input, data "0010" is output.
Performs the same processing.

On the other hand, the inverse conversion table 24a '
When the code “010” is input, data “10” is output. The inverse conversion table 24b 'has the code "100010"
Output data "0011" and input a code "
When "000010" is input, data "0001"
Is output. Similar processing is performed for the other inverse conversion tables 24i '.

In the data demodulation device 20 shown in FIG. 9, similarly to the data modulation device 10, the maximum inversion interval Tmax is smaller than that of the conventional RLL (1-7) code.
The reliability of the timing management unit 27 can be increased. In this data demodulation device 20, the data modulation device 10
Similarly to (Table 2), when the code of the conventional example (Table 1) is used, error propagation is infinite during bit shift.
, The worst error propagation can be made finite. As a result, more stable data demodulation can be performed even when a reading error (bit shift error) due to noise or the like occurs.

In each of the above embodiments, the conversion table (inverse conversion table) used can be changed as shown in the following (Table 5). When the codes corresponding to the respective data are exchanged as described above, the code “x00” at the constraint length i = 1, which is a code in which the maximum run k becomes infinite when continuous, is regarded as an indeterminate code.

In this case, since the maximum value of the number of consecutive 0s from the LSB to the upper bits is 5, MS
For a code in which there may be two or more consecutive 0's on the lower bit side from B, the MSB is an uncertain bit.

(Table 5) Data code i = 1 11 x01 10 010 01 x00 i = 2 0011 010 001 0010 x00 001 0001 010 000 i = 3 0000011 010 100 000 0000 001 x00 100 000 00000 0001 0000 001 0000 0001 0000 000 100 000 000 000 010 x01 00000 000 101 0000 001 x01 00000 000 100 i = 5 00000 0011 010 001 000 000 101 00000 0010 000 00 000 000 101 00000 0001 010 001 000 100 000 100 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000

When the conversion table is changed from (Table 2) to (Table 5), the encoder processing unit 11 of FIG. 1 uses the constraint length i (i = 1, 2, 3,...) Of the input data.
.., R) are determined, and the input data is “11”, “01”, “0010”, “00001”.
0 "," 00000010 "," 00000000
1 "," 00000000010 "," 00000000
00 ", it is converted to an indeterminate code according to (Table 5).

When the input data is converted into an uncertain code, the encoder processing unit 11 sets the uncertain code flag to 1 and outputs it to the selector 14i. Otherwise, the indeterminate code flag is set to 0 and output to the selector 14i. The uncertain bit decision information in the encoder processing unit 11 is 0 when the LSB of the code immediately before the uncertain code is 0, 1 when it is 1, and 1
Output to

The uncertain bit “x” is set to the immediately preceding 0
Is set to "1" or "0" depending on the number. That is,
When the number of consecutive 0s immediately before is less than d which is the minimum run, d = 1 in the case of (Table 5). Therefore, when the number of consecutive 0s immediately before is 0, that is, LSB
Is “1”,｝, “x” is “0”; otherwise, “x” is “1”.

Even if the inverse conversion table is changed from (Table 2) to (Table 5), the demodulator can be applied with the same configuration as in FIGS.

[0144]

As described above, according to the data modulation method and the data modulation apparatus according to the first and fifth aspects of the present invention, the minimum run d is set to 1, and the continuous maximum run k is set to infinity. A bit having a predetermined number of 0s consecutive from the least significant bit to the high order bit, and the number of the 0s and the most significant bit A bit at a predetermined position of 0 consecutive from the least significant bit to the upper bit side of a code whose sum with the maximum value of the number of 0s consecutive from the bit to the lower bit side is greater than the maximum run k is an indeterminate bit, As a further selected code string, at the time of bit shift of code “1”,
Since a code pattern that does not cause decoding error indefinitely is selected, the maximum inversion interval Tmax can be shortened, and the apparatus can be easily designed from the viewpoint of clock reproduction, and worst error propagation is finite. It is characterized in that a code string capable of performing more stable data demodulation can be generated in response to a read error (bit shift error) due to noise or the like.

According to the data demodulating method and the data demodulating apparatus according to the ninth and twelfth aspects of the present invention, the minimum run d is 1 and the basic code length is an n-bit variable length code (d, k). M, n; r), and a code pattern that does not cause an infinite decoding error when the code “1” is bit-shifted is selected as a selected code string, and the value of the bit at a predetermined position is The constraint length i of a variable length code having an uncertain bit determined by the number of consecutive 0s is determined, and based on the determined constraint length i, a variable length code of n × i bits is determined by m × i Since the inverse conversion into data is performed, a variable length code including an uncertain code can be reliably decoded into data.

According to the data modulation method and the data modulation apparatus according to the present invention, the predetermined position of the code where the minimum run d is 1 and the maximum run k becomes infinite when the data is continuous. Is a code having a predetermined number of 0s consecutive from the least significant bit to the most significant bit, and the number of 0s;
The sum of the number of 0s consecutive from the most significant bit to the lower bit side of the following code is larger than the maximum run k, and the sum of the codes that are larger than the maximum run k continues from the most significant bit to the lower bit side of the following code. A bit at a predetermined position of 0 is defined as an indeterminate bit,
Further, as a selected code string, a code pattern that does not cause an infinite decoding error when the code "1" is bit-shifted is selected, so that the maximum inversion interval Tmax can be shortened, and the apparatus can be reproduced from the viewpoint of clock reproduction. Of the present invention, the worst error propagation is finite, and a code string capable of performing more stable data demodulation against the occurrence of a reading error (bit shift error) due to noise or the like can be generated. Having.

Therefore, in any case, the present invention is extremely suitable for application to (1-6) modulation and the like used in optical disks and the like.

[Brief description of the drawings]

FIG. 1 is a system diagram of a main part showing an embodiment of a data modulation device according to the present invention.

FIG. 2 is a diagram illustrating error propagation in a conventional modulation table.

FIG. 3 is a diagram illustrating error propagation in a conventional modulation table.

FIG. 4 is a diagram illustrating an operation of an encoder processing unit 11 of FIG.

FIG. 5 is a diagram illustrating another operation of the encoder processing unit 11 of FIG.

FIG. 6 is a block diagram showing a configuration of one embodiment of a data demodulation device of the present invention.

FIG. 7 is a diagram illustrating the operation of a constraint length determination unit 22 in FIG. 6;

8 is a diagram illustrating another operation of the constraint length determination unit 22 in FIG.

FIG. 9 is a block diagram showing a configuration of another embodiment of the data demodulation device of the present invention.

[Explanation of symbols]

11: encoder processing unit, 12: selector, 1
3i conversion table, 14i selector, 15
i: uncertain bit processing unit, 16: multiplexer, 17: buffer, 21: A / D conversion unit, 2
2 ... constraint length determination unit, 24i ... inverse conversion table,
51 ... uncertain code constraint length determination unit

Claims (28)

[Claims] A data having a basic data length of m bits and a variable length code having a basic code length of n bits (d, k; m, n;
In the data modulation method for converting to r), a code string converted to the variable length code when the minimum run d is 1, and a code for which the maximum run k becomes infinite when the same code string is continued. The bit at the predetermined position is an indeterminate bit, and the number of 0s in a code string having a predetermined number of 0s consecutive from the least significant bit to the high order bit, and the most significant bit of the code string following the code string From the first code string whose sum with the maximum value of the number of 0s consecutive on the lower bit side is larger than the maximum run k, the bit at a predetermined position of 0 consecutive from the least significant bit to the upper bit side is The data is characterized by selecting an uncertain bit and a code string that does not cause an infinite decoding error even when a bit shift error occurs in the code "1" included in the selected code string. Modulation method. 2. A code of {(r / 2) × 3} bits when an even constraint length is given as a constraint length r included in the maximum constraint length so that an error does not propagate infinitely. 2. The data modulation method according to claim 1, wherein a code sequence that does not form a code sequence pattern that repeats the sequence is selected. 3. The data modulation method according to claim 1, wherein when 0 is continuously followed by d bits or more after the uncertain bit, the uncertain bit is set to 1. 4. The data modulation method according to claim 1, wherein a maximum run k of said variable length code is 6. 5. The data modulation method according to claim 1, wherein the maximum constraint length of the variable length code is 5 or more. 6. A data having a basic data length of m bits and a variable length code (d, k; m, n;
In the data modulator for converting to r), when the minimum run d is 1, the code sequence is converted to the variable length code and the maximum run k becomes infinite when the same code sequence continues. The bit at the predetermined position is an indeterminate bit, and the number of 0s in a code string having a predetermined number of 0s consecutive from the least significant bit to the high order bit, and the most significant bit of the code string following the code string From the first code string whose sum with the maximum value of the number of 0s consecutive on the lower bit side is larger than the maximum run k, the bit at a predetermined position of 0 consecutive from the least significant bit to the upper bit side is A conversion table with indeterminate bits is provided. This conversion table includes codes that do not cause an infinite decoding error even when a bit shift error occurs in the code “1” included in the selected code string. Row putter Data modulating apparatus characterized by down is selected. 7. A code of {(r / 2) × 3} bits when an even constraint length is given as a constraint length r included in the maximum constraint length so that an error does not propagate indefinitely. 7. The data modulation device according to claim 6, wherein a code sequence that does not form a code sequence pattern that repeats the sequence is selected. 8. The data modulation apparatus according to claim 6, further comprising a conversion table in which the uncertain bit is set to 1 when 0 continues d bits or more after the uncertain bit. 9. The data modulation apparatus according to claim 6, further comprising a conversion table in which a maximum run k of said variable length code is 6. 10. The apparatus according to claim 6, further comprising a conversion table in which a maximum constraint length of said variable length code is 5 or more.
3. The data modulation device according to claim 1. 11. A variable length code (d, k; m, n; r) having a minimum run d of 1 and a basic code length of n bits, wherein a code "1" is a bit string to be selected. When a shift error occurs, a pattern of a code string that does not cause an infinite decoding error is selected, and the value of a bit at a predetermined position is a variable having an uncertain bit determined by the number of 0s consecutive to this bit. A data demodulation method comprising: determining a constraint length i of a long code; and inversely converting an n × i-bit variable length code into m × i data based on the determined constraint length i. 12. A code of {(r / 2) × 3} bits when an even constraint length is given as the constraint length r included in the maximum constraint length so that an error does not propagate indefinitely. 12. The data demodulation method according to claim 11, wherein a code sequence that does not form a code sequence pattern that repeats the sequence is selected. 13. The data demodulation method according to claim 11, wherein a maximum run k of said variable length code is 6. 14. The data demodulation method according to claim 11, wherein the maximum constraint length of the variable length code is 5 or more. 15. A minimum run d is 1, a basic code length is an n-bit variable length code (d, k; m, n; r), and a code string “1” is selected as a code string to be selected. When a shift error occurs, a code string pattern that does not cause an infinite decoding error is selected, and the value of a bit at a predetermined position is a variable length having an uncertain bit determined by the number of 0s consecutive to this bit. A constraint length judging means for judging the constraint length i of the code; and an inverse conversion table for inversely transforming the variable length code of n × i bits into a data sequence of m × i, the constraint length from the constraint length judging means. a data converting device for converting the variable-length code into data based on i. 16. The inverse conversion table indicates that when an even-numbered constraint length is given as the constraint length r included in the maximum constraint length, エ ラ ー (r
16. The data demodulation device according to claim 15, wherein a code string that does not form a code string pattern that repeats a code string of (/ 2) × 3} bits is selected. 17. The apparatus according to claim 15, further comprising an inverse conversion table in which a maximum run k of said variable length code is 6.
3. The data demodulation device according to 1. 18. The data demodulation device according to claim 15, further comprising an inverse conversion table in which the maximum constraint length of said variable length code is 5 or more. 19. A data having a basic data length of m bits,
Variable-length code (d, k; m, n;
In the data modulation method for converting to r), a code string converted to the variable length code when the minimum run d is 1, and a code for which the maximum run k becomes infinite when the same code string is continued. A bit at a predetermined position of an uncertain bit, and the number of consecutive 0s in a code string that continues from the least significant bit to the high-order bit, and a code word to be converted into a variable length code following the number, Of the codewords to be converted whose sum with the maximum value of the number of consecutive 0s from the most significant bit to the least significant bit is greater than the maximum run k,
The bit at a predetermined position of 0 consecutive from the most significant bit to the lower bit side is set as an indeterminate bit, and even if a bit shift error occurs in the code “1” included in the selected code string, decoding is performed indefinitely. A data modulation method characterized by selecting a code string pattern that does not cause an error. 20. A code of {(r / 2) × 3} bits when an even constraint length is given as the constraint length r included in the maximum constraint length so that the error does not propagate indefinitely. 20. The data modulation method according to claim 19, wherein a code sequence that does not form a code sequence pattern that repeats the sequence is selected. 21. The data modulation method according to claim 19, wherein when 0 is continuously followed by d bits or more before the uncertain bit, the uncertain bit is set to 1. 22. The data modulation method according to claim 19, wherein the maximum run k of said variable length code is 6. 23. The data modulation method according to claim 19, wherein a maximum constraint length of said variable length code is 5 or more. 24. Data having a basic data length of m bits,
Variable-length code (d, k; m, n;
In the data modulator for converting to r), when the minimum run d is 1, the code sequence is converted to the variable length code and the maximum run k becomes infinite when the same code sequence continues. A bit at a predetermined position of an uncertain bit, and the number of consecutive 0s in a code string that continues from the least significant bit to the high-order bit, and a code word to be converted into a variable length code following the number, Of the codewords to be converted whose sum with the maximum value of the number of consecutive 0s from the most significant bit to the least significant bit is greater than the maximum run k,
A conversion table is provided in which a bit at a predetermined position of 0 consecutive from the most significant bit to the lower bit side is an indeterminate bit, and the conversion table includes a bit shift error in the code “1” included in the selected code string. A data modulation apparatus characterized in that a code string pattern is selected so that a decoding error does not occur indefinitely even when an error occurs. 25. A code of {(r / 2) × 3} bits when an even constraint length is given as the constraint length r included in the maximum constraint length so that an error does not propagate indefinitely. 26. The data modulation device according to claim 24, wherein a code sequence that does not form a code sequence pattern that repeats the sequence is selected. 26. The data modulation apparatus according to claim 24, further comprising a conversion table in which the uncertain bit is set to 1 when 0 continues continuously for d bits or more before the uncertain bit. . 27. The data modulation apparatus according to claim 24, further comprising a conversion table in which the maximum run k of the variable length code is 6. 28. The apparatus according to claim 2, further comprising a conversion table in which a maximum constraint length of said variable length code is 5 or more.
5. The data modulation device according to 4.