JPH11121932A - Multilayer wiring board and multilayer printed wiring board - Google Patents

Abstract

(57) [Problem] To provide a multilayer wiring board and a multilayer printed wiring board which are hardly affected by noise. SOLUTION: Conductor circuits (58U, 58D) disposed below an interlayer resin insulating layer (150) supporting outermost conductor circuits (158U, 158D) are used as a power supply layer and a ground layer, and via holes are formed in the conductor circuits (58U, 58D). 160U, 160D
Are directly connected, and solder bumps 76U, 7U are provided in the via holes.
Since the 6D is formed, there is no wiring for connecting the power supply layer or the ground layer and the solder bump. Therefore, the influence of noise superimposed on the wiring is eliminated, and the influence of noise when transferring signals and the like between the integrated circuit and the motherboard and relaying power supply from the motherboard can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention insulates an upper conductive circuit from a lower conductive circuit via an interlayer insulating layer, and connects the upper conductive circuit and the lower conductive circuit via via holes. The present invention relates to a multilayer wiring and a multilayer printed wiring board.

[0002]

2. Description of the Related Art In a multilayer wiring board in which a plurality of layers of conductive circuits are insulated by insulating layers, the use of one conductive circuit as a ground layer or a power supply layer is intended to reduce noise and the like. It is done in. In the multilayer wiring board according to the related art, the connection from the ground layer (or the power supply layer) to the external terminal is performed via the wiring.

A connection from the ground layer to an external terminal in the conventional multilayer printed wiring board will be described with reference to FIG. In the upper layer of the substrate 430, wirings 434A, 434B, 434C (conductor circuits) serving as ground layers are formed. The wirings 434A, 434B, 434C
Above the wiring 4 with an interlayer resin insulating layer 450 interposed
58A and a signal line 458B are formed. Further, signal lines 558C and 558D are formed above the wiring 458A and the signal line 458B with an interlayer resin insulating layer 550 interposed. Here, the signal line 458C is connected to a via hole 560C in which a solder bump 576C is formed, and the signal line 458B is connected to a via hole 560B in which a solder bump 576B is formed.
The signal lines 458C and 458B are connected to an integrated circuit chip (not shown) via 6C and 576B. The wiring 434A forming the ground layer includes a via hole 460A.
Is connected to the via hole 560 via the wiring 458A.
A is connected. The solder bump 576A connected to the via hole 560A is connected to a bump on the ground side of the integrated circuit chip.

[0004]

Here, the ground layer 4
Since the connection between 34A and the solder bump 576A is made via the wiring 458A, noise easily gets on the wiring 458A,
The noise has caused a malfunction of an electronic element connected to a multilayer wiring board such as an integrated chip. In addition, a space for routing the wiring in the multilayer wiring board is required, which hinders high density.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a multilayer wiring board and a multilayer printed wiring board which are hardly affected by noise.

[0006]

According to a first aspect of the present invention, in order to achieve the above object, an outermost conductor circuit, an insulating layer for supporting the outermost conductor circuit, and an insulating layer below the insulating layer are provided. And an inner-layer conductor circuit provided, wherein the inner-layer conductor circuit is a power supply layer and / or a ground layer, penetrates the insulating layer, and is connected to a via hole connected to the inner-layer conductor circuit. It is a technical feature that solder bumps are formed.

According to a second aspect of the present invention, there is provided a first conductive circuit of an inner layer, a first interlayer resin insulating layer formed on the first inner conductive circuit, and a first interlayer resin insulating layer formed on the first interlayer resin insulating layer. A second conductive circuit in the inner layer, and a second conductive circuit formed on the second conductive circuit.
A multilayer printed wiring board comprising an interlayer resin insulation layer and an outermost conductor circuit formed on the second interlayer resin insulation layer, wherein the inner second conductor circuit is a power supply layer and / or a ground. A via hole that penetrates through the second interlayer resin insulation layer and is connected to the second conductor circuit;
It is a technical feature that the solder bump is formed.

According to the first aspect of the present invention, the inner conductor circuit under the insulating layer supporting the outermost conductor circuit is used as a power supply layer and / or a ground layer, and a via hole is directly connected to the second conductor circuit. Since the solder bump is formed in the via hole, there is no wiring for connecting the power supply layer or the ground layer to the solder bump. For this reason, it is not affected by the noise superimposed on the wiring.

In the multilayer printed wiring board according to the present invention, the second conductor circuit provided below the second interlayer resin insulation layer supporting the outermost conductor circuit is a power supply layer and / or a ground layer. Since the via hole is directly connected to the second conductor circuit and the solder bump is formed in the via hole, there is no wiring for connecting the power supply layer or the ground layer to the solder bump. For this reason, it is not affected by the noise superimposed on the wiring.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a multilayer printed wiring board according to a first embodiment of the present invention will be described with reference to FIG. The multilayer printed wiring board according to the first embodiment whose cross section is shown in FIG. 22 constitutes a so-called integrated circuit package for mounting on a motherboard (not shown) with an integrated circuit (not shown) mounted on the upper surface. Things. The multilayer printed wiring board is provided with solder bumps (76U) on the upper surface for connection to the bump side of the integrated circuit, and solder bumps (76D) for connection to the bumps on the motherboard on the lower surface side. It plays a role of transferring signals and the like and relaying power supply from the motherboard.

An inner copper pattern 34U serving as a signal line is formed on the upper surface of the core substrate 30 of the multilayer printed wiring board, and an inner copper pattern 34D serving as a signal line is formed on the lower surface. A conductor circuit 58U for forming a power supply layer is formed above the inner layer copper pattern 34U with the interlayer resin insulating layer 50 interposed therebetween. In the upper layer of the conductor circuit 58U, a via hole 160U penetrating the outermost conductor circuit 158U and the interlayer resin insulation layer 150 via the interlayer resin insulation layer 150 is formed.
U is formed. That is, in the present embodiment, the solder bump 76U is formed in the via hole 160U attached to the conductor circuit 58U forming the power supply layer, and the power supply layer can be directly connected to an external bump (not shown). ing.

On the other hand, the upper layer of the signal line (inner copper pattern) 34D on the lower surface side of the core substrate 30 (here, the upper layer is
A conductor circuit 58 </ b> D which becomes a ground layer via an interlayer resin insulating layer 50 is formed on the upper surface with respect to 0 as the upper surface and the lower surface with respect to the lower surface of the substrate. On the upper layer of the conductor circuit 58D, an interlayer resin insulating layer 15 is provided.
A via hole 160D penetrating through the outermost conductor circuit 158D and the interlayer resin insulating layer 150 through the through hole 0 is formed with a solder bump 76D in the via hole 160D. That is, in the present embodiment, the via hole 1 attached to the conductor circuit 58D forming the ground layer is used.
A solder bump 76D is formed on 60D so that the ground layer can be directly connected to an external bump (not shown).

In the structure of the present embodiment, the conductor circuits 58U and 58D disposed below the interlayer resin insulation layer 150 supporting the outermost conductor circuits 158U and 158D are used as a power supply layer and a ground layer, respectively. Since the via holes 160U and 160D are directly connected to the 58U and 58D, and the solder bumps 76U and 76D are formed in the via holes, there is no wiring for connecting the power supply layer or the ground layer and the solder bumps. Therefore, the influence of noise superimposed on the wiring is eliminated, and the influence of noise when transferring signals and the like between the integrated circuit and the motherboard and relaying power supply from the motherboard can be reduced. Further, since there is no wiring, the density of the multilayer printed wiring board can be increased. In the multilayer printed wiring board of the present embodiment, the conductor circuit 58U is used as a power supply layer and the conductor circuit 58D is used as a ground layer. However, the conductor circuit 58U or the conductor circuit 58D functions as a power supply layer in the same layer. A conductor circuit and a conductor circuit functioning as a ground layer may be provided side by side.

Next, the manufacturing process of the multilayer printed wiring board shown in FIG. 22 will be described with reference to FIGS. (1) The starting material is a copper-clad laminate 30A in which 18 μm copper foils 32 are laminated on both sides of a core substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm (see FIG. 1). ). First, the copper-clad laminate 30A is drilled, subjected to an electroless plating process, and etched in a pattern to form inner layer copper patterns 34U and 34D and through holes 36 on both surfaces of the substrate 30 (FIG. 2). reference).

(2) The inner copper patterns 34U, 3U
The substrate 30 having the 4D and the through-hole 36 formed thereon is washed with water and dried, and then subjected to an oxidation-reduction treatment to provide a roughened layer 38 on the surfaces of the inner copper patterns 34U and 34D and the through-hole 36 (see FIG. 3).

(3) On the other hand, a resin filler for smoothing the substrate surface is adjusted. Here, bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL)
983U) 100 parts by weight of imidazole curing agent (made by Shikoku Kasei Co., 2E4MZ-CN) 6 parts by weight of 1, for these mixtures, SiO having an average particle size of 1.6μm silane coupling agent to the surface-coated ₂ Spherical particles (manufactured by Admatech, CRS1101-CE, where the maximum particle size is the thickness of the inner layer copper pattern described later (15 μm).
m) or less) 170 parts by weight, and 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, Perenol S4), and kneading with a three-roll mill to reduce the viscosity of the mixture to 23 ±
Adjust to 45,000-49,000 cps at 1 ° C,
Obtain resin filler. This resin filler is solventless. If a resin filler containing a solvent is used, the solvent is volatilized from the resin filler layer when the interlayer agent is applied, heated and dried in a later step, so that a gap between the resin filler layer and the interlayer material is generated. This causes peeling.

(4) The resin filler 40 obtained in the above (3)
Is applied to both surfaces of the substrate 30 using a roll coater to fill the space between the conductor circuits (inner copper patterns) 34U on the upper surface or in the through holes 36, and is dried at 70 ° C. for 20 minutes. And resin filler 4
0 is filled between the conductor circuits 34D or in the through holes 36 and dried at 70 ° C. for 20 minutes (see FIG. 4).

(5) The substrate 30 after the processing of the above (4)
Of the inner layer copper pattern 34 by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku).
Polishing is performed so that the resin filler 40 does not remain on the surfaces of the U and 34D and the land surface of the through hole 36, and then buffing is performed to remove the scratches caused by the belt sander polishing (see FIG. 5). Then, at 100 ° C. for 1 hour, 120
The resin filler 40 is cured by performing a heat treatment at a temperature of 3 hours at 150 ° C. for 1 hour and at 180 ° C. for 7 hours.

The surface layer of the resin filler 40 filled in the through holes 36 and the like and the conductor circuit 34
The roughened layer 38 on the upper surfaces of the U and 34D is removed to smooth both surfaces of the substrate, and the resin filler 40 and the side surfaces of the conductor circuits 34U and 34D are firmly adhered to each other through the roughened layer 38. A wiring board in which the inner wall surface and the resin filler 40 are firmly adhered via the roughened layer 38 is obtained. That is, by this step, the surface of the grease filler 40 and the inner copper patterns 34U, 3U
The 4D surface is flush with the surface. Here, the filled resin has a Tg point of 155.6 ° C. and a linear thermal expansion coefficient of 44.5.
× 10 ^-6 / ° C.

(6) On the upper surfaces of the lands of the conductor circuits 34U, 34D and the through holes 36 exposed in the processing of (5), a roughened layer (rough layer) made of a Cu—Ni—P alloy having a thickness of 2.5 μm. Then, an Sn layer having a thickness of 0.3 μm is provided on the surface of the roughened layer 42 (see FIG. 6, but the Sn layer is not shown). The formation method is as follows. That is, the substrate 30 is acid-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst. After activating this catalyst, copper sulfate 8 g / l, sulfuric acid Nickel 0.6g
/ L, citric acid 15g / l, sodium hypophosphite 29
g / l, boric acid 31 g / l, surfactant 0.1 g / l,
Plating is performed in an electroless plating bath having a pH of 9 and Cu-
The roughened layer 42 of the Ni-P alloy was formed. Then, tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l
1, a Cu-Sn substitution reaction was performed under the conditions of a temperature of 50 ° C. and a pH of 1.2 to provide a 0.3 μm thick Sn layer on the surface of the roughened layer 42 (the Sn layer is not shown).

Subsequently, a photosensitive adhesive (for an upper layer) and an interlayer resin insulator (for a lower layer) for forming an insulating layer are prepared. (7) The photosensitive adhesive (for the upper layer) is dissolved in DMDG (diethylene glycol dimethyl ether) at a concentration of 80 w
35% by weight of 25% acrylate of t% cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500), 12 parts by weight of polyether sulfone (PES), imidazole curing agent (2E4MZ-CN) 2
Parts by weight, photosensitive monomer (Toa Gosei Co., Aronix M
315) 4 parts by weight, 2 parts by weight of a photoinitiator (manufactured by Ciba Geigy, Irgacure I-907), a photosensitizer (manufactured by Nippon Kayaku,
0.2 parts by weight of DETX-S) were mixed, and 7.2 parts by weight of epoxy resin particles (manufactured by Sanyo Chemical Industries, polymer pole) having an average particle diameter of 1.0 μm were added to these mixtures, and the average particle diameter was 0%. After mixing 3.09 parts by weight of a 0.5 μm-thick and 0.5 parts by weight of an antifoaming agent (S-65 manufactured by San Nopco), the mixture was further mixed while adding 30 parts by weight of NMP to obtain a viscosity of 7 Pa.
・ S photosensitive adhesive (for upper layer) is obtained.

(8) On the other hand, interlayer resin insulating material (for lower layer)
Is a 25% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku, molecular weight 2500) dissolved in DMDG (diethylene glycol dimethyl ether).
% Acrylate, 35 parts by weight of polyethersulfone (PES), 12 parts by weight of imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 4 parts by weight of photosensitive monomer (Aronix M315, manufactured by Toa Gosei), light 2 parts by weight of an initiator (Circa Geigy, Irgacure I-907) and 0.2 part by weight of a photosensitizer (DETE-S, Nippon Kayaku) were mixed, and the mixture was mixed with epoxy resin particles (Sanyo Chemical Co., Ltd.). 0.5μm average particle size
14.49 parts by weight of an antifoaming agent (manufactured by San Nopco, S
-65) After mixing 0.5 part by weight, NMP30
By mixing while adding parts by weight, an interlayer resin insulating agent (for lower layer) having a viscosity of 1.5 Pa · s is obtained.

(9) The interlayer resin insulating material (for lower layer) having a viscosity of 1.5 Pa · s obtained in the above (7) is applied to both surfaces of the substrate with a roll coater and left in a horizontal state for 20 minutes. Thereafter, drying (prebaking) is performed at 60 ° C. for 30 minutes to form the insulating agent layer 44. Further, the photosensitive adhesive (for the upper layer) having a viscosity of 7 Pa · s obtained in the above (8) is applied on the insulating layer 44 by using a roll coater, and is applied in a horizontal state.
After leaving it for 60 minutes, drying is performed at 60 ° C. for 30 minutes to form an adhesive layer 46 (see FIG. 7).

(10) On both sides of the substrate 30 on which the insulating layer 44 and the adhesive layer 46 are formed in the above (9), 100 μm
The photomask film on which the black circle of φ is printed is brought into close contact with the photomask film, and exposed at 500 mJ / cm ² using an ultra-high pressure mercury lamp. This is spray-developed with a DMDG solution, and further, the substrate is exposed to 3000 mJ / cm ² by an ultra-high pressure mercury lamp, and is subjected to a heat treatment (post-bake) at 100 ° C. for 1 hour, and then at 150 ° C. for 5 hours. Thickness 35 having 100 μmφ opening (via hole forming opening 48) having excellent dimensional accuracy equivalent to a photomask film
A μm interlayer resin insulating layer (two-layer structure) 50 is formed (see FIG. 8). Note that the tin plating layer is partially exposed in the opening 48 serving as a via hole.

(11) The substrate 30 having the opening 48 formed
Is immersed in chromic acid for 1 minute to dissolve and remove the epoxy resin particles on the surface of the adhesive layer 46 to make the surface of the interlayer resin insulating layer 50 rough, and then to a neutralizing solution (manufactured by Shipley). After immersion, it is washed with water (see FIG. 9). Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate subjected to the surface roughening treatment, a catalyst nucleus is attached to the surface of the interlayer resin insulating layer 50 and the inner wall surface of the via hole opening 48.

(12) The substrate is immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 52 having a thickness of 1.6 μm on the entire rough surface (see FIG. 10). [Electroless plating solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C. 30 minutes at liquid temperature

(13) A commercially available photosensitive dry film is stuck on the electroless copper plating film 52 formed in the above (12), a mask is placed, and exposure is performed at 100 mJ / cm ² .
A development process is performed with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 15 μm (see FIG. 11).

(14) Next, electrolytic copper plating is applied to the non-resist-formed portion under the following conditions to form an electrolytic copper plating film 56 having a thickness of 15 μm (see FIG. 12). [Electroplating solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (captoside GL, manufactured by Atotech Japan) 1 ml / l [Electroplating conditions] Current density 1 A / dm ² hours 30 minutes Temperature Room temperature

(15) 5% KOH plating resist 54
Then, the electroless plating film 52 under the plating resist 54 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to form a film comprising the electroless copper plating film 52 and the electrolytic copper plating film 56. 58 μm conductor circuit 58U, 5
8D and via holes 60U, 60D are formed (FIG. 1).
3). Subsequently, the substrate 30 is immersed in 800 g / l chromic acid for 3 minutes to remove the palladium catalyst nuclei remaining on the roughened surface.

(16) The substrate 30 on which the conductor circuits 58U and 58D and the via holes 60U and 60D are formed is replaced with copper sulfate 8 g / l, nickel sulfate 0.6 g / l, and citric acid 15 g.
/ L, sodium hypophosphite 29g / l, boric acid 31g
/ L, a surfactant of 0.1 g / l, immersed in an electroless plating solution having a pH of 9 and a surface of the conductor circuits 58U, 58D and via holes 60U, 60D formed of copper-nickel-phosphorus having a thickness of 3 μm. A roughened layer 62 is formed (see FIG. 14). Further, a Cu—Sn substitution reaction was performed under the conditions of tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 50 ° C., and pH = 1.2, and a thickness of 0 A Sn layer of 0.3 μm is provided (the Sn layer is not shown).

(17) By repeating the above steps (2) to (16), a conductor circuit in a further upper layer is formed.
That is, an interlayer resin insulating agent (for the lower layer) is applied to both surfaces of the substrate 30 with a roller to form an insulating agent layer 144. Also, a photosensitive adhesive (for the upper layer) is provided on the insulating layer 144.
Is applied using a roll coater to form an adhesive layer 146 (see FIG. 15). Insulating agent layer 144 and adhesive layer 1
A photomask film is brought into close contact with both surfaces of the substrate 30 on which the 46 has been formed, and exposed and developed to form an interlayer resin insulating layer 150 having an opening (via hole forming opening 148). The surface is made rough (see FIG. 16). Thereafter, an electroless copper plating film 152 is formed on the surface of the substrate 30 subjected to the surface roughening treatment (see FIG. 17). Subsequently, after a plating resist 154 is provided on the electroless copper plating film 152, an electrolytic copper plating film 156 is formed on a portion where no resist is formed (see FIG. 18). Then, after the plating resist 154 is peeled off with KOH, the electroless plating film 152 under the plating resist 54 is dissolved and removed, and the conductor circuits 158U and 158D and the via holes 160 are removed.
U, 160D are formed (see FIG. 19). Further, the conductor circuits 158U, 158D and via holes 160U,
A roughened layer 162 is formed on the surface of 160D to complete a multilayer printed wiring board (see FIG. 20).

(19) Then, solder bumps are formed on the above-mentioned multilayer printed wiring board. First, adjustment of the solder resist composition for a solder bump will be described. Here, 46.67 g of a photosensitizing oligomer (molecular weight 4000) in which 50% of epoxy groups of a cresol novolak type epoxy resin (manufactured by Nippon Kayaku) of 60% by weight dissolved in DMDG were dissolved in methyl ethyl ketone was dissolved. 15.0 g of 80% by weight of bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001), imidazole curing agent (manufactured by Shikoku Chemicals, 2E4MZ-CN)
1.6 g, 3 g of a polyacrylic monomer (R604, manufactured by Nippon Kayaku), which is a photosensitive monomer, 1.5 g of a polyvalent acrylic monomer (DPE6A, manufactured by Kyoeisha Chemical Co., Ltd.), a dispersion defoaming agent (manufactured by Sannopco, S -65) 0.71 g, and 2 g of benzophenone (Kanto Kagaku) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Kagaku) as a photosensitizer were added to the mixture. A solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C. is obtained.

(20) The solder resist composition is applied to both sides of the wiring board obtained in (18) in a thickness of 20 μm. Next, after performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a circular pattern (mask pattern)
Is placed in close contact with a 5 mm thick photomask film on which is drawn, exposed to ultraviolet light of 1000 mJ / cm ² , and subjected to DMTG development processing. And at 80 ° C for 1
Time, 1 hour at 100 ° C, 1 hour at 120 ° C, 150 ° C
And a heat treatment under conditions of 3 hours, a solder resist layer (opening diameter: 200 μm) with a solder pad portion (including a via hole and its land portion) 71 opened (opening diameter: 200 μm)
70 are formed (see FIG. 21). (21) Next, the substrate 30 on which the solder resist layer 70 is formed is converted into an electroless nickel plating solution having a pH of 5 consisting of 30 g / l of nickel chloride, 10 g / l of sodium hypophosphite, and 10 g / l of sodium citrate. By immersing for 20 minutes, a nickel plating layer 72 having a thickness of 5 μm is formed in the opening 71 (see FIG. 22). Further, the substrate 30 was treated with potassium gold cyanide 2 g / l and ammonium chloride 75 g / l.
immersion in an electroless gold plating solution consisting of 50 g / l of sodium citrate and 10 g / l of sodium hypophosphite at 93 ° C. for 23 seconds to form a gold plating of 0.03 μm thickness on the nickel plating layer 72. A layer 74 is formed.

(22) The solder resist layer 70
The solder bumps 76U and 76D are formed by printing a solder paste in the opening 71 of the substrate and performing reflow at 200 ° C. to complete a multilayer printed wiring board having the solder bumps 76U and 76D.

Next, a multilayer printed wiring board according to a second embodiment of the present invention will be described with reference to FIG.
FIG. 23 is a cross-sectional view illustrating a configuration of a multilayer printed wiring board according to the second embodiment of the present invention. An inner copper pattern 234 serving as a ground layer is provided on the upper and lower surfaces of the core substrate 230.
U and 234D are formed. In other words, the ground layer (inner layer copper pattern) 234 facing with the substrate 230 interposed therebetween
A capacitor is formed by U and the ground layer (inner layer copper pattern) 234D.

A conductor circuit 258U for forming a signal line is formed above the inner layer copper pattern 234U with an interlayer resin insulating layer 250 interposed therebetween. The conductor circuit 25
Via holes 360U penetrating through interlayer resin insulation layer 350 are formed in the upper layer of 8U.
Are formed with solder bumps 376U.

On the other hand, the upper surface of the ground (inner copper pattern) 234D on the lower surface side of the substrate 230 (here, the upper layer means the upper side of the upper surface of the substrate 230 and the lower surface of the lower surface of the substrate). Is the interlayer resin insulation layer 25
A conductor circuit 258D serving as a signal line via 0 is formed. On the upper layer of the conductor circuit 258D, a conductor circuit 388D serving as a power supply layer is formed via an interlayer resin insulating layer 350. In the upper layer of the conductor circuit 388D, a via hole 380D penetrating the interlayer resin insulating layer 390 is formed, and a solder bump 376D is formed in the via hole 380D. That is, in the present embodiment, the via hole 3 attached to the conductor circuit 388D forming the power supply layer is used.
A solder bump 376D is formed on 80D so that the power supply layer can be directly connected to an external bump (not shown).

In the configuration of the second embodiment, the via hole 380D is directly connected to the conductor circuit 388D constituting the power supply layer, and the solder bump 376D is formed in the via hole, so that the power supply layer and the solder bump are connected. There is no wiring to perform. For this reason, it is not affected by the noise superimposed on the wiring.

In the above-described embodiment, the multilayer printed wiring board formed by the semi-additive method has been exemplified. However, the structure of the present invention is different from the multilayer printed wiring board formed by the full-additive method in that the multilayer printed wiring board further includes a ceramic multilayer wiring board. Needless to say, the present invention can be applied to a wiring board.

[0040]

As described above, in the multilayer wiring board according to the first aspect, the inner conductor circuit below the insulating layer supporting the outermost conductor circuit is used as a power supply layer and / or a ground layer, and the second conductor is provided. Since the via hole is directly connected to the circuit and the solder bump is formed in the via hole, there is no wiring for connecting the power supply layer or the ground layer and the solder bump. For this reason, it is not affected by the noise superimposed on the wiring. Further, since the wiring can be eliminated, it is possible to increase the density of the multilayer wiring board.

In the multilayer printed wiring board according to the present invention, the second conductive circuit provided below the second interlayer resin insulating layer supporting the outermost conductive circuit is a power supply layer and / or a ground layer. Since the via hole is directly connected to the second conductor circuit and the solder bump is formed in the via hole, there is no wiring for connecting the power supply layer or the ground layer to the solder bump. For this reason, it is not affected by the noise superimposed on the wiring. Further, since the wiring can be eliminated, it is possible to increase the density of the multilayer printed wiring board.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a multilayer printed wiring board according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 8 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 9 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 10 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 11 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 12 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 13 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 14 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 15 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 16 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 17 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 18 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 19 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 20 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 21 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 22 is a sectional view showing the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 23 is a cross-sectional view illustrating a configuration of a multilayer printed wiring board according to a second embodiment of the present invention.

FIG. 24 is a cross-sectional view illustrating a configuration of a multilayer printed wiring board according to a conventional technique.

[Explanation of symbols]

 Reference Signs List 30 substrate 34U, 34D Inner layer copper pattern (inner conductor circuit) 48 Via hole opening 50 Interlayer resin insulation layer 52 Electroless plating film 54 Plating resist 56 Electrolytic plating film 58U, 58D Conductor circuit (inner conductor circuit) 60U, 60D Via hole 76U, 76D Solder bump 150 Interlayer resin insulation layer (insulation layer) 158U, 158D Conductor circuit 160U, 160D Via hole

Claims (2)

[Claims] 1. A multilayer wiring board comprising: an outermost conductive circuit; an insulating layer that supports the outermost conductive circuit; and an inner conductive circuit provided below the insulating layer. A multilayer wiring board, wherein the conductor circuit is a power supply layer and / or a ground layer, and a solder bump is formed in a via hole penetrating the insulating layer and connected to the inner layer conductor circuit. 2. An inner-layer first conductive circuit, a first interlayer resin insulating layer formed on the first inner-layer conductive circuit, and an inner second conductive circuit formed on the first interlayer resin insulating layer. A multilayer printed wiring board comprising: a second interlayer resin insulation layer formed on the second conductor circuit; and an outermost layer conductor circuit formed on the second interlayer resin insulation layer, The second conductor circuit of the inner layer is a power supply layer and / or a ground layer, and a solder bump is formed in a via hole penetrating through the second interlayer resin insulation layer and connected to the second conductor circuit. A multilayer printed wiring board, characterized in that: