JPH11121496A - Semiconductor chip mounting structure and semiconductor device - Google Patents

Abstract

(57) Abstract: When mounting a plurality of semiconductor chips on a desired supporting member such as a substrate using a so-called chip-on-chip structure, the plurality of semiconductor chips can be formed without causing a short circuit or the like. To make the electrical connection properly. A semiconductor chip mounting structure in which a plurality of semiconductor chips (2A to 2C) are mounted on a support member (1) in a state of being stacked in a thickness direction thereof, wherein a surface of a conductive wire body (30) is insulated. It has a plurality of wires W covered by the layer 31, and the plurality of semiconductor chips 2 </ b> A to 2 </ b> C are connected to desired positions of the support member 1 via the plurality of wires W.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for appropriately mounting a plurality of semiconductor chips on a substrate or the like using a so-called chip-on-chip structure in which a plurality of semiconductor chips are stacked in their thickness direction. About technology.

[0002]

2. Description of the Related Art As is well known, when a desired electronic circuit or semiconductor device is manufactured by using a plurality of semiconductor chips, the mounting density of the semiconductor chips is increased to reduce the size of the entire electronic circuit or semiconductor device. Is often strongly required. In this case, simply arranging a plurality of semiconductor chips in a plane on the substrate has a certain limit in increasing the mounting density. In addition, making a plurality of semiconductor chips into one chip complicates the operation of manufacturing the semiconductor chips, so that the manufacturing cost becomes extremely high.

Therefore, conventionally, for example, Japanese Patent Laid-Open No.
There is a means employing a so-called chip-on-chip structure described in Japanese Patent No. 4046 or Japanese Patent Application Laid-Open No. 5-90486. This means is, for example, as shown in FIG. 9 of the present application, a means for mounting a plurality of semiconductor chips 9a to 9c on a surface of a substrate 90 in a state of being vertically stacked. According to such means, the area occupied by the semiconductor chips 9a to 9c on the surface of the substrate 90 is reduced, which is advantageous in increasing the mounting density of the semiconductor chips.

[0004]

However, conventionally, when the above-described chip-on-chip structure is employed, the following specific problems have occurred.

That is, FIG. 10 shows a configuration in which only one semiconductor chip 91 is mounted on a substrate 90 without adopting a chip-on-chip structure. In such a configuration, when the semiconductor chip 91 is connected to the terminal portion 92 of the substrate 90 via the gold wire 93d, only a plurality of gold wires 93d are arranged in a plane. On the other hand, for example, in the chip-on-chip structure shown in FIG. 9 described above, when each of the plurality of semiconductor chips 9a to 9c is connected to the terminal portion 92 of the substrate 90,
Gold wires 93a to 93c connected to one end of each of the plurality of semiconductor chips 9a to 9c are arranged so as to overlap vertically, and these gold wires 93a to 93c are three-dimensionally arranged. In addition, the number of the gold wires 93a to 93c increases as the number of semiconductor chips increases, and furthermore, the wiring pitch interval between the many gold wires 93a to 93c becomes considerably narrow.

Therefore, conventionally, when a chip-on-chip structure is employed, a plurality of gold wires 93a to 93c are more likely to come into contact with each other than when the structure is not employed. There has been a problem that a short circuit (electric short circuit) is likely to occur. Also, the upper layer 2
Gold wires 93b, 9 connected to two semiconductor chips 9b, 9c
3c may come into contact with the edge portion of the lower semiconductor chip.
In some cases, short-circuiting may occur between 3b and 93c. Of course, if such a short circuit occurred,
An electronic circuit built in a semiconductor chip cannot be operated properly, and it is necessary to surely prevent this.

The present invention has been conceived under such circumstances, and mounts a plurality of semiconductor chips on a desired support member such as a substrate by using a so-called chip-on-chip structure. In such a case, it is an object of the present invention to appropriately connect the plurality of semiconductor chips without causing a short circuit or the like.

[0008]

DISCLOSURE OF THE INVENTION In order to solve the above problems, the present invention employs the following technical means.

According to a first aspect of the present invention, there is provided a semiconductor chip mounting structure. This mounting structure of a semiconductor chip is a mounting structure of a semiconductor chip in which a plurality of semiconductor chips are mounted on a support member in a state where the semiconductor chips are stacked in a thickness direction thereof, and a surface of a conductive wire body is insulated. It has a plurality of wires covered by layers, and the plurality of semiconductor chips are connected to desired positions of the support member via the plurality of wires.

[0010] The wire may be formed by forming an insulating layer made of a synthetic resin on the surface of a gold wire.

In the present invention, a plurality of semiconductor chips are connected to desired positions of the support member by using a plurality of wires, and the plurality of wires have an insulating layer formed on a surface thereof. Therefore, even if such a plurality of wires come into contact with each other or a situation where the wires come into contact with the edge portion of the semiconductor chip, they do not become electrically conductive and the semiconductor chip There is no short circuit of the electrical wiring. on the other hand,
In the present invention, since the plurality of semiconductor chips are mounted on the support member in a state of being vertically stacked, not only can the plurality of semiconductor chips be mounted at high density, but also the electrical Connection can be easily performed by a wire bonding operation generally performed in a semiconductor chip mounting operation. As described above, according to the present invention, in a so-called chip-on-chip structure, electrical connection of a plurality of semiconductor chips can be performed by the same wire bonding operation as in the related art without causing a short circuit in the electrical wiring of the semiconductor chip. This makes it possible to perform it efficiently and properly, which is extremely useful.

According to a second aspect of the present invention, there is provided a semiconductor device. This semiconductor device is characterized by having a semiconductor chip mounting structure provided by the first aspect of the present invention.

According to the second aspect of the present invention, the same effect as obtained by the first aspect of the present invention can be expected.
A semiconductor device having a structure in which the mounting density of a plurality of semiconductor chips is high and the electrical wiring of the plurality of semiconductor chips is hardly short-circuited and appropriate electrical wiring connection is made can be obtained.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a perspective view showing an example of a semiconductor device intermediate product A having a semiconductor chip mounting structure according to the present invention. FIG. 2 is a sectional view taken along line II-II of FIG. FIG.
FIG. 3 is an exploded perspective view of the semiconductor device intermediate product A shown in FIGS. 1 and 2. FIG. 4A is a sectional view showing a wire W used in the semiconductor device intermediate product A shown in FIGS. 1 and 2, and FIG. 4B is a sectional view taken along line IV-IV of FIG. FIG.
FIG. 5 is an enlarged sectional view of a portion V in FIG. 2.

Semiconductor device intermediate product A shown in FIGS. 1 and 2
Is bonded to the substrate 1 in a state where the three semiconductor chips 2A, 2B, and 2C are overlapped with each other in the vertical direction that is the thickness direction of the three semiconductor chips 2A, 2B, and 2C.
C has a structure in which each of C is connected to the conductive wiring portion 10 of the substrate 1 via a plurality of wires W. In the present embodiment, of the semiconductor chips 2A to 2C, the lowermost semiconductor chip 2A is referred to as a first semiconductor chip. The intermediate semiconductor chip 2B is referred to as a second semiconductor chip, and the uppermost semiconductor chip 2C is referred to as a third semiconductor chip.

The substrate 1 is a film-shaped substrate having a base made of a synthetic resin film such as polyimide formed in a thin and long strip shape, and has both sides extending in the longitudinal direction. A large number of small-diameter holes 11 are used at a constant pitch and are used to transfer the particles along a predetermined transfer path. The surface of the substrate 1 is provided with a conductive wiring portion 10 (omitted for convenience in FIG. 1) provided with a plurality of pad-shaped terminal portions for wire bonding by attaching a copper foil or the like.

As best seen in FIG. 3, the substrate 1
The substrate 1 is provided with a plurality of substantially rectangular opening holes 12 in plan view that penetrate in the thickness direction of the substrate 1. The plurality of opening holes 12 are formed as a set of two adjacent opening holes 12, 12 separated by a certain distance La, and
A plurality of sets 2 and 12 are provided at appropriate intervals in the longitudinal direction of the substrate 1. Each set of opening holes 12, 1
Between the two, there is formed a band-shaped auxiliary piece 13 that partitions the opening holes 12 of each set. Each opening hole 1
2 is formed, for example, by subjecting the substrate 1 to punching and pressing. In FIG. 2, a hole denoted by reference numeral 14 is a hole used as a through hole for conducting a predetermined solder ball to the conductive wiring portion 10 in a process of manufacturing a semiconductor device described later.

Each of the three semiconductor chips 2A to 2C is configured as, for example, an LSI chip or another IC chip, and is formed by integrally integrating a desired electronic circuit on a silicon chip. It is.
The first semiconductor chip 2A is oriented such that its main surface 20A faces upward, and a part of the main surface 20A is adhered to the lower surface of the auxiliary piece 13 via an adhesive layer 30 to thereby form the first semiconductor chip 2A. It is mounted on the lower surface side of the substrate 1. A plurality of electrodes 21 for wire bonding are provided on the main surface 20A. The plurality of electrodes 21 are opposed to the opening holes 12 and the upper portion thereof is not covered with the substrate 1. Has become. Therefore, one end of the wire W (W1) can be bonded to the plurality of electrodes 21 from above. The plurality of electrodes 21 are
It is formed as a pad electrode suitable for wire bonding, and its specific material is made of aluminum. However, preferably, the surface is gold-plated as a means for improving the conductive connection with the wire W. This is the same for electrodes 22 and 23 of other semiconductor chips 2B and 2C which will be described later.

In the second semiconductor chip 2B, the main surface 20B on which the plurality of electrodes 22 are formed is oriented upward, and the back surface of the second semiconductor chip 2B is Adhered to the top surface. The second semiconductor chip 2B has a smaller width than the first semiconductor chip 2A, and is arranged at a position that does not cover above the plurality of electrodes 21 of the first semiconductor chip 2A.

The third semiconductor chip 2C is oriented such that the main surface 20C on which the plurality of electrodes 23 are formed faces upward, and the back surface of the third semiconductor chip 2C is bonded via an adhesive layer 32. The main surface 20B of the 2B is bonded to a substantially central portion of the main surface 20B. The third semiconductor chip 2C has a smaller width than the second semiconductor chip 2B,
The second semiconductor chip 2 </ b> B is arranged at a position that does not cover above the plurality of electrodes 22.

The operation of bonding the three semiconductor chips 2A to 2C to the substrate 1 is as follows. First, the adhesive is applied to the upper and lower surfaces of the auxiliary piece 13 while the substrate 1 is transported in the longitudinal direction along a fixed path. I do. Then, the first semiconductor chip 2A is brought into contact with and adheres to the lower surface of the auxiliary piece 13 using a chip mounting device. Further, as for the second semiconductor chip 2B and the third semiconductor chip 2C, these two semiconductor chips 2B and 2C are previously bonded to each other via the adhesive layer 32, and then these are combined into one. What is necessary is just to mount on the upper surface of the auxiliary piece part 13 using a chip mount device. Second semiconductor chip 2B
And the third semiconductor chip 2C are bonded in advance,
Since the work of putting the semiconductor chips 2B and 2C into the substrate 1 can be performed at the same time, there is obtained an advantage that the number of the work steps for the work can be reduced. If there is an error in the work of bonding these two semiconductor chips 2B and 2C, the semiconductor chips 2B and 2C having such a bonding work error are manufactured at a stage before they are put on the substrate 1. It can be excluded from the line in advance, which is preferable in reducing the loss of the semiconductor chip.

The plurality of wires W are used to connect the electrodes 21, 22, 23 of the three semiconductor chips 2A to 2C to the terminals of the conductive wiring portion 10, respectively. The one having the configuration shown in FIGS. 4A and 4B is used. That is, the wire W is formed by forming an insulating layer 31 of, for example, polyester on the outer peripheral surface of the gold wire 30 as the wire main body, and covering the entire outer peripheral surface of the gold wire 30 with the insulating layer 31. The gold wire 30 has a diameter of, for example, about 20 μm, similar to a conventionally used gold wire. The insulating layer 31 has a thickness of, for example, 5 μm.
It is about. Therefore, the wire W has an overall diameter of about 30 μm, and can be appropriately held by a capillary of a conventional wire bonding apparatus.

The bonding portions at both ends of the wire W actually have a structure as shown in FIG. In other words, the drawing shows both ends 32a, 32b of the wire W.
Are bonded to the electrodes 21 of the first semiconductor chip 2A and the terminals of the conductive wiring portion 10 of the substrate 1. In this structure, both ends 32 of the wire W
The configuration is such that a and 32b are not covered by the insulating layer 31, and the other surface portions of the gold wire 30 are covered by the insulating layer 31.

The above configuration will be described in more detail. In the figure, a thermo-ultrasonic bonding method is used as a bonding method of the wire W, the first bonding is performed on the electrode 21 side, and the second bonding is performed on the conductive wiring section 10 side. Have been. The first bonding is
This is performed by heating the tip end of the wire W held by a capillary (not shown) of the wire bonding apparatus to produce a gold ball and then pressing the gold ball against the surface of the electrode 21 to produce the gold ball. At times, the polyester forming the insulating layer 31 around it melts. At this time, when a gas such as air or an inert gas is blown onto the gold ball, molten polyester around the gold ball can be removed from the distal end of the wire W. Since the bonding between the electrode 21 and the wire W is performed through such a process, one end of the gold wire 30 is directly joined to the surface of the electrode 21, and the conductivity of the gold wire 30 is a conventional gold wire. As good as in the case.

On the other hand, in the second bonding, the ultrasonic wave is applied by pressing the wire W held by the capillary against the terminal portion of the conductive wiring portion 10 while heating the terminal portion of the conductive wiring portion 10. The polyester in the contacting portion is melted, and the surface of the gold wire 30 covered with the insulating layer 31 can be brought into direct contact with the conductive wiring portion 10. Therefore, even at the bonding position between the conductive wiring portion 10 and the wire W, a connection with good conductivity can be performed. Also in the case of the second bonding, the melted polyester can be removed from the bonding portion by blowing gas such as air as needed.

The structure of the wire W as described above is such that the wire W connecting the electrode 21 and the conductive wiring portion 10 is formed.
The same applies to not only (W1) but also other wires W (W2, W3) connecting the other electrodes 22, 23 and the conductive wiring portion 10, and the bonding positions at both ends of the wires W (W2, W3). Are all covered with the insulating layer 31.

In this embodiment, the bonding positions of the plurality of wires W with respect to the conductive wiring portion 10 of the substrate 1 are shifted from each other in the direction in which the wires W extend, as is clearly shown in FIG. I have. More specifically, the bonding positions N1 to N3 of the three types of wires W (W1, W2, W3), one ends of which are connected to the electrodes 21, 22, 23, respectively, with respect to the conductive wiring portion 10, are the wires W
Are displaced from each other by an appropriate dimension L in the direction in which the bonding position N2 is larger than the bonding position N1.
The bonding position N3 is a position farther from the semiconductor chips 2A to 2C than the bonding position N2.

In the semiconductor device intermediate product A, three semiconductor chips 2A to 2C are vertically stacked, and the number of wires W for electrically connecting each of these semiconductor chips 2A to 2C to the conductive wiring portion 10 is reduced. Very often, their wiring density is high. Further, the wires W are arranged so as to overlap also in the vertical height direction. However, since these many wires W each have the insulating layer 31 on the surface thereof, even if the wires W come into contact with each other, the gold wires 30, 30 which are the wire main bodies are connected. Do not come into direct contact. Therefore, it is possible to prevent the wires W from being unduly short-circuited.

On the other hand, as described in FIG. 5, one end 3 of each wire W bonded to the conductive wiring portion 10
2b is not covered by the insulating layer 31. However, in the present embodiment, since the bonding positions N1 to N3 in the conductive wiring portion 10 are shifted from each other in the direction in which the wires W extend, the bonding pitch interval between the wires W adjacent to each other in the conductive wiring portion 10 is reduced.
It can be made larger than the pitch between the wires W. Therefore, in the mounting structure of the semiconductor chip, it is preferable to prevent the bonding portions of the wires W adjacent to each other in the conductive wiring portion 10 from being unduly conducted. Further, in the above structure, in the structure viewed from the side view direction shown in FIG. 2, three types of wires W (W1 to W
3) do not overlap each other. For this reason,
Contact between the wires W can be prevented as much as possible. Since each of the wires W has the insulating layer 31 on the surface thereof, as described above, just contacting the wires W will not cause an electrical short in those portions. If the contact can be avoided, a short circuit between the wires W can be more reliably prevented, and the insulation layer 31 can be protected.

FIG. 6 is a sectional view showing an example of a semiconductor device B manufactured using the semiconductor device intermediate product A shown in FIGS. FIG. 7 is a sectional view showing an example of the manufacturing process.

To manufacture the semiconductor device B shown in FIG.
First, as shown in FIG.
A resin package operation of covering the bonding portion of the 2C and the wire W with the mold resin 4 is performed. This resin package operation is performed by, for example, a transfer molding method. Further, as the mold resin 4, for example, a thermosetting epoxy resin can be used. After that, after bonding the solder ball 5 'to the opening at the lower surface of the hole 14 provided in the substrate 1 using an adhesive or the like,
The solder ball 5 'is heated and melted and then re-hardened. When the solder ball 5 'is melted, a part thereof flows into the hole 14 and conducts with the conductive wiring portion 10. After the melting, the solder ball 5' is again formed into a ball shape by the surface tension of the solder itself. For this reason, as shown in FIG. 6, on the lower surface of the substrate 1, a protruding terminal 5 formed of a solder ball and electrically connected to the conductive wiring portion 10 is formed. The terminal 5 protrudes below the lower surface of the first semiconductor chip 2A by an appropriate dimension L1. Next, after the terminals 5 are formed in this manner, the substrate 1 is cut into an appropriate length.

According to such a series of manufacturing steps, FIG.
As shown in FIG. 7, a resin package type semiconductor device B in which three semiconductor chips 2A to 2C are stacked in a so-called chip-on-chip structure is manufactured. This semiconductor device B
For example, when the semiconductor device is mounted on a desired circuit board and used, the surface mounting by the solder reflow method can be easily performed. That is, the plurality of terminals 5 of the semiconductor device B
Is made of solder. After mounting the semiconductor device B on a desired circuit board, the circuit board is loaded into a heating furnace and the terminals 5 are heated and melted. The semiconductor device B is appropriately and electrically connected to the upper terminal, so that the surface mounting operation of the semiconductor device B can be easily and reliably performed.

In the above embodiment, since the wire body of the wire W is a gold wire which is hardly oxidized, the conductive connection to each electrode of the semiconductor chips 2A to 2C can be improved, but the present invention is not limited to this. Instead, the material of the wire body may be a material other than gold. Similarly, the specific material of the insulating layer is not limited to polyester, and another insulating material may be used. However, as the material of the insulating layer, a synthetic resin that can be heated and melted when performing wire bonding and can be removed from the wire bonding position by blowing air or the like is preferable.

In the above embodiment, since the first semiconductor chip 2A is arranged on the lower surface side of the substrate 1, the height of the second semiconductor chip 2B and the third semiconductor chip 2C from the substrate surface is increased. Can be lowered. For this reason, in the above embodiment, each of the electrodes 21 to 21 of the semiconductor chips 2A to 2C is used.
There is obtained an advantage that the height difference between each of the conductive wiring portions 23 and the conductive wiring portion 10 can be reduced, and it is possible to make these portions convenient for performing the wire bonding operation. That is, for example, when the height difference between the electrode 23 and the conductive wiring portion 10 increases, when one end of the wire W is bonded to the electrode 23 using a wire bonding apparatus, the capillary holding the wire W In some cases, the end of the wire W may not be properly thermocompression-bonded due to a large inclination obliquely with respect to the upper surface of the electrode 23. In the above-described embodiment, it is possible to appropriately prevent such a problem. it can. However, the present invention is not limited to this, and all of the plurality of semiconductor chips may be mounted in a state of being stacked on the upper surface or the lower surface of the substrate. Of course, the number of semiconductor chips is not limited to three, and the present invention can be applied to all cases where two or more semiconductor chips are mounted in a chip-on-chip structure.

Further, according to the present invention, it is not necessary to connect all of the plurality of semiconductor chips mounted in the chip-on-chip structure to predetermined positions using wires. In the present invention, as shown in FIG. 8, for example, when three semiconductor chips 2D to 2F are mounted on a substrate 1A in a state of being stacked vertically, two semiconductor chips 2 of a lowermost layer and an intermediate layer are provided.
D, 2E are connected to each other via bump electrodes 29, 29a, and two semiconductor chips 2D, 2D,
The present invention can be applied to a structure in which the electrodes 28 and 28a of the 2F are connected to predetermined positions of the substrate 1A via the wires W.

Further, in the present invention, the support member on which a plurality of semiconductor chips are mounted is not limited to a thin film-shaped substrate made of a synthetic resin, and a metal lead frame may be used. Furthermore, in the present invention, instead of the lead frame, for example, a ceramic plate-like substrate having a conductive wiring portion formed on the surface, or a synthetic resin plate-like substrate such as an epoxy resin may be used as the support member. I don't care. The specific type of the support member according to the present invention is not limited.

In addition, the mounting structure of the semiconductor chip according to the present invention and the specific configuration of each part of the semiconductor device can be variously changed in design. Regardless of the specific type of the semiconductor chip referred to in the present invention, semiconductor chips such as various memory elements such as ferroelectric memories (ferroelectrics-RAM) and various other IC chips and LSI chips can be used. Can be applied.

[Brief description of the drawings]

FIG. 1 is a perspective view showing an example of a semiconductor device intermediate product having a semiconductor chip mounting structure according to the present invention.

FIG. 2 is a sectional view taken along line II-II of FIG.

FIG. 3 is an exploded perspective view of the semiconductor device intermediate product shown in FIGS. 1 and 2;

FIG. 4A is a cross-sectional view showing a wire used in the semiconductor device intermediate product shown in FIGS. 1 and 2;
(B) is the IV-IV sectional view.

FIG. 5 is an enlarged sectional view of a portion V in FIG. 2;

FIG. 6 is a cross-sectional view illustrating an example of a semiconductor device manufactured using the semiconductor device intermediate product illustrated in FIGS. 1 and 2;

FIG. 7 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device shown in FIG.

FIG. 8 is an explanatory view showing another example of the mounting structure of the semiconductor chip according to the present invention.

FIG. 9 is an explanatory view showing an example of a conventional mounting structure of a semiconductor chip.

FIG. 10 is an explanatory view showing another example of a conventional mounting structure of a semiconductor chip.

[Explanation of symbols]

 Reference Signs List 1 substrate (supporting member) 2A first semiconductor chip 2B second semiconductor chip 2C third semiconductor chip 2D to 2F semiconductor chip 10 conductive wiring portion 21 electrode 22 electrode 23 electrode 30 gold wire (wire main body) 31 insulating layer W Wire A Intermediate semiconductor device B Semiconductor device

Claims (3)

[Claims] 1. A mounting structure of a semiconductor chip in which a plurality of semiconductor chips are mounted on a support member in a state of being stacked in a thickness direction thereof, wherein a surface of a conductive wire body is covered with an insulating layer. A semiconductor chip mounting structure, comprising: a plurality of wires, wherein the plurality of semiconductor chips are connected to desired positions of the support member via the plurality of wires. 2. The mounting structure of a semiconductor chip according to claim 1, wherein the wire is formed by forming an insulating layer made of a synthetic resin on a surface of a gold wire. 3. A semiconductor device having the semiconductor chip mounting structure according to claim 1.