JPH11120074A - Data transfer control method - Google Patents

Abstract

(57) [Summary] A control device for performing a pre-read operation for a read transfer from a processing device suppresses competition between a read transfer from the processing device to a storage device and a pre-read transfer. When a memory read request is issued from a processing device, a control device determines whether address information corresponding to data stored in an internal buffer matches an address requested by the processing device with an address comparator. If no hit is found, a preread buffer to be used is selected to directly access the storage device 40, and if hit, data is read from an internal buffer. When a pre-read request from the buffer to the storage device 40 conflicts in the control device 10, the occupation of the access to the storage device 40 by the pre-read operation is avoided by prohibiting or delaying the acceptance of the subsequent pre-read request, thereby reducing the urgency. Contention between direct access to the storage device 40 from a certain processing device and pre-read access is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data transfer control method, and more particularly, to an arbitration method when a plurality of pre-read requests are made to a control device for controlling data from a storage device to a processing device.

[0002]

2. Description of the Related Art As is well known, a pre-read circuit pre-reads data at an address following data once read into a processing device or a device near the processing device which can be accessed at a high speed. This is a circuit for ending the read cycle faster than accessing the storage device directly when the processing device next needs the data.

FIG. 17 shows an example of a typical pre-read circuit. FIG. 18 shows a control device 10 having a plurality of (three) pre-read circuits shown in FIG.
And a configuration example of a circuit including a ROM 30, a storage device 40, a bus master 50, and the like.

In FIG. 17, AC ₁ and AC ₂ are address comparators, AB ₁ and AB ₂ are address buffers, DB ₁ and D
B ₂ is a data buffer, AC ₁ , AB ₁ , and DB ₁ constitute a buffer of one stage, and AC ₂ , AB ₂ , and DB ₂ constitute another buffer of one stage. The size of the buffer of one stage is Usually, it is adjusted to the data size of the most common continuous transfer such as line fetch of the cache. In order to increase the buffer hit ratio, the buffer is often configured in a multi-stage configuration, and FIG. 17 shows a case of a two-stage configuration as an example.
Each stage of the buffer is a data buffer that stores data,
An address buffer for holding the address information of the data, and an address comparator for detecting a match between the address and the address requested by the processing device (hereinafter, referred to as a hit).

FIG. 19 is a flowchart for explaining the basic operation of the circuit shown in FIG. 18. When a memory read request is issued from the processing device 20 (S
1) The address information corresponding to the data stored in the internal buffer is matched with the address requested by the processing device 20 by the address comparator (S2). If no hit is found (miss hit), the address is used. A preread buffer to be selected is selected (S3), and direct access to the storage device 40 is performed (S4). If a hit occurs, data is read from the internal buffer (S5). Concurrently, the pre-read control device 10 invalidates the data transferred to the processing device 20 and no longer required to be held in the buffer (S6). Then, when the second-stage buffer hits or when all the data in the first-stage buffer is invalidated (S7), the contents of the second-stage buffer are shifted to the first stage and become empty. The data stored at the address subsequent to the second stage is read from the storage device (S8). Hereinafter, this operation is referred to as pre-read.

FIGS. 20, 21 and 22 and 23 are timing charts for explaining the basic operation of the pre-read. In these timing charts, the respective transfer conditions are assumed as follows. 1.32 bits are called one word and 64 bits are called one double word, and the size of the continuous data transfer requested by the processor 20 is eight words. 2. The width of a bus (hereinafter, referred to as a local bus) between the processing device 20 and the control device 10 is 1 word (= 32 bits)
It is. 3. The number of clocks at the time of 8-word continuous transfer of the local bus is 2-1-1-1-1-1-1. 4. The width of a bus (hereinafter, referred to as a memory bus) between the control device 10 and the storage device 40 is 2 words (= 1 double word = 64 bits). 5. The number of clocks at the time of continuous transfer of 8 words (= 4 double words) of the memory bus is 6-1-1-1.

The other preread buffer is not operating, and the other bus master 50 in FIG. 18 is not operating.
Is in an environment where a pre-read cycle can be immediately generated. In the figure, BR, BG, and BB are high active signals, respectively, Bus Request, Bus Grad, Bus Busy.
Is an abbreviation for A represents an address, and D represents data.

At the start of a read cycle from the processor 20, a hit check is performed in the address comparator in the buffer, and in the case of a mishit, a read request is asserted directly from the processor 20 to the storage device 40. In the case of a hit, the data is transferred from the buffer to the processing device 2.
Transfer to 0. Once an address is registered in the address buffer, the next address is automatically calculated, and if there is free space in the buffer, data reading of eight consecutive words from the storage device 40 is performed.

FIG. 20 and FIG.
In the timing chart when the continuous read transfer in word units is performed twice, the first 8-word continuous read transfer (0
CLK to 16 CLK), 17 clocks (= 8 waits) were required. However, the pre-read circuit operates, and the subsequent second 8-word continuous read transfer (17 clocks) is performed.
CLK to 26CLK) are completed in 10 clocks (= 1 wait).

FIG. 22 and FIG. 23 are timing charts when a single word read transfer from the A00 address is performed 12 times, and the first read transfer (0CLK to 9C) is performed.
LK) required 10 clocks (= 8 waits),
When the pre-read circuit operates, the following 2
The second and subsequent read transfers are completed in two clocks (= 0 wait).

[0011]

The pre-read circuit is effective as described above for continuous read access from consecutive addresses, but may be slower for random read access. .

FIGS. 24, 25 and 26 are timing charts for explaining an example in which pre-reading acts negatively. FIGS. 24, 25 and 26 show A06 and A06.
After a state in which the processor alternately reads and transfers data of two systems of 46 addresses one word at a time, A80
FIG. 9 is a timing chart in the case where data other than the above-described two systems called addresses is transferred by one word read. A0
6 and before the transfer from the A46 address starts, 2
It is assumed that the preread buffers 1 and 2 of the system are filled with data corresponding to the addresses A06 and A46, and the data corresponding to the address A80 does not exist in the preread buffers.

In such a case, while the alternate read transfer from the addresses A06 and A46 continues (0CLK to 1
5CLK), the pre-read circuit operates effectively, but when the single read transfer from the irregular A80 address occurs (16 CLK), the pre-read transfer from the pre-read buffer 2 and the direct read transfer from the processing device are performed. 10 clocks (= 8 waits, FIG. 22, FIG. 23)
(Similar to the first single transfer), the direct read transfer from the processing device is a transfer of 18 clocks (= 16 waits). In this way, the pre-read transfer of which the use is uncertain in this state is uncertain and the urgency is low, which hinders the start of the direct read transfer from the processing device having a high urgency and results in the operation of the processing device being stagnated. I have.

The present invention has been made in view of the above situation, and is located between a processing device (example CPU) and a storage device (example memory), and performs a pre-read operation for a read transfer from the processing device. In the control device, the contention between the pre-read circuit and the read transfer from the processing device to the storage device is suppressed by suppressing the contention of the pre-read circuit in the control device.

[0015]

According to a first aspect of the present invention, there is provided a control device having a plurality of sets of buffers therein, wherein the control device controls data transfer from a storage device to a processing device. In the case where a pre-read request from the buffer to the storage device conflicts in the control device, the occupation of access to the storage device by the pre-read operation is prevented by prohibiting or postponing the reception of a subsequent pre-read request, and It is characterized by suppressing contention between direct access to the storage device and pre-read access from the processing device with the possibility, thereby suppressing contention between pre-reads and increasing the speed of urgent direct read transfer from the processing device. It is intended.

According to a second aspect of the present invention, in the first aspect of the present invention, when the processing device makes a read access to the storage device, the corresponding data exists in a buffer in the control device, and When the device does not need to be accessed, the pre-read request generated by the read access or one of the pre-read requests whose acceptance has been postponed is executed, thereby increasing the use efficiency of the pre-read buffer. Therefore, it is possible to compensate for the shortage of the operation of the pre-read circuit, which is a disadvantage of the circuit of claim 1, and to perform the pre-read transfer in consideration of the conflict between the direct read transfer from the processing device and the pre-read.

According to a third aspect of the present invention, in the first or second aspect of the invention, when the processing unit accesses a bus other than the control device and the storage device bus, the pre-read request whose reception has been postponed has been delayed. (1) to increase the efficiency of use of the pre-read buffer, thereby compensating for the shortage of operation of the pre-read circuit, which is a disadvantage of the circuit of claim 1, and direct read transfer from the processing device. This makes it possible to perform pre-read transfer in consideration of contention between pre-read and pre-read.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a pre-read request inhibition signal for suppressing the occurrence of pre-read transfer when there is a possibility that a pre-read circuit may occupy a transfer request to a memory bus in a control device. Thus, the waiting time when the read transfer from the processing device must be dealt with by direct reading to the storage device is shortened, and the operation of the processing device is speeded up. .

[0019]

FIG. 1 is a flow chart for explaining an example of a data transfer control method according to the present invention, and FIGS.
Is a timing chart. In the following description, the pre-read request inhibition signal is the sum of the pre-read request and the BB (Bus Busy) of the memory bus.

According to a first aspect of the present invention, when a pre-read request from a buffer to a storage device conflicts in a control device, a pre-read operation is prohibited by prohibiting or delaying the acceptance of a subsequent pre-read request. Occupation of access to the storage device due to the above, and the conflict between the direct access to the storage device from the urgent processing device and the pre-read access is suppressed. In the flowchart shown in FIG. As described with reference to the flowchart of FIG. 19, the difference is that as shown in the flowchart of FIG. 19 and the flowchart of FIG. 1, in the present invention, the pre-read request inhibition signal is asserted as shown in S10. This is to prohibit the occurrence of pre-read when it exists.

FIGS. 24, 25 and 26 and FIGS.
In the timing chart of FIG. 4, the addresses A07 and A47 are the addresses of the last data of the first stage data buffer of the pre-read buffers 1 and 2, respectively. No data buffer is required. Therefore, in FIGS. 24, 25, and 26, a pre-read request occurs at the rising edge of the fifth and seventh CLKs. However, in the case of FIG. 2, FIG. 3, and FIG.
The pre-read request prohibition signal is asserted at the Kth position, and the pre-read request is not asserted.

As a result, in FIG. 24, FIG. 25 and FIG. 26, the direct read transfer from the processing device 20 which has been waiting during the read transfer by the pre-read buffer 2 is performed. Is performed immediately because the pre-read transfer due to is not generated. As a result, FIG.
In FIGS. 25 and 26, the direct read transfer from the processing device 20, which has been 18 clocks (= 16 waits), is reduced to 10 clocks (= 8 waits) in FIGS. 2, 3, and 4. Since the pre-read by the pre-read buffer 2 prohibited at the 7th CLK is performed when the A4a address is read at the 29th CLK, FIGS.
After 34 CLK in FIG. 4, even if access to the buffer continues, the cycle can be ended without inserting a wait.

As described above, according to the first aspect of the present invention,
Competition between pre-reads can be suppressed, and the speed of direct read transfer with high urgency from the processing device can be increased. However, in the examples shown in FIG. 2, FIG. 3, and FIG. 4, the pre-read does not occur for the A88 address. Even if the access to hit the pre-read buffers 1 and 2 continues after 34 CLK and the transfer request to the memory bus does not occur, the pre-read buffer 3 does not assert the pre-read request again, and the memory bus remains empty. Becomes for that reason,
When an access to the corresponding address occurs in the future, a wait is inserted into the transfer cycle, which causes a reduction in processing speed. Therefore, by introducing the control method described in claim 2 or 3 described below, the pre-read request is again asserted to the pre-read buffer 3 to suppress a reduction in the speed of the processing device.

(Invention of Claim 2) FIGS. 5 and 6 are flowcharts for explaining the invention of Claim 2, and FIGS.
0 is a timing chart. In the following description, the pre-read request mask signal is a signal for masking the pre-read request asserted from the pre-read buffer which asserted it, and the pre-read request arbitration circuit for the memory bus performs the pre-read request arbitration circuit. Only the pre-read request not masked by the mask signal is input.

According to a second aspect of the present invention, when the processing device makes a read access to the storage device and the corresponding data exists in a buffer in the control device and the storage device does not need to be accessed, By executing one of a pre-read request generated by a read access or a pre-read request whose acceptance has been postponed, the usage efficiency of the pre-read buffer is improved.
In the flowchart shown in FIG. 6, S1 to S10 are the same as those in the flowchart shown in FIG.
As can be seen by comparing the flowcharts of FIGS. 6A and 6B, the occurrence of pre-read is inhibited using the pre-read request mask signal (S11 to S16). That is, in FIG. 5, the corresponding data exists in the pre-read buffer (S
2) If the hit is the second-stage pre-read buffer (S11), an additional pre-read acceptance number is transmitted (S12), and the pre-read request prohibition signal is asserted in FIG. 6 (S10). When the mask signal for the pre-read cycle request is asserted (S1
In 3), it is determined whether or not the additional pre-read acceptance signal from (S12) has been received (S14). If received, the mask signal of the pre-read cycle request is negated (S15), and the pre-read from the memory is performed. This is performed (S16).

In the timing charts of FIGS. 7 to 10, the operations are the same as those in the timing charts of FIGS. The transfer cycle from 40CLK is the A4d address. Read transfer from this address is performed from the pre-read buffer 2, and no access to the storage device 40 occurs. Therefore, the pre-read request additional acceptance signal is asserted by multiplying this information by the negation of the pre-read request prohibition signal. At this point, one of the pre-read request mask signals asserted is selected, and the pre-read request mask signal is negated at the rising edge of the 41st CLK. 7 to 10
In the figure, the preread request mask signal asserted from the preread buffer 3 is negated. As a result, pre-reading is performed for the A88 address requested by the pre-read buffer 3 for the memory bus.

As described above, according to the second aspect of the present invention, it is possible to perform pre-read transfer in consideration of competition between direct read transfer from the processing device 20 and pre-read.

(Invention of Claim 3) FIGS. 11 and 12 are flow charts for explaining the invention of claim 3, FIG.
FIG. 16 to FIG. 16 are timing charts. As shown in FIG. 2, it is assumed that a local bus between the control device 10 and the processing circuit 20 has a ROM and other devices 30. Access to these devices is collectively called ROM access.

According to a third aspect of the present invention, when the processing device accesses a bus other than the control device and the storage device bus, the processing device executes one of the preread requests whose reception has been postponed, thereby providing a preread buffer. As can be seen by comparing the flowcharts of FIGS. 5 and 6 with FIGS. 11 and 12, the pre-read additional acceptance signal is also asserted when a ROM access occurs (S17). (S18).

In the timing charts of FIGS. 13 to 16, the operation is the same as that of the timing charts of FIGS. From the 40th CLK, there was access to A4d in the timing charts of FIGS. 7 to 10, but in the timing charts of FIGS. 13 to 16, access to the ROM (ROM cycle).
Is required. Generally, access to the ROM 30 is slower than access to the storage device 40. Therefore, while the access to the ROM 30 is being performed, the processing device 20 does not access the memory bus. Therefore, the product of the ROM address decode and the negation of the preread request prohibition signal is used to assert the preread request addition acceptance signal. I do. In FIGS.
At the rising edge of the eye, the pre-read request mask signal asserted from the pre-read buffer 3 is negated. As a result, pre-reading is performed for the A88 address requested by the pre-read buffer 3 for the memory bus.

As described above, by using the invention of claim 3, it is possible to perform pre-read transfer in consideration of competition between direct read transfer from the processing device and pre-read.

[0032]

According to a first aspect of the present invention, there is provided a control device having a plurality of sets of buffers therein, wherein the control device controls data transfer from a storage device to a processing device. When a pre-read request to the storage device conflicts within the control device, the occupation of access to the storage device by the pre-read operation is prevented by prohibiting or postponing the acceptance of the subsequent pre-read request, and an urgent process is performed. Since the contention between the direct access from the device to the storage device and the pre-read access is suppressed, the contention between the pre-reads can be suppressed, and the speed of the urgent direct read transfer from the processing device can be increased.

According to a second aspect of the present invention, in the first aspect of the present invention, when the processing device makes a read access to the storage device, the corresponding data exists in a buffer in the control device, and When the apparatus does not need to be accessed, the pre-read request generated by the read access or one of the pre-read requests whose acceptance has been postponed is executed to increase the efficiency of use of the pre-read buffer. In addition, it is possible to compensate for the shortage of the operation of the pre-read circuit, which is a disadvantage of the circuit of the first aspect, and to perform the pre-read transfer in consideration of the conflict between the direct read transfer from the processing device and the pre-read.

According to a third aspect of the present invention, in the first or the second aspect of the present invention, when the processing device accesses a bus other than the control device and the bus of the storage device, the pre-read request whose reception has been postponed is deferred. By executing one of the above, the use efficiency of the pre-read buffer is enhanced, so that the shortage of the operation of the pre-read circuit, which is a disadvantage of the circuit according to the first aspect, is compensated for and the direct read transfer from the processing device is performed. It is possible to perform pre-read transfer in consideration of contention between pre-read and pre-read.

[Brief description of the drawings]

FIG. 1 is a flowchart for explaining the operation of the invention of claim 1;

FIG. 2 is a partial view of a timing chart for explaining the operation of the invention of claim 1;

FIG. 3 is another partial view of the timing chart for explaining the operation of the invention of claim 1;

FIG. 4 is still another partial view of the timing chart for explaining the operation of the invention of claim 1;

FIG. 5 is a partial view of a flowchart for explaining the operation of the invention according to claim 2;

FIG. 6 is another partial view of the flowchart for explaining the operation of the invention of claim 2;

FIG. 7 is a partial view of a timing chart for explaining the operation of the invention according to claim 2;

FIG. 8 is another partial view of the timing chart for explaining the operation of the invention of claim 2;

FIG. 9 is still another partial view of the timing chart for explaining the operation of the invention according to claim 2;

FIG. 10 is still another partial view of the timing chart for explaining the operation of the invention according to claim 2;

FIG. 11 is a partial view of a flowchart for explaining the operation of the invention according to claim 3;

FIG. 12 is another partial view of the flowchart for explaining the operation of the invention of claim 3;

FIG. 13 is a partial view of a timing chart for explaining the operation of the invention of claim 3;

FIG. 14 is another partial diagram of a timing chart for explaining the operation of the invention according to claim 3;

FIG. 15 is another partial view of the timing chart for explaining the operation of the invention of claim 3;

FIG. 16 is still another partial view of the timing chart for explaining the operation of the invention according to claim 3;

FIG. 17 is a diagram illustrating a typical circuit example of a pre-read circuit.

18 is a diagram illustrating an example of an information processing circuit including the pre-read circuit illustrated in FIG.

FIG. 19 is a flowchart illustrating a basic operation of a pre-read circuit.

FIG. 20 is a part of a timing chart for explaining a basic operation (8-word continuous transfer) of the pre-read circuit.

FIG. 21 is a timing chart of a part following the timing chart shown in FIG. 20;

FIG. 22 is a part of a timing chart for explaining another basic operation (single word transfer) of the pre-read circuit.

FIG. 23 is a timing chart of a portion following the timing chart shown in FIG. 22;

FIG. 24 is a part of a timing chart for explaining an example of a case where pre-read conflicts with direct reading from the processing device to the storage device.

FIG. 25 is a diagram showing a part of a timing chart following the timing chart shown in FIG. 24;

FIG. 26 is a timing chart subsequent to the timing chart shown in FIG. 25;

[Explanation of symbols]

1-3: pre-read buffer, 10: control device, 20 ...
Processing device, 30 ROM, 40 storage device, 50 bus master.

Claims (3)

[Claims] 1. A data transfer control method in a control device having a plurality of sets of buffers therein and controlling data transfer from a storage device to a processing device, wherein a pre-read from the buffer to the storage device is performed. When requests conflict in the control device, the occupation of access to the storage device by the preread operation is prevented by prohibiting or delaying the acceptance of a subsequent preread request, and direct access from the processing device with urgency to the storage device is prevented. A data transfer control method characterized by suppressing contention between data and pre-read access. 2. When the processing device performs read access to the storage device, if the data is present in a buffer in the control device and the storage device does not need to be accessed, the read operation is performed. 2. The use efficiency of a pre-read buffer is increased by executing one of a pre-read request generated by an access and a pre-read request whose acceptance has been postponed.
The described data transfer control method. 3. The use of a pre-read buffer by executing one of pre-read requests whose acceptance has been postponed when the processing device accesses a bus other than the control device and the bus of the storage device. 3. The data transfer control method according to claim 1, wherein the efficiency is increased.