JPH11126823A - Semiconductor integrated circuit and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate circuit correction, while increasing the design freedom of the whole circuit by a method, wherein in a standard mode semiconductor integrated circuit, unwired dummy cells are arranged beforehand on a chip. SOLUTION: In a design of a semiconductor device circuit, first the chip layout on a chip 4 is automatically arranged and wired, using an automatic tool based on the circuit connection data. Next, dummy cells 3, 3A, 3B having no wiring data in high frequency of use having horizontal directional power supply wiring and ground wiring are arranged in the vacant regions between function cells causing the floating of ground wiring. In such a constitution, since the dummy cells 3, 3A, 3B having layout data on the diffused parts only are inserted, deciding the data on the diffused parts can be made with only one-time chip layout. Accordingly, the circuit correction similar to the one in the gate array mode can be facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same, and more particularly, to an LSI designed by a standard cell system.

[0002]

2. Description of the Related Art In developing and designing an application-specific LSI, there are mainly two design methods. The first design method is a gate array method. In this method,
In advance, base data such as diffusion layers and gate poly are created,
This is a method in which the customer performs only the arrangement and wiring of the function blocks prepared in the cell library in advance.

A second design method is a method called a standard cell method. This method is called a building block method.
Functions of a memory such as an AM / ROM, a CPU, a peripheral circuit, and an analog circuit can be integrated into one chip. In the case of the ASIC using the standard cell method, the function block of the logic section has a higher density than the gate array because the diffusion layer section (base) and the wiring section (upper layer) are integrated. ) Has the advantage of a small area.

[0004] The AS using the standard cell method described above
When designing an IC, the designer performs automatic placement and wiring of function cells using a CAD tool based on the circuit connection information, and then does not isolate the function cells. Therefore, as shown in FIG. A standard empty cell 10 is arranged in an empty area between 2 and 2. The standard empty cell 10 has no electrical characteristics and only connects the power supply (VDD) wiring 9 and the ground (GND) wiring 8.

However, when modifying the circuit of the standard cell type ASIC, the cell arrangement and
Wiring must be performed, and there is a disadvantage that the circuit cannot be easily changed. That is, the function cell made by the standard cell method has a problem that the development period becomes long because the diffusion layer and the wiring layer are integrated and the cell cannot be added.

In Japanese Patent Application Laid-Open No. 61-253831, a required standard cell is selected from a cell library, laid out so as to achieve a predetermined function, and the standard cell is arranged on a chip. There is shown a semiconductor device characterized in that an unwired cell by a gate array is arranged in a portion where no wiring is provided, and Japanese Unexamined Patent Publication (Kokai) No. 63-299247 discloses wiring between cell rows before wiring between cells is performed. A plurality of semiconductor elements are formed in a part of the channel in an unwired state, and at least a part of the plurality of semiconductor elements is connected as a part of an integrated circuit. The semiconductor integrated circuit and the plurality of semiconductor elements are completed up to the polysilicon wiring step in an unwired state, and are connected as a part of the integrated circuit. A standard cell type semiconductor integrated circuit characterized by being a basic cell configured as a required logic gate in a wiring step for the purpose of the present invention is disclosed in Japanese Patent Application Laid-Open No. 5-243378. In a semiconductor integrated circuit in which a plurality of standard cell rows in which a plurality of standard cells having functions are arranged are arranged across a wiring area, in one or more standard cell rows, between standard cells and / or between standard cells There is shown a semiconductor integrated circuit in which a basic cell capable of realizing a specific logical function by wiring is arranged at an end of a cell row.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of the prior art, and in particular, to facilitate the modification of a circuit, which has been difficult in the standard cell system, and to increase the degree of freedom in designing the entire circuit. It is an object of the present invention to provide an increased new semiconductor integrated circuit and a method for manufacturing the same. Another object of the present invention is to dispose a dummy cell (phantom cell).
An object of the present invention is to provide a semiconductor integrated circuit that does not adversely affect a circuit and a method for manufacturing the same.

[0008]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, a first aspect of the semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit of a standard type semiconductor integrated circuit, in which an unwired dummy cell is previously arranged in a chip to facilitate circuit correction. According to a second aspect, in addition to the above configuration, the dummy cell is a semiconductor integrated circuit in which a diffusion layer region, a gate polysilicon, and a gate oxide film are formed. As a third aspect, the dummy cell includes In a fourth aspect, the dummy cell is a semiconductor integrated circuit that includes registered function blocks having different functions.

Further, a method of manufacturing a semiconductor integrated circuit according to the present invention is a method of manufacturing a semiconductor integrated circuit of a standard type.
A method of manufacturing a semiconductor integrated circuit in which unwired dummy cells are arranged in a chip in advance and wired to the dummy cells at the time of circuit correction. In a second aspect, in addition to the above configuration, the dummy cells are , A diffusion layer region, a gate polysilicon, and a gate oxide film are formed. In a third aspect, the dummy cell is a semiconductor integrated circuit including a different functional block registered in a cell library. It is a manufacturing method.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit and a method of manufacturing the same according to the present invention provide a semiconductor integrated circuit of a standard type, in which unwired dummy cells are previously arranged in a chip to facilitate circuit correction. Since the circuit is a circuit, if the designer wants to modify the circuit, the cell (block) must be arranged and wired again. However, since the dummy cells are arranged in the chip in advance, the existing design data is used. Moreover, the design can be easily changed only by changing the mask of the aluminum wiring.

Referring to the drawings, the dummy cell used in the present invention has a simple structure having no wiring data among the data of the function cells registered in the cell library. That is, the function cell is M
The dummy cell used in the present invention is composed of an OS transistor and is composed of a diffusion layer region, a gate poly, a gate contact, and a wiring region. Among them, layout data of the wiring region, that is, the gate contact and the wiring region are deleted. ing.

The layout data of the diffusion layer / gate poly is exactly the same as the standard block layout. Therefore, when the circuit is changed, it is only necessary to change the wiring to the dummy cell, and the change is extremely easy.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a semiconductor integrated circuit and a method of manufacturing the same according to the present invention will be described below in detail with reference to the drawings.
1 is a plan view in which dummy cells are arranged, FIG. 2 is a cross-sectional view of a main part of the dummy cells, and FIG. 3 is an overall view of a chip in which dummy cells are arranged on a chip.

FIGS. 1 to 3 show dummy wirings 3 and 3 in a standard type semiconductor integrated circuit.
A semiconductor integrated circuit whose circuit modification is facilitated by arranging A and 3B in a chip 4 is shown. In the dummy cells 3, 3A and 3B, a diffusion layer region 7, a gate polysilicon 6, a gate oxide film 6A are provided. Is shown, and the dummy cells 3, 3A, 3B are registered function cells (functional blocks) having different functions.
Is shown.

Further, in a standard type semiconductor integrated circuit, unwired dummy cells 3, 3A, 3B are arranged in the chip 4 in advance, and when the circuit is modified, the dummy cells 3, 3A, 3B are wired to the dummy cells as necessary. A method of manufacturing a semiconductor integrated circuit as described above is shown. The present invention will be described in further detail. Reference numeral 2 denotes a function cell of a semiconductor integrated circuit on the chip 4, and reference numerals 3, 3A, and 3B denote dummy cells of the present invention, which are dummy cells having different circuit functions.

In the design of the semiconductor integrated circuit of the present invention, first, the chip layout on the chip 4 is automatically arranged and wired using an automatic tool based on the circuit connection information. next,
Horizontal power (VDD) wiring 9, ground (GND)
The dummy cells 3, 3A, 3B having the wiring 8 are arranged to prevent the power (VDD) wiring 9 and the ground (GND) wiring 8 from floating. Dummy cells 3, 3A, 3B having no high wiring data are arranged, and wiring of the function cells is performed automatically or manually.

The dummy cells 3, 3A and 3B have a diffusion layer (N channel, P channel), a gate poly and a power supply (V
DD) wiring 9 and ground (GND) wiring 8 only. It has only the data of the diffusion layer 7, that is,
Since it does not have the wiring data necessary for forming the transistor, it does not affect the wiring between the function cells that are normally used and the wiring between the function cells.

In addition, at the same time as a normal standard funk cell, a diffusion portion (well, gate polysilicon) of a dummy cell.
Is also formed, so that the circuit can be changed in the subsequent wiring process. When the circuit needs to be changed, the wiring can be changed so as to use the dummy cell, so that all the work does not need to be redone as in the conventional standard cell method, and therefore, the circuit change is completed in a short time. I do.

Further, by giving a unique instant name to the placed dummy cell, it is possible to know at a glance which type of cell is placed where, and it is possible to change the circuit when modifying the circuit. Work becomes easier.
Next, the operation of the embodiment of the present invention will be described. As described in the previous section, the dummy cell does not have not only the aluminum data which is the wiring data but also the contact formed on the diffusion layer as data. Therefore, even if a dummy cell is inserted, the wiring in the portion where the transistor is formed (on the source / drain side) is deleted, so that other cells on the chip are not adversely affected.

When it is necessary to modify the circuit, only the wiring work needs to be performed, so that the circuit can be modified in a short time.

[0021]

Since the present invention is constructed as described above, the circuit can be easily changed only by changing the mask of the aluminum wiring, so that the circuit can be easily changed even in the standard type ASIC. That is, since a dummy cell having only the layout data of the diffusion portion is inserted, the data of the diffusion portion can be determined by one chip layout, so that the circuit can be easily modified as in the gate array system.

Moreover, the placement of the dummy cell does not adversely affect other function cells. Also, since dummy cells having different functions can be arranged, there is an excellent effect that the degree of freedom in design is increased and the development period can be shortened. In addition, when a correction is made, a unique name is assigned to the dummy cell inserted in the layout data in advance, so that a circuit change and a layout change can be easily made by a partial correction.

[Brief description of the drawings]

FIG. 1 is a layout diagram of dummy cells used in the present invention.

FIG. 2 is a sectional view of a main part of an empty cell.

FIG. 3 is an overall view of a chip of a semiconductor integrated circuit.

FIG. 4 is a layout diagram of a standard empty cell showing a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Function cell 3 Dummy cell (empty cell) 4 Semiconductor integrated circuit 5 Contact 6 Gate polysilicon 7 Diffusion layer 8 Ground (GND) wiring 9 Power supply (VDD) wiring 10 Standard empty cell

Claims (7)

[Claims] 2. A semiconductor integrated circuit according to claim 1, wherein the circuit is easily modified by previously arranging unwired dummy cells in the chip. 2. The semiconductor integrated circuit according to claim 1, wherein said dummy cell is formed of a diffusion layer region, a gate polysilicon, and a gate oxide film. 3. The dummy cell according to claim 1, wherein the dummy cell is a function block registered in a cell library.
Or the semiconductor integrated circuit according to 2. 4. The semiconductor integrated circuit according to claim 1, wherein the dummy cells include registered function blocks having different functions. 5. A method of manufacturing a semiconductor integrated circuit according to claim 1, wherein in a standard type semiconductor integrated circuit, an unwired dummy cell is previously arranged in a chip, and when the circuit is modified, the dummy cell is wired to the dummy cell. 6. A method of manufacturing a semiconductor integrated circuit, wherein a diffusion layer region, a gate polysilicon, and a gate oxide film are formed in the dummy cell. 7. The method according to claim 6, wherein the dummy cells include different function blocks registered in a cell library.