JPH11126155A - Data sorting device and filter device using the same - Google Patents

Abstract

(57) [Problem] To provide a data rearranging apparatus which can easily cope with an arbitrary number of input data and has a small hardware amount, and a filter apparatus using the apparatus. SOLUTION: In a data rearranging device, two data are inputted, a larger data is outputted to one output terminal, and a smaller data is outputted to the other output terminal. Are provided, and these are connected in cascade in a plurality of stages as required. Further, it is possible to configure a median filter device that outputs, for example, a median using the data sorting device. In the present invention, a data rearrangement device and a filter device of an arbitrary number of input data can be easily realized, and the amount of hardware can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data rearranging apparatus and a filter apparatus using the same, and more particularly to a data rearranging apparatus which can be easily configured for an arbitrary number of input data and has a small hardware amount. The present invention relates to a device and a filter device using the device.

[0002]

2. Description of the Related Art Conventionally, linear filters have been used in the field of signal processing. However, since linear filters have limitations in several points, non-linear filters are often used especially in the field of noise removal and the like. I was Among the non-linear filters that are often used are, for example, a median filter that outputs the median value of an input signal sequence, and an order statistical filter that multiplies and adds a weighting coefficient corresponding to the rank of data value. There is. These filters are premised on rearranging a plurality of input data according to the magnitude of the value.

FIG. 7 is a block diagram showing a circuit configuration of a conventional data rearranging device used in the above-described filter device. A plurality of (three in FIG. 7) input data input to the input terminals S11 to S13 are combined two by two, and the magnitudes thereof are determined by the comparison circuits 80, 81, and 82. The data selector control signal generation circuit 83 , The overall data order is determined from the output information of the comparison circuits 80, 81 and 82, and the selection control signals for the data selectors 84, 85 and 86 are generated. The data selectors 84, 85, 86 select desired data from the input data, and
It outputs to 41-S43. In general, if the number of data is n, nC2 comparison circuits and n input data selectors are required.

[0004]

In general, the number of input data of the median filter and the order statistical filter is at least 3 × 3 = 9 in the case of an image, and the effect is not obtained unless the number is nine. Some require more input data. However, in the above-described conventional data rearranging apparatus, when the number n of input data is relatively small, rearrangement can be performed with a simple configuration. However, when n is large, the data selector control signal generation circuit 83 However, there is a problem that the circuit scale of the above becomes large and individual design is required according to n. SUMMARY OF THE INVENTION It is an object of the present invention to provide a data rearranging apparatus which solves the above-mentioned problems of the prior art, can easily cope with an arbitrary number of input data, and has a small amount of hardware, and a filter apparatus using the apparatus. Is to do.

[0005]

According to the present invention, in a data rearranging apparatus, two data are inputted, a larger data is outputted to one output terminal, and a smaller data is outputted to the other output terminal. It is characterized in that a plurality of data rearranging circuits to be output are provided, and a plurality of these data rearranging circuits are cascaded, and a filter device using the data rearranging device is also characterized. In the present invention, by combining a plurality of two-input data rearranging circuits having the same configuration, a data rearranging device having an arbitrary number of input data and a filter device using the data rearranging device can be easily realized. .

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the data sorting device of the present invention. In FIG. 1, the number of input data is 3, and each data is input terminal S1.
1 to S13. The data rearranging apparatus of FIG. 1 includes three two-input data rearranging circuits 10 to 1 having the same configuration.
Consists of two.

The data rearranging circuits 10 to 12 include, for example, a comparison circuit 20, two data selector circuits 21, 22,
It consists of an inverter 23. The comparison circuit 20 compares the two input data, and outputs “1” when the value of the input data on the upper side (S11) is larger, and outputs “0” otherwise. Two data selectors 2
When the control terminal is "0", the output data of the upper side (S11) are output when the control terminal is "1", and when the control terminal is "1", the input data of the lower side (S12) is output.

Since a control signal is input to the control terminal of the data selector 22 via the inverter 23, the input data having a small value is output to the terminal S21 and the input data having a large value is output to the terminal S22. Will be. Similarly, the other rearranging circuits 11 and 12 output data having a small value to the upper output terminal and data having a large value to the lower output terminal.

An output terminal (hereinafter, referred to as a (large) output terminal) S22 for outputting a large value of the data rearranging circuit 10 is connected to an upper input terminal of the data rearranging circuit 11 at the next stage, and the other lower side. The side input terminal is connected to the input terminal S13 of the device. The (low) output terminal S21 of the first-stage data rearranging circuit 10 is connected to the upper input terminal of the third-stage data rearranging circuit 12, and the second-stage data rearranging circuit 11 is connected to the lower input terminal. (Large) output terminal S32 is connected.

Next, the operation will be described. In FIG. 1, for example, "3" is input to the input terminal S11, "2" is input to S12, and S13 is input.
It is assumed that “1” has been input to the key (indicated by parentheses in FIG. 1). “1” is output from the comparison circuit 20 of the first-stage data rearrangement circuit 10, “2” is output from the data selector 21, and “3” is output from the data selector 22. In the second-stage data rearranging circuit 11, "3" and "1" are input, "1" is inputted to the upper (small) output terminal S32, and "1" is outputted to the lower (large) output terminal S43.
Is output as "3". In the third-stage data rearrangement circuit 12, "2" and "1" are input, "1" is input to the upper (small) output terminal S41, and "1" is input to the lower (large) output terminal S42. 2 "is output. By the operation as described above, the output terminals S41 to S43 are arranged in the order of smaller values.
2 is a block diagram showing the configuration of another embodiment of the data rearranging circuit.
In the data rearrangement circuit 10 shown in FIG. 2, the inverter 23 is used. In the data rearrangement circuit 30 shown in FIG. 2, the connections of the data selector 32 and the data selector 33 to the input terminals are reversed. Thus, the inverter is omitted, and the output signal of the comparison circuit 31 is directly input to the control terminals of the two data selectors.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the data rearranging apparatus. This embodiment is shown in FIG.
A D-type flip-flop (FF) is added to the first embodiment shown in FIG. 1 to enable high-speed operation or pipeline operation. In the first embodiment shown in FIG. 1, it is necessary to hold input data of the first stage until data is output from the output terminal of the last stage. However, in the second embodiment shown in FIG. 3, D-type FFs 43 to 48 for latching data are provided between the stages,
For example, by latching with a clock signal whose period is the operation time of one data rearranging circuit 40, data can be input at the clock period and a rearranged result can be obtained. In FIG. 3, D-type FFs may be provided at the input terminal and the output terminal as needed.

FIG. 4 is a block diagram showing the configuration of a third embodiment of the data sorting apparatus. This embodiment is a configuration example of a data rearranging device when the number of input data is 4, and the configuration of each data rearranging circuit 50 to 55 is the same as that of the first embodiment shown in FIG. 1 or FIG. is there. In two vertically arranged data rearranging circuits (for example, 50 and 51) in the same stage, one data rearranging circuit (5
0) and the other (upper) output terminal of the other data rearranging circuit (51) are connected to the input terminal of one data rearranging circuit (52) in the next stage, respectively. As described above, the data rearranging circuits 50 to 55 are cascade-connected in a plurality of stages.

In this embodiment, for example, when values from "4" to "1" are sequentially input to each input terminal from the top, as shown in parentheses in FIG. The outputs of the replacement circuits 50 and 51 are “3, 4,
1, 2 ". Similarly, the output of the second stage is" 3, 1, 4, 2 "in order from the top, and the output of the third stage is" in order from the top. "
1, 3, 2, 4 ", the output of the fourth stage is" 1,
2, 3, 4 ", and the rearrangement is completed.

In general, when the input data number n is an even number, n / 2 data rearranging circuits are used for even-numbered stages and n / 22-1 data rearranging circuits are used for odd-numbered stages. Are cascaded for n stages. Therefore, the number of required data rearrangement circuits is (n / 2) * (n / 2) + (n / 2-1) * (n / 2) = (n-1) * (n / 2) In the example of FIG. 4, since n = 4, the number of circuits is 6.

FIG. 5 is a block diagram showing the configuration of a fourth embodiment of the data sorting apparatus. This embodiment is a configuration example of a data rearranging apparatus when the number of input data is 9, and the configuration of each data rearranging circuit 60 is the same as that of the first embodiment shown in FIG. 1 or FIG. Further, the data rearranging circuits 60 are cascaded in a plurality of stages according to the same rules as in the third embodiment shown in FIG.

In this embodiment, input / output values of each data rearranging circuit when values from "9" to "1" are input to each input terminal in order from the top are shown in parentheses in FIG. Finally, the output of the ninth stage is “1,
2, ..., 9 ", and the rearrangement is completed. Generally,
If the input data number n is an odd number, (n-
1) Using two data rearranging circuits, cascading the rearranging circuits in n stages. Therefore, the required number of data rearranging circuits is n * (n-1) / 2, and in the example of FIG.
Since the number is 9, the number of circuits is 36.

FIG. 6 is a block diagram showing the configuration of a filter device using the data sorting device of the present invention. In this embodiment, for example, an image signal of a raster scan system such as a digitized NTSC signal is input, and the median value of pixel data within a predetermined range (3 × 3) Median that outputs a value
an) Filter device.

The filter device shown in FIG. 6 includes a signal delay circuit portion for delaying an input image signal by a predetermined amount to obtain desired pixel data, and a data rearranging device portion for selecting a median value from a plurality of input signals. Can be divided into The signal delay circuit portion includes six D-type FF circuits 71, 72, 74, 75, 77, and 78 for delaying the signal by one pixel, and delaying the signal by one line (more precisely, one line and two pixels). 3 lines × 3
Data for nine pixels in a column is output in parallel.

The data rearranging unit is constructed similarly to the 9-input data rearranging unit shown in FIG.
However, in the data rearrangement circuit, the uppermost 1 in the seventh stage
, The upper and lower two in the eighth row, the upper two in the ninth row, and the lower one, a total of six are omitted because they are not involved in the selection of the median (the fifth data value in the order of magnitude). Have been. Therefore, the number of data rearrangement circuits is 30. In this embodiment, a latch circuit as shown in FIG. 3 may be added. When an order statistical filter is configured, a multiplying circuit and an adder for multiplying each of the weighting coefficients may be added after the data rearranging device.

Although the embodiments have been disclosed above, the following modifications are also conceivable. Although an example in which parallel data is input has been disclosed as an embodiment, for example, each input data may be input serially, and a comparison circuit in a data rearranging circuit may compare one bit at a time from the upper bit. In this case, processing time is required, but the amount of hardware is smaller than in the case of parallel processing. As an application example, an example of a median filter that outputs a median value of image data has been disclosed. However, with a configuration similar to the embodiment shown in FIG. 6, data of an arbitrary order including a maximum value and a minimum value is output. It is possible. Further, by using a delay circuit corresponding to a window to be extracted, it is possible to perform a filtering process corresponding to an arbitrary type of signal relating to communication and information recording.

[0021]

As described above, in the present invention,
By combining a plurality of two-input data rearranging circuits having the same configuration, a data selector control signal which conventionally required a sudden increase in the circuit scale with an increase in the number of input data and a separate design according to the number of inputs was required. There is an effect that a generation circuit is not required, a data rearrangement device having an arbitrary number of input data can be easily realized, and the amount of hardware can be reduced. There is also an effect that a nonlinear filter device such as a median filter or an order statistical filter can be easily realized by using the data rearrangement device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data rearranging apparatus according to the present invention.

FIG. 2 is a block diagram showing another embodiment of the data rearranging circuit.

FIG. 3 is a block diagram showing a second embodiment of the data sorting apparatus.

FIG. 4 is a block diagram showing a third embodiment of the data sorting apparatus.

FIG. 5 is a block diagram showing a fourth embodiment of the data sorting apparatus.

FIG. 6 is a block diagram showing a configuration of a filter device using the data sorting device of the present invention.

FIG. 7 is a block diagram showing a circuit configuration of a conventional data rearranging device.

[Explanation of symbols]

10, 11, 12, 30, 40 to 42, 50 to 55, 6
0, 70: data rearranging circuit, 20: comparing circuit, 2
1, 22, 32, 33 ... data selector, 23 ... inverter, 43 to 48, 71, 72, 74, 75, 77, 7
8 ... D-type flip-flop, 73, 76 ... 1 line delay circuit

Claims (3)

[Claims] 1. Data rearrangement in which two data are input, the magnitudes of data values are compared, the larger data is output to one output terminal, and the smaller data is output to the other output terminal. A plurality of circuits are provided, and in two adjacent data rearranging circuits, one output terminal for outputting the larger data of one data rearranging circuit and the smaller data of the other data rearranging circuit are output. A data rearranging circuit connected in cascade in a plurality of stages such that the other output terminal to be connected is connected to the input terminal of one data rearranging circuit in the next stage. 2. When the number of data n is an even number, n / 2 data rearranging circuits are used for even-numbered stages and n / 2-1 data rearranging circuits are used for odd-numbered stages. If the number of data n is odd, the (n−
2. The data rearranging apparatus according to claim 1, wherein 1) / 2 data rearranging circuits are used, and said rearranging circuits are cascaded by n stages. 3. Data rearrangement in which two data are input, the data values are compared in size, the larger data is output to one output terminal, and the smaller data is output to the other output terminal. A plurality of circuits are provided, and in two adjacent data rearranging circuits, one output terminal for outputting the larger data of one data rearranging circuit and the smaller data of the other data rearranging circuit are output. The data rearranging circuits are cascaded in a plurality of stages such that the other output terminal to be connected is connected to the input terminal of one data rearranging circuit in the next stage, and the size of the plurality of input data is predetermined. And a signal delaying means for inputting a predetermined input data sequence to each input terminal of the data sorting means. The other apparatus.