JPH11112338A - Frequency control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency control system simple in circuit configuration, high in pull-in speed and capable of flexibly dealing with the input/output signals of different frequency ratios. SOLUTION: A buffer 12 stores data Di inputted from outside and outputs data by synchronizing a frequency with that of the output of VCO 16b under the control of CPU 13. CPU 13 checks the remaining amount of data in the buffer 12 at timing when a timing signal SYNC which is inputted synchronously with data Di and becomes the reference of synchronism is inputted from outside, and it controls the output frequency of VCO 16 so that a difference between the remaining amount of data and a target value at the time of checking can be absorbed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency control system for generating a frequency output synchronized with a timing signal input from the outside.

[0002]

2. Description of the Related Art Conventionally, a PLL (Phase Lock Loop) circuit has been known as a method for generating a frequency output signal synchronized with an input signal. A general PLL circuit outputs a phase comparator that compares the phase of an input signal and an output signal (such as a reproduced clock signal), a loop filter that smoothes the output of the phase comparator, and a reproduced clock whose frequency changes according to the output. It is configured based on a VCO (voltage controlled oscillator). Further, for example, when a sampling clock of 44.1 kHz synchronized with the input signal of 1 kHz is reproduced from the input signal of 1 kHz, a frequency dividing circuit for reducing the frequency of the reproduction clock of 44.1 kHz to 1 kHz is provided with a feedback to the phase comparator. Required for the route.

[0003]

However, in the case of the conventional PLL circuit, all the elements must be configured by hardware, so that the number of elements increases, especially when the number of frequency division stages is large, and the circuit configuration is complicated. Problem. In addition, in the conventional circuit, the response at the time of pull-in depends on the time constant of the loop filter, and this time constant cannot be easily changed. There is a problem. Furthermore,
The conventional circuit has a problem that the circuit elements cannot be flexibly coped with input / output signals having different frequency ratios because the circuit elements are built assuming a specific input / output frequency ratio.

The present invention has been made in view of such problems, and has a simple circuit configuration and a high pull-in speed.
Moreover, it is an object of the present invention to provide a frequency control method capable of flexibly dealing with input / output signals having different frequency ratios.

[0005]

According to the frequency control method of the present invention, a variable frequency oscillator that changes an output frequency based on a control input and a monitoring amount that changes according to an output of the variable frequency oscillator are used as a synchronization reference. A timing signal is checked at a timing externally input, a difference between a monitoring amount at the time of the check and a predetermined target value is obtained, and an output frequency of the variable frequency oscillator is controlled so as to absorb the difference. Control means.

According to the present invention, the monitoring amount is checked by, for example, interrupting the control means at a timing when a timing signal serving as a synchronization reference is input from the outside while changing the monitoring amount by the output of the variable frequency oscillator. . Then, a difference between the monitored amount and the target value is obtained, and the oscillation frequency of the variable frequency oscillator is controlled so as to absorb the difference. Therefore, according to the present invention, the check of the monitoring amount, the calculation of the difference between the monitoring amount and the target value, and the calculation of the control amount of the variable frequency oscillator can all be realized by software, and the number of required elements is greatly reduced. can do.
Further, since the difference between the output frequency of the variable frequency oscillator and the positive / negative direction is directly obtained from the difference between the monitored amount and the target value, a quick frequency pull-in is possible to absorb the difference. Further, since the frequency ratio of the input / output signal is determined by the target value of the monitoring amount when the timing signal is input from the outside, the input / output frequency ratio can be easily changed by changing the target value.

When predetermined data is input together with an external timing signal, data storage means for temporarily storing the data is provided, and the remaining amount of data in the data storage means can be used as a monitoring amount. . That is, one preferred frequency control method of the present invention is a variable frequency oscillator that changes the output frequency based on a control input, and stores data input from the outside, and stores the data based on the output of the variable frequency oscillator. The data storage means to be output, and the remaining data amount of the data storage means are checked at a timing when a timing signal serving as a synchronization reference input in synchronization with the data is externally input, and the remaining data amount at the time of this check is checked. Control means for controlling an output frequency of the variable frequency oscillator so as to absorb a difference between the variable frequency oscillator and a target value.

According to the present invention, the remaining amount of data in the data storage means is checked as the monitoring amount at the timing when the timing signal is input, and the data amount is changed based on the difference between the remaining amount of data and the target value (target remaining amount). Since the output frequency of the frequency oscillator is controlled, no matter what type of data is input during one cycle of the timing signal (for example, in a burst), if the output sampling rate is predetermined, By determining the target remaining amount based on the cycle of the timing signal, data output at a constant output sampling rate synchronized with the timing signal can be easily obtained.

In this case, the control means performs control such that the write pointer is advanced by one each time data is stored in the data storage means, and the read pointer is advanced by one each time data is output from the data storage means. Thus, the remaining data amount is obtained from the difference between the write pointer and the read pointer.

As the monitored amount, a count value of a counting means for counting the output of the variable frequency oscillator can be used. In this case, a frequency output synchronized with the timing signal can be obtained regardless of the presence or absence of data input together with the timing signal.

In consideration of the operation by software, the control means preferably controls the variable frequency oscillator based on a pulse width control signal having a pulse width corresponding to a difference between the monitored amount and the target value. Further, the control means may change the output frequency of the variable frequency oscillator linearly based on the difference between the monitored amount and the target value, or may change the output frequency nonlinearly. In this case, when the amount of deviation from the target value exceeds a certain range, the maximum control amount is given to the variable frequency oscillator, so that the response speed at the time of pull-in can be further improved.

Further, in the present invention, all processing can be executed by software. In this case, the frequency control program recorded on the medium according to the present invention includes an output frequency variable process for changing the frequency of the output sampling signal based on the control amount, and a monitoring amount changed by the output sampling signal as a synchronization reference. Is checked at the timing when the timing signal is input from the outside, the difference between the monitored amount at this check and a predetermined target value is obtained, and the output frequency of the output sampling signal is controlled so as to absorb the difference. Output frequency control processing.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a system to which a frequency control circuit according to one embodiment of the present invention is applied. The computer 1 that gives a timing serving as a reference for synchronization and the synchronization target device 2 that synchronizes with the output from the computer 1 are, for example, a USB.
(Universal Serial Bus) or the like. The synchronization target device 2 may be, for example, a simple audio device that receives music data output from the computer 1 and generates and outputs a musical sound. The frequency control circuit according to the present invention is built in the synchronization target device 2.

FIG. 2 is a block diagram showing a configuration of the frequency control circuit. This circuit comprises a FIFO (First In First Out) 11 as a data storage means and a buffer 1
2, CPU 13, ROM 14 and V
CO control unit 15 and VCO as variable frequency oscillator
(Voltage-controlled oscillator) 16.

FIG. 3 shows input data Di input to this circuit and a SYNC signal as a timing signal serving as a reference for synchronization on the data bus. In addition, US
According to the B standard, an equivalent synchronization signal is transmitted using an SOF (Start of Frame
e) It is called a signal. After the burst-like input data Di following the SYNC signal is stored in the FIFO 11,
Under the control of the CPU 13, the data is stored in the buffer 12 and output as output data Do at a predetermined timing. CPU
Reference numeral 13 is operated by a microprogram stored in the ROM 14 to execute read / write control of the buffer 12 at regular intervals, and the remaining amount of data in the buffer 12 every time the SYNC signal is interrupted from the outside in the cycle T. the check as monitored amount, and outputs an up pulse P _U or down pulse P _D of PWM (pulse width modulation) to the VCO control unit 15 based on the difference between the remaining data amount and the target remaining. VCO control unit 15 controls the oscillation frequency of the VCO16 based on up-pulse P _U or down pulse P _D. The output of the VCO 16 is output as an output sampling signal Fs synchronized with the output data Do to the next stage circuit, for example, a D / A converter for D / A converting the output data Do, and the data from the buffer 13 is output. It is supplied to the CPU 13 to give a read timing.

The CPU 13 holds a read pointer RP and a write pointer WP of the buffer 12 and an output request flag ORQ set by an output from the VCO 16 in a group of internal registers. Although not shown, F
The data remaining amount of the IFO 11 is also held inside the CPU 13.

FIG. 3 also shows the remaining data state of the FIFO 11 and the buffer 12 and the output states of the output data Do and the up / down pulses P _U and P _D in accordance with the input timing of the data and the SYNC signal. The number of data to be output during the period T of the SYNC signal is determined by the output sampling rate Fs. For example, the period T is 1
If the output sampling rate is 44.1 kHz in ms, 44 bits of data are output at regular intervals during the period T. Here, it is assumed that a group of input data Di following the SYNC signal is, for example, data of 44 bits. However, the data amount of the input data Di may be any amount as long as it is within a range allowed by the capacity of the buffer 12, and may be a variable length code.

Each SYNC signal becomes an interrupt signal to the CPU 13. The CPU 13 uses the interrupt signal to check the remaining amount of data in the buffer 12, determine the output frequency of the VCO 16 based on the remaining amount of data, and take in the remaining amount of data in the FIFO 11. Execute the process.

FIG. 4 shows a state in which C is generated by interruption of the SYNC signal.
It is a flowchart which shows the above-mentioned procedure which PU13 performs. When the SYNC signal interrupt occurs, the CPU 1
3 first checks whether or not data exists in the FIFO 11 (S1). If no data exists, the process is terminated as it is.
The number of data in the FO11 is stored (S2). Next, a difference ΔR between the data remaining amount R of the buffer 12 and the target value R ₀ is calculated (S3). Data remaining amount R of buffer 12 and difference ΔR
Is determined as follows.

[0020]

## EQU1 ## Remaining data amount (R) = write pointer (WP)-
Read Pointer (RP) Difference (ΔR) = Remaining Data (R) −Target Value (R ₀ )

If the difference ΔR is 0, the process is terminated (S4). If the difference ΔR is not 0, pulses P _U and P _D having appropriate pulse widths corresponding to ΔR are generated, and the PWM pulse is output to the VCO. Output to the control unit 15 (S5). That is, the difference Δ
When R is a positive value (when the data remaining amount as time t ₄ in FIG. 3 is large), it is determined that the output rate of the data is slow to generate up pulse P _U, the difference ΔR is negative (when the data level is low as the time t ₆ in FIG. 3) when the value produces a down pulse P _D output speed of the data is determined to fast. The pulse width of the pulses P _U and P _D is, for example, a value proportional to the absolute value of the difference ΔR. Note that the remaining data amount R and the target value R ₀ are not limited to the number of bits, but may be any values as long as they are values proportional to the number of data bytes. For example, in the case of 16-bit stereo audio data, 1
Since the sample is 4 bytes, in the case of 44.1 kHz, the target value R ₀ of the remaining data amount in the 1 ms period is:
This is equivalent to 176 bytes.

FIG. 5 is a flowchart showing a process repeated by the CPU 13 during a period T between the input of the SYNC signal and the input of the SYNC signal. This process is repeatedly executed in a cycle shorter than T / N, where N is the amount of input data input during the cycle T. First, it is determined whether or not the output request flag ORQ is active, that is, whether or not the output of the VCO 16 has just been input (S11).
When the RQ is active, the CPU outputs one bit of the data Do, advances the read pointer RP by one, reduces the remaining data amount R = WP-RP by one, and resets the ORQ (S12). This processing is not performed when ORQ is inactive. Next, it is confirmed whether the remaining amount of data in the FIFO 11 is 0 (S13). If the remaining amount of data in the FIFO 11 is not 0, the data Di is written to the buffer 12, the write pointer WP is advanced by one, and 1 is added to the remaining amount of data R = WP-RP to reduce the remaining amount of the FIFO 11 by one ( S14). FIFO11 data remaining amount is 0
In this case, this process is not performed (S13).

When such processing is performed, as shown in FIG. 3, at time t ₁ , the data Di ₁ input following the SYNC signal is started to be stored in the FIFO 11, and the data Di ₁ is all stored in the FIFO 11. And the data amount stored in the FIFO 11 at the input time t ₂ of the next SYNC signal is C
The data is taken into the PU 13 and is transferred from the FIFO 11 to the buffer 12.
The storage of the input data Di _{1 into} the storage device is started. As a result, the write pointer WP of the buffer 12 is sequentially advanced. At the same time, the next data Di ₂ is stored in the FIFO 11. When the data amount of the FIFO 11 taken into the CPU 13 becomes 0, the buffer 1 is transferred from the FIFO 11
2 is stopped, and at the next SYNC signal input timing t ₃ , the remaining data amount R _{1 of the} buffer 12 is obtained from the difference between the write pointer WP and the read pointer RP of the buffer 12, and the remaining amount R ₁ Determines the output sampling rate. Further, the CPU 13 controls the VCO 16 via the VCO control unit 15 based on the difference ΔR between the remaining amount R ₁ and the target value R ₀ .

Output sampling signal F from VCO 16
Since s sets the output request flag ORQ in the CPU 13, the CPU 13 outputs one data from the buffer 12 and advances the read pointer RP by one. With the above processing, as indicated by the hatched lines in FIG.
Control is performed such that a fixed amount of data always remains in the buffer 12 at the time of input of the YNC signal, whereby the output data Do is frequency-synchronized with the SYNC signal.

The data output may be performed by an interrupt to the CPU 13 instead of the output request flag ORQ as in this example. In this case, as shown in FIG. 6, the CPU 13 outputs data Do by interruption of the output sampling signal Fs,
A process is performed in which P is incremented by one and the remaining data amount R is decremented by one (S21). In this case, the processes repeatedly executed between the SYNC signal and the SYNC signal are only steps S13 and S14 in FIG.

The pulse width of the up pulse P _U and a down pulse P _D is generated by the CPU13, for example 7
As shown in (a), in addition to changing linearly in accordance with the difference ΔR, as shown in FIG. (B), when ΔR exceeds a certain range, it may change non-linearly so as to reach a maximum value. good. In this case, there is an advantage that the retraction time is further reduced. The right side (positive direction side) in the figure shows the up pulse P
_U, left (negative direction side) shows the output range of the down pulse P _D, respectively. When a table or the like is provided in the ROM 14, only the relation table of the first quadrant shown in FIGS. 7A and 7B is created, and | ΔR | is obtained, and up / down is switched according to the sign thereof. This will reduce the capacity of the table by half.

As shown in FIGS. 8A and 8B, for example, a pulse whose duty ratio changes from 0 to 100% while the difference ΔR changes from the minimum value to the maximum value is V
When used as a control signal for the CO 16, the VCO 16 can be controlled by one type of control signal without using two types of pulses as described above.
The number of ports of U13 can be reduced.

FIG. 9 is a block diagram showing another embodiment of the present invention. This circuit is provided with F as a data storage means.
IFO 21, counter 22 as control means, CPU
23, a ROM 24, a VCO control unit 25, and a VCO 26 as a variable frequency oscillator.

In this circuit, the count value of the counter 22 is used as a monitoring amount. That is, the input data Di is stored in the FIFO 21 and is output from the FIFO 21 in synchronization with the output sampling signal Fs of the VCO 26. The output sampling signal Fs is also supplied as a clock of the counter 22. The CPU 23 captures the count value of the counter 22 in the interrupt processing by the SYNC signal input at a constant period, and when the count value is smaller than the target value, outputs the control signal PWM for increasing the output frequency of the VCO 26. If the count value is larger than the target value, the control signal PWM for lowering the output frequency of the VCO 26 is output. As a result, the output sampling signal Fs from the VCO 26 becomes S
Synchronizing with the YNC signal, the frequency converges to a value determined by the target count value.

FIG. 10 is a block diagram showing still another embodiment of the present invention, and the same parts as those in FIG. 9 are denoted by the same reference numerals. This circuit receives no data from outside,
An example is shown in which only a SYNC signal is given as a timing signal. In this example, the count value is used as a monitoring amount using a counter 31 inside the CPU 23. The control method of the output frequency of the VCO 26 is the same as in the example of FIG. This embodiment is effective for the purpose of reading data stored in the synchronization target device 2 under the timing control of the computer 1.

In the present invention, all processes can be realized by software. In this case, the frequency control program may include an output frequency variable process and an output frequency control process. The output frequency variable processing is based on the output sampling signal F based on the control amount.
Oscillation processing that changes the frequency of s is realized by timer processing. In the output frequency control process, the monitoring amount that changes according to the output sampling signal Fs is checked at the timing when the timing signal SYNC serving as a synchronization reference is input from the outside, and the monitoring amount at this check and a predetermined target value are compared. Is obtained, and the output frequency of the output sampling signal Fs is controlled so as to absorb the difference. Such programs are FD, CD
-Provided by being recorded on a recording medium such as a ROM, or provided via an appropriate communication medium.

In the embodiment described above, the circuit shown in FIG.
Although the stage configuration is used, this is to cope with large frequency fluctuations, and when the output frequency is higher than the reference value, data in the buffer may be lost. Is to avoid as much as possible. Since the reference output frequency corresponds to the number of input data, the output frequency setting process particularly when data is transmitted for the first time tends to involve relatively large fluctuations in the output frequency. According to the circuit described above, a sufficient margin can be provided. If there is little possibility that such a problem will occur, it goes without saying that the buffer 12 may be omitted and the remaining amount of data in the FIFO 11 may be used as the monitoring amount.

[0033]

As described above, according to the present invention,
While changing the monitoring amount by the output of the variable frequency oscillator, the monitoring amount is checked at the timing when the timing signal serving as the synchronization reference is input from the outside, and the difference between the monitoring amount and the target value is calculated and absorbed. The oscillation frequency of the variable frequency oscillator is controlled so that
The check of the monitoring amount, the calculation of the difference between the monitoring amount and the target value, and the calculation of the control amount of the variable frequency oscillator can all be realized by software, and the required number of elements can be greatly reduced. Further, since the deviation amount of the output frequency of the variable frequency oscillator is directly obtained in the positive and negative directions based on the difference between the monitored amount and the target value, quick synchronization can be established to absorb the deviation amount. Further, since the frequency ratio of the input / output signal is determined by the target value of the monitoring amount when the timing signal is input from the outside, the input / output frequency ratio can be easily changed by changing the target value. To play.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a system to which a frequency control circuit according to an embodiment of the present invention is applied.

FIG. 2 is a block diagram of a frequency control circuit of an embodiment used in the system.

FIG. 3 is a timing chart showing input data to the circuit and a state of each unit.

FIG. 4 is a flowchart showing a process performed by the circuit when a SYNC signal is interrupted.

FIG. 5 is a flowchart showing a steady process of the circuit.

6 is a flowchart illustrating an example in which a part of the processing in FIG. 5 is set as an interrupt processing;

FIG. 7 is a graph showing a relationship between a difference ΔR and a pulse width of a control pulse in the circuit.

FIG. 8 is a graph showing a relationship between a difference ΔR and a control pulse in another example of the circuit.

FIG. 9 is a block diagram of a frequency control circuit according to another embodiment of the present invention.

FIG. 10 is a block diagram of a frequency control circuit according to still another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Computer, 2 ... Synchronization target equipment, 3 ... Signal cable, 11,21 ... FIFO, 12 ... Buffer, 13,2
3 CPU, 14, 24 ROM, 15, 25 VCO
Control unit, 16, 26 VCO, 22, 31 counter.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor: Hitoshi Furuseki, 10-1, Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha Corporation (72) Inventor, Sadayuki Narusawa 10-1, Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha Corporation ( 72) Inventor Shuichi Ezaki 10-1 Nakazawa-cho, Hamamatsu City, Shizuoka Prefecture Yamaha Corporation

Claims (7)

[Claims] 1. A variable frequency oscillator that changes an output frequency based on a control input, and a monitoring amount that changes by an output of the variable frequency oscillator is checked at a timing when a timing signal serving as a synchronization reference is input from the outside. And a control means for obtaining a difference between the monitoring amount at the time of the check and a predetermined target value, and controlling an output frequency of the variable frequency oscillator so as to absorb the difference. method. 2. A variable frequency oscillator that changes an output frequency based on a control input; a data storage unit that stores data input from the outside and outputs the data based on an output of the variable frequency oscillator; The remaining amount of data in the data storage means is checked as a monitoring amount at the timing when a timing signal serving as a synchronization reference input in synchronization with the external device is input, and the difference between the remaining amount of data at this check and the target value is checked. Control means for controlling the output frequency of the variable frequency oscillator so as to absorb the frequency. 3. The control means advances a write pointer by one each time data is stored in the data storage means, and advances a read pointer by one each time data is output from the data storage means. 3. The frequency control method according to claim 2, wherein the remaining data amount is obtained from a difference between a write pointer and the read pointer. 4. The apparatus according to claim 1, wherein said control means includes a count means for counting an output of said variable frequency oscillator, and checks a count value of said count means as said monitoring amount. Frequency control method. 5. The variable frequency oscillator according to claim 1, wherein the control means controls the variable frequency oscillator based on a pulse width control signal having a pulse width corresponding to a difference between the monitored amount and a target value. The frequency control method according to any one of claims 1 to 4. 6. The control means according to claim 1, wherein said control means changes the output frequency of said variable frequency oscillator nonlinearly with respect to a difference between said monitored amount and a target value.
The frequency control method according to any one of claims 1 to 5. 7. An output frequency variable process for changing a frequency of an output sampling signal based on a control amount, and a monitoring amount changed by the output sampling signal.
A timing signal serving as a reference for synchronization is checked at a timing input from the outside, a difference between a monitoring amount at the time of the check and a predetermined target value is obtained, and an output of the output sampling signal is absorbed so as to absorb the difference. A medium on which a frequency control program including an output frequency control process for controlling a frequency is recorded.