JPH11103055A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device capable of improving driving capability without deteriorating element characteristics and a method of manufacturing the same. A gate oxide film and a gate electrode are formed on a silicon substrate, and a source region and a drain region are formed by B ion implantation. Gate electrode 6
A first spacer 7a of SiO ₂ film is formed on both sides of, to form a second spacer 7b of SiN film on the side surface of the first spacer 7a. The high concentration diffusion layers 2a and 3a are formed by ion implantation of B, Ti is formed on the high concentration diffusion layers 2a and 3a, and the silicide film 8 is formed by heat treatment. After removing the second spacer 7b, B ions are implanted to form high concentration diffusion regions 2c and 3c on the surfaces of the source region 2 and the drain region 3 between the first spacer 7a and the silicide film 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, elements have been rapidly miniaturized in order to achieve high integration and high speed of LSI (Large Scale Integrated Circuit). In a field-effect semiconductor device such as a metal-oxide-semiconductor field-effect transistor (hereinafter, referred to as a MOSFET), a leak current increases with miniaturization of an element.
Fluctuations in element characteristics due to hot carriers increase. In order to suppress these, LDD (Lightly Doped
Drain) structure is used.

FIG. 5 shows a conventional MOSF having an LDD structure.
FIG. 2 is a schematic cross-sectional view illustrating a structure of an ET.

In FIG. 5, an n-type single crystal silicon substrate 1
The source region 2 and the drain region 3 are formed at predetermined intervals on the surface of the substrate. A region of the silicon substrate 1 between the source region 2 and the drain region 3 becomes a channel region 4. The source region 2 includes a high-concentration diffusion layer 2a formed of a p ⁺ layer and a low-concentration diffusion layer 2b formed of a p ⁻ layer on the channel region 4 side. The drain region 3 has p ⁺
High-concentration diffusion layer 3a composed of
^And a low-concentration diffusion layer 3b.

A gate electrode 6 made of polysilicon (polycrystalline silicon) is formed on channel region 4 via a gate oxide film 5 made of silicon oxide. Spacers 7 each made of a silicon oxide film are formed on both side surfaces of the gate electrode 6.

A silicide film 8 is formed on high concentration diffusion layers 2a and 3a. A source electrode and a drain electrode (not shown) are formed on the silicide film 8 on the high concentration diffusion layers 2a and 3a, respectively.

In the MOSFET shown in FIG. 5, when a drain voltage is applied between the drain region 3 and the source region 2, the low-concentration diffusion layer 3b having a relatively high resistance value generates near the end of the drain region 3. A rapid increase in the electric field is suppressed. As a result, a higher breakdown voltage of the MOSFET and suppression of hot carriers are realized.

The resistance between the source electrode and the high concentration diffusion layer 2a and the resistance between the drain electrode and the high concentration diffusion layer 3a are formed by the silicide film 8 formed on the high concentration diffusion layers 2a and 3a. The value is reduced. As a result, a large amount of current can flow between the source and the drain.
The driving capability of the OSFET is improved.

As a method of forming the silicide film 8 on the high concentration diffusion layers 2a and 3a, a self-aligned silicide method using Ti has been proposed. In the silicide process using Ti, a two-step RTA method (Ra
pid Thermal Anneal).

In this two-step RTA method, the high concentration diffusion layer 2
After forming a Ti film on a and 3a by sputtering, 6
A heat treatment (first RTA) is performed in a temperature range of 00 ° C. to 750 ° C. to cause a solid-phase reaction of the Ti film with the underlying silicon to form a TiSi
Form ₂ . In this case, TiSi ₂ forms a high-resistance C49 structure that is relatively stable at low temperatures, and has a sheet resistance of 2
It is about 0 to 30 Ω / □.

Then, after the unreacted Ti is selectively etched, heat treatment (second RTA) is performed again in a temperature range of 750 ° C. to 850 ° C. to remove TiSi ₂ from the C49 structure to C
Phase transition to 54 structure. The C54 structure is relatively stable at high temperatures and has a sheet resistance of 2 to 5 Ω / □, which is lower than that of the C49 structure. Thus, the low-resistance silicide film 8 is formed.
Is formed.

[0012]

However, in a P-channel type MOSFET, when the above-mentioned two-step RTA method is used for forming the silicide film 8 made of TiSi ₂ ,
By heat treatment, B (boron), which is an impurity in the high concentration diffusion layers 2a and 3a formed of p ⁺ layers, diffuses into Ti or TiSi ₂ of the silicide film 8, and the concentration of B on the surfaces of the high concentration diffusion layers 2a and 3a decreases. descend. Therefore, the silicide film 8 and the high-concentration diffusion layers 2a and 3a come into Schottky contact, and
As shown in FIG. 5, the silicide film 8 and the high concentration diffusion layers 2a, 3
The contact resistance R with a increases, thereby increasing the external resistance of the MOSFET. As a result, the P-channel type MOSF
The driving ability of the ET decreases.

The silicide film 8 and the high concentration diffusion layers 2a, 3a
FIG. 7
As shown in (1), it has been proposed to perform additional ion implantation of B after the formation of the silicide film 8. In this case, B
It is necessary to set the ion range (Rp) of the ion implantation near the interface between the silicide film 8 and the high concentration diffusion layers 2a and 3a.

However, when the ion range (Rp) is set near the interface between the silicide film 8 and the high concentration diffusion layers 2a, 3a, the diffusion layer depth (Xj) of the high concentration diffusion layers 2a, 3a becomes larger. P-channel type MOSFE
The punch-through characteristics and element isolation characteristics of T deteriorate.

An object of the present invention is to provide a semiconductor device capable of improving the driving capability without deteriorating the element characteristics and a method for manufacturing the same.

[0016]

Means for Solving the Problems and Effects of the Invention

(1) First invention In a semiconductor device according to a first invention, an impurity region of one conductivity type is formed in a semiconductor substrate or a semiconductor layer, and a low-resistance film for reducing resistance is formed on the impurity region. And the one-conductivity-type high-concentration impurity region is formed so as to be in contact with the end surface of the low-resistance film.

In the semiconductor device according to the present invention, the resistance of the surface of the impurity region is reduced by the low resistance film formed on the impurity region. In particular, since the high-concentration impurity region is formed so as to be in contact with the end face of the low-resistance film, when impurities in the impurity region are reduced by heat treatment during the formation of the low-resistance film, the impurity under the low-resistance film is reduced. The resistance value of the current path in the direction parallel to the surface of the semiconductor substrate or the semiconductor layer can be reduced without additionally implanting impurities into the impurity region. Therefore, a semiconductor device capable of improving driving capability without deteriorating element characteristics is realized.

(2) Second Invention In a semiconductor device according to a second invention, an impurity region of one conductivity type is formed in a semiconductor substrate or a semiconductor layer, and an alloy film made of an alloy of a semiconductor and a metal is formed on the impurity region. The one conductivity type high-concentration impurity region is formed so as to be in contact with the end face of the alloy film.

In the semiconductor device according to the present invention, the resistance of the surface of the impurity region is reduced by the alloy film formed on the impurity region. In particular, since the high-concentration impurity region is formed so as to be in contact with the end surface of the low-resistance film, when the impurity in the impurity region is reduced by heat treatment during the formation of the alloy film, the impurity region is formed in the impurity region below the alloy film. Without additional implantation, the resistance value of the current path in the direction parallel to the surface of the semiconductor substrate or the semiconductor layer can be reduced. Therefore, a semiconductor device capable of improving driving capability without deteriorating element characteristics is realized.

(3) Third Invention In a semiconductor device according to a third invention, an impurity region of one conductivity type is formed in a silicon substrate or a silicon layer, a silicide film is formed on the impurity region, and an end face of the silicide film is formed. The one-conductivity-type high-concentration impurity region is formed so as to be in contact with.

In the semiconductor device according to the present invention, the resistance of the surface of the impurity region is reduced by the silicide film formed on the impurity region. In particular, since the high-concentration impurity region is formed so as to be in contact with the end face of the silicide film,
When the impurity in the impurity region is reduced by the heat treatment during the formation of the silicide film, the resistance of the current path in the direction parallel to the surface of the semiconductor substrate or the semiconductor layer is increased without additionally implanting the impurity into the impurity region below the silicide film. The value can be reduced. Therefore, a semiconductor device capable of improving driving capability without deteriorating element characteristics is realized.

(4) Fourth Invention A semiconductor device according to a fourth invention is characterized in that first and second impurity regions of one conductivity type formed on a semiconductor substrate or a semiconductor layer at predetermined intervals, and A gate insulating film formed on a channel region between the first and second impurity regions, a gate electrode formed on the gate insulating film, and a low-resistance gate formed on the first and second impurity regions. The first and second low-resistance films, and the one-conductivity-type high-concentration impurity region provided between the end surfaces of the first and second low-resistance films and the channel region. It is.

In the semiconductor device according to the present invention, the first
The resistance of the surface of the first and second impurity regions is reduced by the first and second low-resistance films formed on the second and the second impurity regions, respectively. In particular, since the first and second high-concentration impurity regions are formed so as to be in contact with the end surfaces of the first and second low-resistance films, heat treatment during the formation of the first and second low-resistance films is performed. When the impurities in the first and second impurity regions are reduced by the
It is possible to reduce the resistance value of the current path in a direction parallel to the surface of the semiconductor substrate or the semiconductor layer without additionally implanting impurities into the first and second impurity regions below the low-resistance film. Therefore, a semiconductor device capable of improving driving capability without deteriorating element characteristics is realized.

(5) Fifth invention A semiconductor device according to a fifth invention is the semiconductor device according to the fourth invention, wherein the first and second low-resistance films are made of a semiconductor-metal alloy film. It becomes.

In this case, the surface resistance of the first and second impurity regions is reduced by the alloy film formed on the first and second impurity regions. In particular, since the first and second high-concentration impurity regions are formed so as to be in contact with the end surfaces of the alloy film, heat treatment during the formation of the alloy film reduces impurities in the first and second impurity regions. In addition, the resistance value of the current path in the direction parallel to the surface of the semiconductor substrate or the semiconductor layer can be reduced without additionally implanting impurities into the first and second impurity regions below the alloy film. Therefore, a semiconductor device capable of improving driving capability without deteriorating element characteristics is realized.

(6) Sixth invention A semiconductor device according to a sixth invention is the semiconductor device according to the fourth or fifth invention, wherein the semiconductor substrate or the semiconductor layer contains silicon, and the first and second semiconductor devices have the same structure. Is made of a silicide film.

In this case, the surface resistance of the first and second impurity regions is reduced by the silicide film formed on the first and second impurity regions. In particular, since the first and second high-concentration impurity regions are formed so as to be in contact with the end surfaces of the silicide film, the heat treatment at the time of forming the silicide film reduces the impurities in the first and second impurity regions. In addition, the current path in the direction parallel to the surface of the semiconductor substrate or the semiconductor layer can be reduced without additionally implanting impurities into the first and second impurity regions below the silicide film. Therefore, a semiconductor device capable of improving driving capability without deteriorating element characteristics is realized.

(7) Seventh Invention The semiconductor device according to the seventh invention is a semiconductor device according to the fourth, fifth or sixth aspect.
In the structure of the semiconductor device according to the present invention, the first and second conductive type first and second regions, which extend from the first and second impurity regions to the channel region side and have lower concentrations than the first and second impurity regions, respectively. The semiconductor device further includes a second low-concentration impurity region, and the first and second high-concentration impurity regions are formed in the first and second low-concentration impurity regions so as to be in contact with end faces of the first and second low-resistance films. Are provided respectively.

In this case, a semiconductor device having an LDD structure capable of improving the driving capability without deteriorating the element characteristics is realized.

(8) Eighth Invention A semiconductor device according to an eighth invention is characterized in that, in the configuration of the semiconductor device according to any one of the first to seventh inventions, the semiconductor device is the one conductivity type p-type. I do.

In this case, a P-channel type semiconductor device capable of improving the driving capability without deteriorating the element characteristics is realized.

(9) Ninth Invention In a method of manufacturing a semiconductor device according to a ninth invention, there is provided a step of forming an impurity region of one conductivity type in a semiconductor substrate or a semiconductor layer, and forming a low-resistance film on the impurity region. And forming a one-conductivity-type high-concentration impurity region in contact with the end surface of the low-resistance film.

According to the semiconductor device of the present invention, the resistance at the surface of the impurity region is reduced by the low resistance film formed on the impurity region. In particular, since the high-concentration impurity region is formed so as to be in contact with the end surface of the low-resistance film, if the impurity in the impurity region is reduced by the heat treatment during the formation of the low-resistance film, the impurity under the low-resistance film is reduced. It is possible to reduce the resistance value of the current path in a direction parallel to the surface of the semiconductor substrate or the semiconductor layer without additionally implanting impurities into the region. Therefore, a semiconductor device capable of improving driving capability without deteriorating element characteristics can be obtained.

(10) Tenth Invention In a method for manufacturing a semiconductor device according to a tenth invention, in the method for manufacturing a semiconductor device according to the ninth invention, the step of forming the low-resistance film is performed on the impurity region. The method includes a step of forming a metal film and a step of forming an alloy film by reacting the metal film with an impurity region by heat treatment.

In this case, the resistance of the surface of the impurity region is reduced by the alloy film formed on the impurity region. Especially,
Since the high-concentration impurity region is formed so as to be in contact with the end face of the alloy film, when the impurity in the impurity region is reduced by the heat treatment during the formation of the alloy film, the impurity is additionally implanted into the impurity region below the alloy film. In addition, the resistance value of the current path in the direction parallel to the surface of the semiconductor substrate or the semiconductor layer can be reduced. Therefore, a semiconductor device capable of improving driving capability without deteriorating element characteristics can be obtained.

(11) Eleventh Invention A method of manufacturing a semiconductor device according to an eleventh invention is directed to the method of manufacturing a semiconductor device according to the ninth invention, wherein the semiconductor substrate or the semiconductor layer contains silicon and the low-resistance film is formed. Forming a metal film on the impurity region and reacting the metal film with silicon in the impurity region by heat treatment to form a silicide film.

In this case, the resistance of the surface of the impurity region is reduced by the silicide film formed on the impurity region.
In particular, since the high-concentration impurity region is formed so as to be in contact with the end surface of the silicide film, when the impurity in the impurity region is reduced by the heat treatment during the formation of the silicide film, the impurity is additionally implanted into the impurity region below the silicide film. Without this, the resistance value of the current path in the direction parallel to the surface of the semiconductor substrate or the semiconductor layer can be reduced. Therefore, a semiconductor device capable of improving driving capability without deteriorating element characteristics is realized.

(12) Twelfth Invention In a method of manufacturing a semiconductor device according to a twelfth invention, a step of forming a gate insulating film on a predetermined channel region of a semiconductor substrate or a semiconductor layer, and a step of forming a gate on the gate insulating film Forming an electrode, forming a mask film on both sides of the gate insulating film and the gate electrode, and ion-implanting the first and second conductive types into the semiconductor substrate or the semiconductor layer on both sides of the gate insulating film and the gate electrode. Forming a second impurity region, forming first and second low-resistance films on the first and second impurity regions, removing the mask film; Forming the first and second high-concentration impurity regions of the one conductivity type between the end face of the second low-resistance film and the channel region by ion implantation, respectively. It is.

According to the semiconductor device of the present invention, the resistance of the surface of the first and second impurity regions is reduced by the first and second resistance reducing films formed on the first and second impurity regions. Reduced. In particular, since the first and second high-concentration impurity regions are formed so as to be in contact with the end faces of the first and second low-resistance films, heat treatment during the formation of the first and second low-resistance films is performed. When the amount of impurities in the first and second impurity regions decreases, the semiconductor substrate or the semiconductor substrate is not added to the first and second impurity regions under the first and second low-resistance films without additionally implanting impurities. It is possible to reduce the resistance of the current path in the direction parallel to the surface of the layer. Therefore, a semiconductor device capable of improving driving capability without deteriorating element characteristics can be obtained.

(13) Thirteenth Invention A method of manufacturing a semiconductor device according to a thirteenth invention is directed to the method of manufacturing a semiconductor device according to the twelfth invention, in which the semiconductor substrate or the semiconductor layer is subjected to ion implantation before forming the mask film. Forming the first and second low-concentration impurity regions of the one conductivity type by implantation; forming the mask film in the step of forming the first mask film on both side surfaces of the gate insulating film and the gate electrode; And a second step on the side surface of the first mask film.
Forming the first and second high-concentration impurity regions, wherein the step of forming the first and second high-concentration impurity regions includes the step of removing the second mask film and the end faces of the first and second resistance-reducing films. Forming the first and second high-concentration impurity regions by ion implantation so as to make contact with the second mask film, and removing the second mask film.

In this case, a semiconductor device having an LDD structure capable of improving the driving capability without deteriorating the element characteristics is obtained.

[0042]

FIG. 1 is a schematic sectional view showing the structure of a P-channel MOSFET according to an embodiment of the present invention.

In FIG. 1, an n-type single crystal silicon substrate 1
A source region 2 and a drain region 3 are formed at a predetermined interval on the surface. A region of the silicon substrate 1 between the source region 2 and the drain region 3 becomes a channel region 4. The source region 2 includes a high-concentration diffusion layer 2a formed of a p ⁺ layer and a low-concentration diffusion layer 2b formed of a p ⁻ layer on the channel region 4 side. The drain region 3 has p
^A high-concentration diffusion layer 3a composed of a ⁺ layer and a low-concentration diffusion layer 3b composed of ap ⁻ layer on the channel region 4 side.
B (boron) is used as the n-type impurity.

A gate electrode 6 made of polysilicon (polycrystalline silicon) is formed on channel region 4 via a gate oxide film 5 made of silicon oxide. First spacers 7a made of silicon oxide are formed on both side surfaces of the gate electrode 6, respectively. This first spacer 7
The width w1 of a is smaller than the width w2 of the low concentration diffusion layers 2b and 3b. For example, the width w1 of the first spacer 7a is 50 to 100.
nm, and the width w2 of the low concentration diffusion layers 2b and 3b is 100
２００200 nm.

On the high concentration diffusion layers 2a and 3a, TiSi
₂ are formed, respectively.
On the surfaces of the source region 2 and the drain region 3 between the first spacer 7a and the silicide film 8, high-concentration diffusion regions 2c and 3c made of p ⁺ layers are formed, respectively. A source electrode and a drain electrode (not shown) are formed on the silicide film 8 on the high concentration diffusion layers 2a and 3a, respectively.

In the MOSFET of this embodiment, high-concentration diffusion regions 2c, 3c made of p ⁺ layers are formed in the source region 2 and the drain region 3 so as to be in contact with the end surfaces of the silicide film 8 on the channel region 4 side. In the lateral direction of the silicide film 8 (the direction parallel to the surface).
Is increased, and as shown in FIG.
Contact with the high concentration diffusion layers 2a and 3a. Thereby, the resistance value of the current path between the channel region 4 and the silicide film 8 decreases, and the external resistance of the MOSFET decreases. As a result, the P-channel type MOSF
ET driving ability is improved.

FIGS. 3 and 4 show the P-channel type MO shown in FIG.
It is a process sectional view showing the manufacturing method of SFET.

Firstly, as shown in FIG. 3 (a), on the n-type single-crystalline silicon substrate 1, the film thickness made of SiO ₂ 5 to 10
A gate oxide film 5 having a thickness of 100 nm and a gate electrode 6 made of polysilicon having a thickness of 100 to 200 nm are sequentially formed. The gate length is 0.1 to 0.3 μm.

Then, B is ion-implanted into the surface of the silicon substrate 1 on both sides of the gate electrode 6 so that p is implanted.
A source region 2 and a drain region 3 are formed respectively. The dose of B is 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² . A region between the source region 2 and the drain region 3 becomes a channel region 4.

Next, as shown in FIG. 3B, an SiO ₂ film having a thickness of 50 to 100 nm is formed on the entire surface of the silicon substrate 1 and is etched to form a width on both side surfaces of the gate electrode 6. The first spacers 7a of w1 are respectively formed.

Thereafter, a 50- to 100-nm-thick SiN film is formed on the entire surface of the silicon substrate 1 and is etched to form a second spacer 7 on the side surface of the first spacer 7a.
b is formed. Thereafter, high-concentration diffusion layers 2a and 3a made of p ⁺ layers are formed in the source region 2 and the drain region 3 by ion implantation of B, respectively. The dose of B is 1 ×
10 is a ^{15 ~5} × 10 ¹⁵ cm ^-2.

In this case, the first and second spacers 7a,
7b, the source region 2 and the drain region 3 below
Low-concentration diffusion layers 2b and 3b made of p ^- layers are formed. The diffusion layer depth (Xj) of the high concentration diffusion layers 2a and 3a is about 0.1 μm, and the width W is about 0.1 μm.

Next, as shown in FIG. 3C, a Ti film is formed on the high-concentration diffusion layers 2a and 3a by a sputtering method, and heat-treated at a temperature range of 600 ° C. to 700 ° C. (first RT).
Perform A). Further, unreacted Ti is removed by etching, and heat treatment (second RTA) for phase transition is performed in a temperature range of 700 ° C to 800 ° C. As a result, silicide films 8 made of TiSi ₂ having a C54 structure are formed on the high concentration diffusion layers 2a and 3a, respectively.

Next, as shown in FIG. 4D, after removing the second spacer 7b using hot phosphoric acid, B
Is implanted at an acceleration energy of 5 to 10 keV. The dose of B is 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² . Then, RT is activated to activate the implanted impurities.
The heat treatment is performed by the method A in a temperature range of about 800 to 1000 ° C. Thereby, high-concentration diffusion regions 2c and 3c formed of p ⁺ layers are formed on the surfaces of source region 2 and drain region 3 between first spacer 7a and silicide film 8, respectively.

Thereafter, as shown in FIG. 4E, an interlayer insulating film 12 made of SiO _{2 is} formed on the entire surface of the silicon substrate 1.
And a contact hole is formed in the interlayer insulating film 12 on the source region 2 and the drain region 3, and the source electrode 1 made of Al (aluminum) is formed in the contact hole.
3 and the drain electrode 14 are formed.

According to the manufacturing method of this embodiment, after the outer second spacer 7b of the first and second spacers 7a and 7b having the two-layer structure is etched, B ions are implanted, whereby the silicide film 8 is formed. And the silicide film 8 can be in ohmic contact with the high concentration diffusion layers 2a and 3a.

As a result, the resistance of the current path between the channel region 4 and the silicide film 8 decreases, and the MOSFET
Is reduced in external resistance. As a result, the driving capability of the MOSFET is improved.

In this case, since the ion range (Rp) in the ion implantation of B may be set on the surface of the silicide film 8, the depth (Xj) of the diffusion layer does not increase. Therefore, it is possible to improve the driving capability of the MOSFET without deteriorating the punch-through and element isolation characteristics of the MOSFET.

Although B is used as the p-type impurity in the above embodiment, other impurities such as In (indium) and Ga (gallium) may be used.

In the above embodiment, the case where the present invention is applied to a P-channel type MOSFET having an LDD structure has been described.
The present invention can be similarly applied to other semiconductor devices such as an OSFET.

In the above embodiment, Ti is used as the material of the silicide film 8, but other materials may be used. For example, Sc (scandium), V (vanadium), Cr
(Chromium), Mn (manganese), Fe (iron), Co (cobalt), Ni (nickel), Cu (copper), Y (yttrium), Zr (zirconium), Nb (niobium), M
o (molybdenum), Ru (ruthenium), Rh (rhodium), Pd (palladium), Hf (hafnium), Ta
(Tantalum), W (Tungsten), Re (Rhenium), Os (Osmium), Ir (Iridylm), Pt
(Platinum) or the like may be used.

[Brief description of the drawings]

FIG. 1 shows a P-channel type MOS according to an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view illustrating a structure of an FET.

FIG. 2 is a diagram illustrating a current path in the MOSFET of FIG.

FIG. 3 is a process sectional view illustrating the method for manufacturing the MOSFET of FIG.

FIG. 4 is a process sectional view illustrating the method of manufacturing the MOSFET in FIG. 1;

FIG. 5 is a schematic sectional view showing the structure of a conventional P-channel MOSFET.

FIG. 6 is a diagram for explaining an increase in contact resistance in a conventional MOSFET.

FIG. 7 is a diagram for explaining an increase in the depth of a diffusion layer in a conventional MOSFET.

[Explanation of symbols]

 Reference Signs List 1 n-type single crystal silicon substrate 2 source region 2a high concentration diffusion layer 2b low concentration diffusion layer 2c high concentration diffusion region 3 drain region 3a high concentration diffusion layer 3b low concentration diffusion layer 3c high concentration diffusion region 4 channel region 5 gate oxide film Reference Signs List 6 gate electrode 7a first spacer 7b second spacer 8 silicide film

Claims (13)

[Claims] An impurity region of one conductivity type is formed in a semiconductor substrate or a semiconductor layer, a low-resistance film for reducing resistance is formed on the impurity region, and an end surface of the low-resistance film is in contact with the impurity region. Wherein the one conductivity type high-concentration impurity region is formed in the semiconductor device. 2. An impurity region of one conductivity type is formed in a semiconductor substrate or a semiconductor layer, an alloy film made of an alloy of a semiconductor and a metal is formed on the impurity region, and the impurity film is formed so as to contact an end surface of the alloy film. A semiconductor device, wherein a conductive type high-concentration impurity region is formed. 3. An impurity region of one conductivity type is formed in a silicon substrate or a silicon layer, a silicide film is formed on the impurity region, and the high-concentration impurity region of one conductivity type is in contact with an end surface of the silicide film. A semiconductor device characterized by being formed. 4. A first conductivity type and a second conductivity type formed at a predetermined interval in a semiconductor substrate or a semiconductor layer, and formed on a channel region between the first conductivity type and the second conductivity type. A gate insulating film, a gate electrode formed on the gate insulating film, and first and second resistance reducing films for reducing the resistance formed on the first and second impurity regions, respectively. And the first and second high-concentration impurity regions of the one conductivity type provided between the end surfaces of the first and second low-resistance films and the channel region, respectively. Semiconductor device. 5. The semiconductor device according to claim 4, wherein said first and second resistance reducing films are made of an alloy film of a semiconductor and a metal. 6. The semiconductor device according to claim 4, wherein the semiconductor substrate or the semiconductor layer contains silicon, and the first and second low resistance films are made of a silicide film. 7. The first and second one-conductivity-type first and second conductive regions extend from the first and second impurity regions toward the channel region, respectively, and have a lower concentration than the first and second impurity regions. And the first and second low-concentration impurity regions are arranged such that the first and second high-concentration impurity regions are in contact with end faces of the first and second low-resistance film. 7. The semiconductor device according to claim 4, wherein the semiconductor device is provided inside the semiconductor device. 8. The semiconductor device according to claim 1, wherein said one conductivity type is a p-type. 9. A step of forming an impurity region of one conductivity type in a semiconductor substrate or a semiconductor layer, a step of forming a low-resistance film on the impurity region, and a step of contacting an end surface of the low-resistance film. Forming a conductive type high concentration impurity region. 10. The step of forming the low-resistance film includes: forming a metal film on the impurity region; and reacting the metal film with the impurity region by heat treatment to form an alloy film. The method for manufacturing a semiconductor device according to claim 9, further comprising: 11. The semiconductor substrate or the semiconductor layer contains silicon, the step of forming the low-resistance film includes: forming a metal film on the impurity region; and heat-treating the metal film by heat treatment. 10. The method of manufacturing a semiconductor device according to claim 9, further comprising the step of forming a silicide film by reacting with silicon. 12. A step of forming a gate insulating film on a predetermined channel region of a semiconductor substrate or a semiconductor layer, a step of forming a gate electrode on the gate insulating film, and both sides of the gate insulating film and the gate electrode Forming a mask film on a surface; forming ion-implanted first and second impurity regions in the semiconductor substrate or semiconductor layer on both sides of the gate insulating film and the gate electrode, respectively; Forming first and second low-resistance films on the first and second impurity regions, respectively, removing the mask film, and end faces of the first and second low-resistance films. Forming the first and second high-concentration impurity regions of the one conductivity type respectively by ion implantation between the semiconductor device and the channel region. Manufacturing method of the device. 13. The method according to claim 1, further comprising, before forming the mask film, forming the first and second low-concentration impurity regions of the one conductivity type into the semiconductor substrate or the semiconductor layer by ion implantation. Forming a first mask film on both side surfaces of the gate insulating film and the gate electrode, and forming a second mask film on a side surface of the first mask film; Forming the first and second high-concentration impurity regions includes: removing the second mask film; and ion-implanting the first and second low-resistance films by ion implantation so as to contact end surfaces of the first and second low-resistance films. The method of manufacturing a semiconductor device according to claim 12, further comprising: forming a first and a second high-concentration impurity region; and removing the second mask film.