JPH11109935A - Rgb signal converting method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an RGB signal converting method and device by which adjusting operations are entirely unnecessitated and which is capable of autonomously generating and outputting a digital RGB signal having optimum phases. SOLUTION: When the number of clocks per one line of a horizontal synchronizing signal Ssy applying a horizontal synchronization to an analog RGB signal Sa is defined as N, a sampling signal Ss is generated by synchronizing the analog RGB signal Sa to the horizontal synchronizing signal Ssy and also by subjecting it to an oversampling with the frequency of (n×N) multiple ((n) is an integer) of the horizontal synchronizing frequency Ssy. Then, plural delayed sampling signals Ss1, Ss2 are generated by respectively applying plural stages of delays corresponding to plural cycles of the frequency of (n×N) multiple of the horizontal synchronizing frequency Ssy to the sampling signal Ss and sampling signals Ss, Ss1, Ss2 are synchronized to the frequency of (n×N) multiple of the horizontal synchronizing frequency Ssy to be outputted and either of the sampling signals Ss or Ss1 or Ss2 is selected corresponding to combinations among the sampling signals Ss, Ss1, Ss2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog R output from a personal computer, a workstation or the like.
The present invention relates to a method and an apparatus for converting an RGB signal into a digital RGB signal suitable for a liquid crystal display device or the like.

[0002]

2. Description of the Related Art In recent years, with the spread of personal computers, there has been an increasing demand for outputting analog RGB signals, which are video outputs, to display devices other than dedicated display devices. Generally, an analog RGB signal output from a personal computer has a signal form suitable for a scanning deflection display device having a specific scanning frequency.

[0003] Therefore, in order to view the image on a display device having different horizontal and vertical scanning frequencies, for example, a television receiver, the scanning frequency conversion device (scan converter) is interposed to convert the scanning frequency and the like, and these display devices are converted. Had been supplied to

In a display device such as a liquid crystal projector, a liquid crystal monitor, and a plasma display, which does not perform deflection scanning, an analog RGB signal cannot be directly displayed. Therefore, an input analog RGB signal is temporarily converted to a digital RGB signal by an RGB signal converter. And supplied it to the display device.

A conventional RGB signal conversion method and apparatus will be described with reference to the drawings.

FIG. 6 is a block diagram of an RGB signal converter of a first conventional example, FIG. 7 is a waveform diagram of each part, and FIG. 8 is a block diagram of an RGB signal converter of a second conventional example.

The first prior art RGB signal converter shown in FIG. 6 receives a horizontal synchronizing signal Ssy from an external personal computer (not shown) and receives the horizontal synchronizing signal Ss.
This is a technique of sampling with a sampling clock signal CLK having a frequency that is N times (N: the number of clocks) synchronized with y.

The input analog RGB signal Sa is A
In the / D converter 1, a PLL including a phase comparator 8, a loop filter 9, a VCO (voltage controlled oscillation circuit) 10, a (1 / N) frequency divider 12, a phase shifter 13, and a phase shift amount setting device 14.
(Phase Lock Loop) Frequency fc Output from Circuit 7
Is sampled by the clock signal CLK of
The digital signal is converted and output as a digital RGB signal Sd.

[0009] The PLL circuit 7 outputs a D signal of a video output device (not shown) from the horizontal synchronizing signal Ssy of the video output device (not shown).
The frequency fc of the / A converter is reproduced, the phase is finely adjusted by the phase shifter 13, and the clock signal CLK is supplied to the A / D converter 1.

A second conventional RGB signal converter shown in FIG. 8 uses a sampling clock signal C input from the outside.
This is a technique for generating a sampling clock signal CLK from a digital video signal Sd generated by A / D conversion or sampling using the LK as it is, and is an A / D converter disclosed in JP-A-7-334136. Is equivalent to

The RGB signal converter of the second conventional example uses the external clock signal CLK as it is as the sampling clock signal CLK of the A / D converter 51,
A change in video is captured from the digital RGB signal Sd output from the / D converter 51, a phase lock operation is performed in the PLL circuit 57 from the digital RGB signal Sd, and the oscillation output of the PLL circuit 57 is output to the A / D converter 51. Two kinds of operations when used as the sampling clock signal CLK can be selected by the switch 58.

[0012]

However, the conventional RGB signal converter has the following problems.

In the first prior art RGB signal converter shown in FIG. 6, an analog RGB signal Sa and a horizontal synchronizing signal Ssy are output.
7 is not strictly defined, the clock signal (FIG. 7 (b)) having the same phase as the analog RGB signal Sa (FIG. 7 (a)) as shown in FIG. 1
7D, the analog RGB signal Sa can be accurately sampled and output as shown by the solid line in FIG. 7D, but the clock signal CLK (FIG. 7 When c)) is supplied to the A / D converter 1, the analog RGB signal Sa cannot be accurately sampled and output as indicated by the double-dashed line in FIG. 7D.

Therefore, it is necessary to optimally adjust the phase of the clock signal CLK by the phase shift amount setting device 14 so that the analog RGB signal Sa can always be sampled and output with the optimum phase.

Further, since the phase shift amount adjusted by the phase shift amount setting unit 14 differs depending on the connected display device, the operator checks the image of the digital RGB signal Sd on the screen for each display device. It is necessary to adjust the amount of phase shift so as to obtain an optimal image, and there is a disadvantage that the adjustment work is troublesome.

Further, even if the operator once adjusts the phase shift amount to the optimum value, the phase shift amount changes due to a change in power supply voltage, ambient temperature, aging, and the like, so that there is a problem that a readjustment operation is required. .

By the way, the digital RGB of FIG.
The signal Sd waveform is represented as an analog voltage level for easy understanding.

In the RGB signal conversion method of the second conventional example shown in FIG. 8, there is no problem when the clock signal CLK is supplied from the outside, but the digital RGB signal Sd is
The phase locked by the L circuit 57 and the clock signal CL
In the case of reproducing K, if the analog RGB signal Sa contains very little luminance component and is very close to black, or if there is very little change in the image, there is very little or no phase comparison target. The phase lock of the PLL circuit 57 becomes impossible, the oscillation frequency becomes unstable,
In the worst case, there was a problem of low reliability such as the stop of oscillation.

Here, the present invention provides an RGB signal conversion method and apparatus capable of autonomously generating and outputting a digital RGB signal having an optimum phase without any adjustment operation.

[0020]

In order to solve the above problems, the present invention employs the following novel characteristic methods and means.

That is, a feature of the method of the present invention is that when the number of clocks per line of a horizontal synchronizing signal (Ssy) for horizontal synchronizing an analog RGB signal (Sa) is N, the analog RGB signal (Sa) is Synchronous signal (Ss
y) and (n × N) of the horizontal synchronization signal (Ssy)
A sampling signal (Ss) is generated by oversampling at a frequency (n is an integer) times the frequency of the sampling signal (Ss), and (n × N) of the horizontal synchronizing signal (Ssy) with respect to the sampling signal (Ss)
A plurality of delay sampling signals (Ss1, Ss
2), and outputs the sampling signal (Ss) and the plurality of delay sampling signals (Ss1 and Ss2) in synchronization with the frequency N times the horizontal synchronization signal (Ssy). Sampling signal (Ss
1, Ss2), a sampling signal (Ss) or a plurality of delayed sampling signals (Ss
1, Ss2) is an RGB signal conversion method for selectively outputting any one of digital RGB signals (Sd).

The feature of the device of the present invention is that when the number of clocks per line of the horizontal synchronizing signal (Ssy) for horizontal synchronizing the analog RGB signal (Sa) is N, it is synchronized with the horizontal synchronizing signal (Ssy) and A clock generating means (107) for generating an oversampling clock signal (3CLK) having a frequency (n × N) times (n is an integer) times the horizontal synchronizing signal (Ssy), and an analog RGB signal (Sa) as an oversampling clock signal A / D conversion means (101) for oversampling in synchronism with (3CLK) to perform analog / digital conversion and output as a sampling signal (Ss), and a plurality of oversampling clock signals (3CLK) for the sampling signal (Ss). Respectively, and a plurality of delayed sampling signals (Ss1, Ss ) And a sampling clock signal (CLK) having a frequency (1 / n) times the oversampling frequency of the sampling signal (Ss) and the plurality of delayed sampling signals (Ss1, Ss2). ), And the sampling is performed in accordance with each combination of the sampling signal (Ss) output from the synchronization output means (104) and the plurality of delayed sampling signals (Ss1, Ss2). Any one of the signal (Ss) or the plurality of delayed sampling signals (Ss1, Ss2)
Control means for selectively outputting one of the two as a digital RGB signal (Sd).

In the present invention, by adopting such a method and means, the present invention oversamples an analog RGB signal at n times the frequency of the input horizontal synchronizing signal, and converts the oversampled oversampled signal. By delaying by a plurality of cycles and selecting and outputting a specific one of a sampling signal or a plurality of delayed sampling signals in accordance with a combination of the signal level differences of the plurality of adjacent n points, the phase is autonomously calculated. Can be obtained an optimized digital RGB signal.

[0024]

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an RGB signal converter according to an embodiment of the present invention.

Here, the sampling clock frequency of 3
When oversampling at twice the frequency, ie, n =
The case of 3 will be described.

In the block diagram of the RGB signal conversion apparatus of the present embodiment shown in FIG. 1, an A / D converter 101 receives analog RGB signals from an external analog RGB signal output device (not shown) such as a personal computer or a workstation.
The signal Sa is supplied to the sampling input terminal, and the clock supply terminal φ is supplied with the oversampling clock signal 3CLK from the PLL circuit 107.

The first D-FF (flip-flop) circuit 102 has an input terminal D connected to a sampling output terminal of the A / D converter 101 and a PL terminal connected to a clock supply terminal φ.
Oversampling clock signal 3 from L circuit 107
CLK is supplied. The second D-FF (flip-flop) circuit 103 has an input terminal D connected to the Q output terminal of the first D-FF circuit 102 and a clock supply terminal φ.
Is supplied with an oversampling clock signal 3CLK from the PLL circuit 107.

In this way, the sampling signal Ss and the first and second delayed sampling signals Ss1 and Ss2 corresponding to the three phases in one period of the normal sampling clock are extracted from the analog RGB signal Sa.

The gate circuit 104 has a sampling terminal Ss and a delayed sampling signal Ss1,
Ss2 is supplied, and at the same time as the rising edge of the clock signal CLK supplied from the PLL circuit 107, the signals Da, Db, and Dc are output in the same phase. The output signal control circuit 105 detects a level difference between the signals Da, Db, and Dc, and outputs a switching control signal Sct corresponding to a combination of these level differences as shown in FIG.
In this way, of the signals Da, Db, and Dc, a signal having a small level difference therebetween, that is, a signal having a small error from the original analog RGB signal Sa is selectively output.

The switch 106 receives the input signals Da, D
One of b and Dc is selected and output as a digital RGB signal Sd according to the switching control signal Sct.

The phase comparator 108 receives the horizontal synchronizing signal Ssy input from an external video output device (not shown) and (1/1).
N) Compare the phase with the output signal of the frequency divider 112, and output the phase error signal Ser to the loop filter 109. Here, N is a horizontal synchronization signal Ss of a video output device (not shown).
This is the number of clocks per cycle of y.

The loop filter 109 smoothes the input phase error signal Ser using a leaky integration circuit or the like, and outputs a control voltage Vct.

The control voltage Vct output from the loop filter 109 is input to the VCO 110, and the control voltage Vc
It oscillates and outputs an oversampling clock signal 3CLK having a frequency 3fc corresponding to t.

The (1/3) frequency divider 111 divides the oversampling clock signal 3CLK by (1/3) and generates and outputs a sampling clock signal CLK having a frequency fc.

Next, the signal conversion operation will be described.

In FIGS. 1 and 3, the A / D converter 10
Analog RGB input to the sampling input terminal 1
The signal Sa (FIG. 3A) is the 3N of the horizontal synchronization signal Ssy.
It is sampled with the oversampling clock signal 3CLK (FIG. 3B) having a frequency 3fc (N: the number of clocks), and is output as a sampling signal Ss (FIG. 3C).

The sampling signal Ss is added with a delay corresponding to one cycle of the sampling clock signal 3CLK having a frequency of 3fc by the first and second D-FF circuits 102 and 103, and the delayed sampling signals Ss1 and Ss2, respectively.
(FIGS. 3D and 3E). By the way,
Sampling signal Ss, delayed sampling signal Ss1,
Each of Ss2 is actually a digital binary value.
Here, it is expressed as an analog voltage level for easy understanding. Sampling signal Ss, delayed sampling signal S
The signals s1 and Ss2 are output at the rising edge of the sampling clock signal CLK supplied to the gate circuit 104, are aligned in phase, and are output as signals Da, Db, and Dc, respectively. These signals Da, Db, Dc are supplied to the output signal control circuit 105. FIG. 2 is a block diagram of the output signal control circuit.

As shown in FIG. 2, the signals Da and Db are supplied to a subtractor 151, and the difference component (Da-Db) is output. Further, this difference component is input to the comparator 155 by the absolute value circuit 153 as a signal Dd of the absolute value of the difference component. The comparator 155 compares the signal Dd with the reference value Dr of the reference value holding unit 157 and outputs the result as a signal Df.

Similarly, the signals Db and Dc are supplied to a subtractor 152, and the difference component (Db-Dc) is output. Further, the difference component is supplied to the comparator 156 by the absolute value circuit 154 as a signal De of the absolute value of the difference component. The comparator 156 compares the signal De with the reference value Dr of the reference value holding unit 157, and outputs the result as a signal Dg. The selection circuit 158
As shown in an example in FIG. 5, the switching control signal Sct is output according to the values of the signals Df and Dg. FIG. 5 is an example of a switching condition table of the output signal control circuit 105. This switching condition table is
Level difference (Dd) between signal Da and signal Db and signal Db
The level difference (De) between the signal and the signal Dc by the reference value Dr
, And those of the level differences (Dd, De) smaller than the reference value Dr are extracted. Since any one of the signals Da, Db, and Dc that is the source of the signal (Dd, De) with a small level difference extracted in this way is selectively output, the level of the sampling point with a small sampling error is selected and output. Is done.

The output signal control circuit 1 configured as described above
05 constitutes a kind of majority circuit, detects the level difference between the signal Da and the signal Db and the level difference between the signal Db and the signal Dc, and the level difference is smaller than the reference value Dr.
That is, any one of the signals Da, Db, and Dc having a small difference from the signal levels at the other oversampling points is selectively output.

The signals Da, Db and Dc are supplied to the switch 1 respectively.
06, and one of them is selectively output as a digital RGB signal Sd according to the switching control signal Sct.

FIGS. 4A to 4F show the sampling clock signal, the signals Da, Db, Dc and the switching control signal Sct.
And the switch 106 controlled by the switch control signal Sct.
3 shows a digital RGB signal Sd which is an output signal of the first embodiment. By the way, the signals Da, Db, in FIGS. 4 (b), (c), (d)
Dc and the switching control signal Sct in FIG. 4E are actually digital binary values, but are represented here as analog voltage levels for easy understanding.

The RGB signal conversion method and apparatus according to the present embodiment can be configured as described above.
Signals Da and D sampled during one cycle of
b, Dc, the digital RGB signal S having the optimum phase
d can be selected and output autonomously.

In the above embodiment, the RGB signal input Sa is sampled with the oversampling clock signal 3CLK having a frequency 3fc three times as high as the sampling clock signal CLK, and 2 (= 3 (double frequency) -1) stages , But the frequency is arbitrary and the D-FF
The number of delay stages by the circuit is arbitrary. As the frequency is higher and the number of delay stages is greater, the number of sampling points increases, so the conversion accuracy improves.However, from the viewpoint of the following speed and manufacturing cost,
It is desirable to select an optimal frequency and number of delay stages.

Further, when sampling at a frequency n · fc which is n times the frequency fc, the sampling of the optimum phase is performed from the sampling signals at n places in one waveform of the sampling clock signal by delaying (n−1) stages. Although the signal is selected, any number of delay stages less than n may be used.

Further, a D-FF circuit 10 is used as a delay circuit.
2,103, but the sampling clock signal CL
Of course, it may be replaced with another circuit element having a function of adding a delay process synchronized with K. As the gate circuit 104, another circuit element having a function of aligning the phases of a plurality of input signals and outputting the signals in synchronization with the sampling clock signal CLK may be used.

[0048]

By adopting the above configuration, the RGB signal conversion method and apparatus of the present invention exhibit the following effects.

As a first point, the analog RGB signal is sampled at an integral multiple of the frequency of the horizontal synchronizing signal and A / D converted, and the digital signal having the optimum phase is obtained from a plurality of sample points in one cycle of the sampling clock. RGB
Since the signal is selected and output autonomously, there is an advantage that the operation of adjusting the phase shift amount setting device of the PLL circuit by the operator, which is conventionally indispensable, is unnecessary.

Second, even if a change in power supply voltage or ambient temperature or aging occurs, the digital RGB signal of the optimum phase is autonomously followed and selected and output, so that the phase amount setting device of the PLL circuit is adjusted. There is an advantage that no work is required.

Third, when the analog RGB signal contains almost no luminance component and is very close to black as compared with a method in which the analog RGB signal is directly phase-locked using a PLL circuit to reproduce a clock signal. Also, there is an advantage that the sampling clock signal can be surely reproduced even when the change of the video is very small.

[Brief description of the drawings]

FIG. 1 is a block diagram of an RGB signal conversion device according to an embodiment of the present invention.

FIG. 2 is a block diagram of an output signal control circuit.

FIG. 3 is a waveform diagram of each part of the RGB signal conversion device according to the present embodiment.

FIG. 4 is a waveform diagram of each portion of another portion of the RGB signal conversion device according to the present embodiment.

FIG. 5 is an example of a switching condition table of the output signal control circuit.

FIG. 6 is a block diagram of a first conventional example of an RGB signal converter.

FIG. 7 is a waveform diagram of each part of the RGB converter of the first conventional example.

FIG. 8 is a block diagram of an RGB signal converter according to a second conventional example.

[Explanation of symbols]

 1,51,101 A / D converter. 02 First D-FF circuit 103 Second D-FF circuit 104 Gate circuit 105 Output signal control circuit 106 Switcher 7, 57, 107 PLL circuit 8, 108 Phase comparator 9, 109 Loop filter 10, 110 VCO 111 (1/3) frequency divider 12, 112 (1 / N) frequency divider 151, 152 subtractor 153, 154 absolute value circuit 155, 156 comparator 157 reference value holding unit 158 selection circuit 13 phase shifter 14 phase shift Volume setting device 58 switch

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI // H03M 1/12 H03M 1/12 C

Claims (7)

[Claims] When the number of clocks per line of a horizontal synchronization signal for providing horizontal synchronization to an analog RGB signal is N, the analog RGB signal is synchronized with the horizontal synchronization signal and (n × N) times (n is an integer) times oversampling to generate a sampling signal, and (n) of the horizontal synchronizing signal with respect to the sampling signal
.Times.N) to generate a plurality of delayed sampling signals by respectively applying a plurality of stages of delays corresponding to a plurality of cycles of the frequency, and to generate the sampling signals and the plurality of delayed sampling signals at N times the frequency of the horizontal synchronization signal. And outputting any one of the sampling signal or the plurality of delayed sampling signals as a digital RGB signal corresponding to a combination of the sampling signal and the plurality of delayed sampling signals. An RGB signal conversion method, characterized in that: 2. A combination of the sampling signal and the plurality of delayed sampling signals is synchronized with a frequency N times as high as the horizontal synchronizing signal, and a combination of the sampling signal having the highest frequency of occurrence or the plurality of delayed sampling signals is used. 2. The RGB signal conversion method according to claim 1, wherein any one of the signals is selectively output as the digital RGB signal. 3. When the number of clocks per line of a horizontal synchronizing signal for horizontal synchronizing an analog RGB signal is N, (n) of the horizontal synchronizing signal is synchronized with the horizontal synchronizing signal.
A clock generating means for generating an oversampling clock signal having a frequency of (N) times (n is an integer); oversampling the analog RGB signal in synchronization with the oversampling clock signal to perform analog / digital conversion; A / D conversion means that outputs the sampling signal and a plurality of delay signals that respectively delay the sampling signal by a plurality of cycles of the oversampling clock signal and output the plurality of delayed sampling signals. Synchronous output means for outputting a delayed sampling signal in synchronization with a sampling clock signal having a frequency (1 / n) times the oversampling frequency; and the sampling signal output from the synchronous output means and the plurality of delayed sampling signals Corresponding to each combination issue, digital RG any one of the sampling signal or the plurality of delayed sampling signal
And a control means for selecting and outputting a B signal. 4. When the number of clocks per line of a horizontal synchronizing signal for horizontal synchronizing an analog RGB signal is N, (n) the horizontal synchronizing signal is synchronized with the horizontal synchronizing signal.
A clock generating means for generating an oversampling clock signal having a frequency of (N) times (n is an integer); oversampling the analog RGB signal in synchronization with the oversampling clock signal to perform analog / digital conversion; An A / D converter that outputs the sampling signal; a plurality of flip-flop circuits that respectively delay the sampling signal by a plurality of periods of the oversampling clock signal and output the plurality of delayed sampling signals; Of the oversampling clock signal by (1 /
n) a gate circuit that outputs in synchronization with a sampling clock signal having a frequency twice as high; the sampling signal output from the gate circuit and the plurality of delay sampling signals are input; and the sampling signal is output from the gate circuit. And control means for generating and outputting a switching control signal in accordance with a combination of the plurality of delayed sampling signals, and among the sampling signals and the plurality of delayed sampling signals passed through the gate circuit in accordance with the output of the output control signal An RGB signal conversion device, comprising: a switch for selecting and outputting any one of them. 5. A clock-controlled oscillating circuit for oscillating and outputting a sampling clock signal having a frequency (n × N) times the horizontal synchronizing signal, wherein the clock generating means divides the oversampling clock signal by (1 / n). The (1 / n) frequency divider that outputs the frequency, the phase of the output of the (1 / n) frequency divider and the phase of the externally input horizontal synchronization signal are compared, and the oscillation frequency and the oscillation phase are sent to the voltage controlled oscillation circuit. 5. The RG according to claim 3, further comprising: a phase comparator that outputs a control signal of
B signal converter. 6. The control means includes: a plurality of subtracters for calculating absolute values of respective difference components between the sampling signal and the plurality of delayed sampling signals; and a combination of output signals of the plurality of subtracters. 6. The RGB signal conversion device according to claim 3, further comprising a selection circuit for outputting a predetermined switching control signal correspondingly. 7. The switching control signal for selecting and outputting one of the sampling signal having the most frequently occurring level or the plurality of delay sampling signals in synchronization with the sampling clock signal. 7. The method according to claim 3, wherein:
The RGB signal conversion device as described in the above.