JPH1097465A - Multiprocessor system - Google Patents

Abstract

(57) Abstract: In a main storage sharing multiprocessor, both speedup by simultaneous execution (SMP) of a plurality of processes by multiple processors and speedup by parallel execution (ASMP) by a plurality of processors of one process are compatible. . SOLUTION: A mode bit for indicating whether SMP / ASMP is being executed or which part of the program is being executed is provided, which can be changed by an OS or a user program, and different cache coherent control is performed according to the value of the mode bit. Start the circuit to be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system sharing a main memory, and more particularly to a multiprocessor for achieving both the objective of improving throughput by simultaneously executing a plurality of processes and increasing the speed of executing one process in parallel. About the system.

[0002]

2. Description of the Related Art In recent years, in order to improve the performance of a processor system, a multiprocessor configuration including a plurality of processors sharing a main memory has been generally adopted.

A main memory sharing multiprocessor (hereinafter referred to as SM)
P: Symmetric Multi-Process
The purpose of (or) is roughly divided into (1) improvement of system throughput by simultaneous execution of a plurality of processes on a plurality of processors, and (2) parallel execution of a plurality of processes on a plurality of processors (1 process is divided and divided. Speedup by executing each process in parallel by each processor at the same time).

In order to achieve both of the above objects, the following is generally performed in the prior art. That is, execution of a single processor is accelerated by using a cache, and consistency between the processor caches is guaranteed by a cache coherent mechanism of hardware. The cache coherent mechanism is roughly classified into a snoop method and a directory method. In each method, it manages whether each line in each processor cache matches with other lines or the contents of main memory, and when a mismatch occurs, the match is determined via a connection network between processors. The mismatch is eliminated by copying / updating / invalidating the cache line to be taken, thereby preventing the processor from malfunctioning. Some caches are divided into instruction caches and data caches, and the program side is restricted from rewriting instructions so that coherence between instruction caches is not taken. Regarding this, "Information Science Core Curriculum Course Computer Architecture I",
Pages 167 to 177, written by Shinji Tomita, published by Maruzen Publishing.

[0005]

However, in the above-mentioned prior art, in a multiprocessor system sharing a main memory, even when the system is simultaneously executing a plurality of processes or when executing one process in parallel. Used the exact same cache coherent scheme.

When a multiprocessor system composed of a plurality of processors is executing a plurality of processes at the same time, each processor generally executes a different process. Therefore, the cache of each processor rarely points to the same main memory. The performance is improved by controlling the cache coherent mechanism so as not to be activated as much as possible. As a result, cache coherence in multiprocessor systems running multiple processes simultaneously is often
When there is data in the cache of the own processor, the contents of the cache are not sent to the connection network with other processors, and the contents of the instruction cache are not sent to the connection network with other processors.

However, the cache coherent method of a multiprocessor system in which a plurality of processes are simultaneously executed by a plurality of processors is not necessarily the most suitable method when the multiprocessor system executes a plurality of processors in parallel.

This will be described with reference to an example in which DO10 and DO20 of the FORTRAN program shown in FIG. 3 are executed in parallel by four processors for the subscript i.
The program in FIG. 3 is executed as follows. 310
0, 3300 is one processor in a system having a plurality of processors (this is called a parent processor).
This is executed by PE0, and portions 3200 and 3400 are referred to as a plurality of processors (these are called child processors).
These are assumed to be PE1, PE2 and PE3) and the parent processor. When the execution of 3100 is completed, the parent processor PE0 activates the child processors PE1 to PE3,
Subscript i = 3-8, 9-12, 13-1
6 respectively, and the subscripts i = 1 to 4
To share. When the execution of all the processors ends, the parent processor PE0 executes 3300, and when it ends,
The child processors PE1 to PE3 are activated again, and the subscripts i = 5 to 8, 9 to 12, 13 to 16 of 3400 are executed, respectively, and the subprocessors share the subscripts i = 1 to 4. While the parent processor is executing 3100 and 3300, the child processors wait for activation from the parent processor.

In the execution of this program, the child processor group is notified of the instruction address of the program portion to be executed only after being started by the parent processor. Therefore, 1
When using the cache coherent method in which multiple processes are executed simultaneously by multiple processors as the cache coherent method when processes are executed in parallel by multiple processors, the contents of the instruction cache are not notified to other processors. Instruction cache misses often occur.

In the execution of the above program, the child processor group fetches data to be executed only after being started by the parent processor. Therefore, as a cache coherent method in which one process is executed in parallel by a plurality of processors, a cache coherent method in which a plurality of processes are executed simultaneously by a plurality of processors is used. Since the contents of the cache are not sent to the connection network with the processor, execution of the above program often causes a data cache miss. As a result, due to a large penalty of a cache miss, a situation occurs in which even if one process is executed in parallel, the performance is not significantly improved.

The above situation is that the coherent method originally required for parallel execution by a plurality of processors in one process and the coherent method required for simultaneous execution by a plurality of processors in a process have different characteristics. Nevertheless, it occurs because we are trying to maintain coherence by the same means.

An object of the present invention is to provide a system for realizing different cache coherent schemes when a system is executing a plurality of processes at the same time and when a process is executing one process in parallel in a multiprocessor system with shared main memory. It is to provide a configuration.

[0013]

According to the present invention, there is provided a system comprising: a plurality of processors each having a cache; a connection line connecting the processors; and a content matching control circuit between the caches. A mode in which a first plurality of processors in the processor group execute a plurality of processes simultaneously on the first plurality of processors or a mode in which one process is executed in parallel on the first plurality of processors First information for identifying the content matching control circuit, and the operation of the content matching control circuit is switched according to the information.

The content matching control circuit includes a plurality of functional units, and includes a circuit for selecting which one of the functional units is to be activated according to the information.

Further, the mode for simultaneously executing one process by the first plurality of processors includes a mode for executing a parallel operation part of the process and a mode for executing a non-parallel operation part of the process. Means for switching between a mode for executing the parallel operation part and a mode for executing the non-parallel operation part, and means for switching the operation of the content matching control circuit in accordance with the mode for executing the parallel operation part and the mode for executing the non-parallel operation part And

Still further, a mode in which the content coincidence control circuit is constituted by a plurality of functional units, wherein the one process is simultaneously executed by the first plurality of processors, and a non-parallel operation portion is executed. In the case of (1), a circuit for selecting the functional unit is provided so that each cache of the first plurality of processors is updated with the same entry.

Further, in the content matching control circuit, a mode in which one process is simultaneously executed by the first plurality of processors and a mode in which a non-parallel operation part is executed are provided. Update the cache of each of the processors with the same entry.
Furthermore, in the case where the content matching control circuit is constituted by a plurality of functional units, the one process is simultaneously executed by the first plurality of processors, and the parallel operation part is executed. , So that each cache of the first plurality of processors is updated with an individual entry.

Still further, the first plurality of processors comprises one parent processor and another child processor,
The operation of the content matching control circuit is changed depending on whether the parent processor or the child processor.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. First, terms in the present embodiment are defined. A system consisting of multiple processors
A mode indicating that a plurality of processes are being executed simultaneously by a plurality of processors is hereinafter referred to as SMP (Symmetric).
A Multi-Processor (SM) mode, which indicates that one process is being executed in parallel by a plurality of processors, an ASMP (Asynchronous S)
MP) mode. Further, the processor group in the ASMP mode is provided with a non-parallelized portion of the program (3100 in FIG. 3,
3300 etc. The case where the single part is being executed is referred to as single mode, and the parallel part (3200, 3200 in FIG. 3) is executed.
300 etc. (Hereinafter, referred to as a parallel portion) is referred to as a parallel mode.

FIG. 1 shows the overall configuration of a system according to an embodiment of the present invention. Processor groups 10 to 13 (PE0 to PE0)
PE 3) and the main memory 43 are connected via an address / command bus 41 and a data bus 42. Each of the processor groups 10 to 13 has an instruction cache (Icache).
e), and a data cache (Dcache). The signal lines 18 to 21 connect the processor group and the address / command bus 41. The signal lines 22 to 25 connect the processor group and the data bus 42. The signal line 26 connects the main memory 43 and the address / command bus 41 to the signal line 2.
7 connects the main memory 43 and the data bus 42. These components are also provided in a conventional SMP system (a system in which a multiprocessor system is simultaneously executing a plurality of processes).

Further, a constituent element unique to this embodiment is
It has a synchronization information bus 40 for connecting and synchronizing the processors of the processor groups 10 to 13, and signal lines 14 to 17 for connecting the processor group and the synchronization information bus. The synchronization information bus is used for notifying mode information and a value of a program counter (that is, an instruction address) to be described later.

FIG. 2 shows the internal configuration of the processor 10. The configuration of the other processors 11 to 13 is the same, and the description is omitted. The processor has an instruction cache (Icac)
he) 52, an instruction unit 53 for controlling instruction execution and an instruction cache, an arithmetic unit (ALU) 57, a load store unit (LSU) 56, a data cache (Dcache) 51, a data unit 50 for controlling the data cache, and a register 58. Consists of Also, signal lines 60, 62, 63, 64, 65, 6
6, 68, signal lines 18-0, 1 for connection to an external bus
8-1, 22-0 and 22-1. These components are also provided in a well-known SMP system, and
The operation in the MP mode is the same as the operation of the known SMP system.

Further, FIG. 2 shows a mode line in the instruction unit 53 which is a component specific to this embodiment, a signal line 67 for transmitting information of the mode bit to the data unit, and a signal line 14 for connecting to the synchronization information bus 40. Having. The mode determined by the mode bit will be described with reference to FIG.

FIG. 11 shows the configuration of the mode bits in the above embodiment. The mode bits are: (1) ASMP bit: ASMP mode (mode (Asy) indicating that one process is being executed in parallel by a plurality of processors in the main memory shared multiprocessor system.
nchronous SMP mode)) or SMP
Mode (mode indicating that a plurality of processes are simultaneously executed by a plurality of processors in a main memory shared multiprocessor system (SMP mode)) (here, when the ASMP bit = 1, the ASMP mode and the ASMP mode). (2) parent bit: indicates whether the own processor is a parent or a child in the ASMP mode (here, pa
parent when parent bit = 1, parent bit =
(3) para bit: indicates whether the parallel part or single part of the program is currently being executed in the ASMP mode (here, if the para bit = 1, The parallel part is executed, and the single part is executed when para bit = 0).

The ASMP bit and the parent bit are changed by the OS (operating system). pa
The ra bit is changed by the user program and the OS.
Here, each mode type is recorded in the form of bit information, but may be recorded in any form as long as it can record information that can identify them. For example, a register may be provided, and information for identifying them may be stored in the register in the form of numbers or alphabetic symbols.

The operation when the present system operates in the SMP mode will be described below. The OS first sets the ASMP bit of the processor operating in the SMP mode to “0” (SMP
Mode), and an independent process is assigned to each processor.

In the SMP mode, the processor operates as follows (see FIG. 2). The instruction unit 53 fetches the instruction in the instruction cache 52 when the instruction is present, and sends out the instruction fetch line transfer request to the address / command bus 41 via the signal line 18-1 when the instruction is not present, and 52 controls to receive the instruction line from the data bus 42. Instruction unit 53
Decodes the instruction fetched via the bus, and controls the arithmetic unit ALU 57 for an arithmetic instruction, and the load store unit 56 for a load store instruction via a signal line 68.

If the instruction is a load store instruction, the load store unit 56 sends the instruction type and address to the data unit 50 via the signal line 60. The data unit 50 controls the data cache 51 to send the data to the register 58 when the data is present in the data cache 51. If there is no data, signal line 18
A data fetch line transfer request is sent to the address / command bus 41 via −0, and the data cache 51 is controlled to receive a data line from the data bus 42.

FIG. 6 shows a data cache coherence method in the SMP mode performed in the present embodiment. This system is a well-known system known as the Berkeley protocol ("Information Science Core Curriculum Course Computer Architecture I", pp. 170-173, Shinji Tomita, Maruzen Publishing).

In FIG. 6, what is surrounded by "circles" is
The status of each cache line of the cache is shown. "I"
Is Invald (there is no data in its own cache),
"V" is Valid (there is data in the own cache and the content matches the main memory. There is a possibility that the same data exists in other caches). "D" is Dirty (there is data in the own cache and the content Is different from the main memory. It is not in other caches.), "Sh.D" is Shared Dir
ty (there is data in the own cache, the content is different from the main memory. There is a possibility that the same data exists in other caches).

FIG. 6A shows an access (L: load, ST: store, Castout:
Due to the write back to the main memory accompanying the replacement), how the state of each cache line changes, and a transaction is generated in accordance with the change in the cache line state, and is output to another processor via a bus. A transaction transmitted on the bus is referred to as a bus transaction). This bus transaction is surrounded by a "square" in FIG. This bus transaction is notified to other processors via the bus (address / command bus 41, data bus 42). The bus transaction includes LTreq: a line transfer request associated with loading of another processor, LTreq-forST: a line transfer request associated with storage of another processor, Inv: an invalidation request issued from another processor, and Busout: the corresponding cache of its own cache Output the contents of the line to the data bus,
There is.

FIG. 6B shows a bus transaction (LTreq, LTreq-) from another processor via the bus.
ForST, Inv, Busout), it indicates how the state of its own cache of the own processor changes, and what kind of bus transaction to transmit to another processor occurs. The bus transactions that occur are boxed. Here, "Busout & S
h. D instruction (output of the contents of the cache line of the own cache to the data bus and a request for Sh.D conversion at the data fetch destination).

For example, when the own processor executes a store instruction for a line that is a Valid, the state shifts to Dirty in order to write to the line of the own processor, and at the same time, an Inv transaction is issued to the bus (FIG. 6 (a)). On the other hand, if the same line is Valid in another processor, it receives the bus transaction Inv, the line is invalidated, and the state shifts to I (see FIG. 6B).

This protocol is well-known, and its operation is clear from the state transition diagram, and will not be described further here. However, according to this protocol, the caches of a plurality of processors in the SMP mode store the same main memory location. Even in the case of sharing, the consistency of the cache contents is guaranteed. The operation when the present system operates in the SMP mode has been described above.

Next, the operation of the present system in the ASMP mode will be described. The OS first selects as many processor groups as required by the program to be executed in parallel, and
The MP bit is set to 1. Furthermore, only one of them is par
Set the ent bit to 1 (this processor is the parent),
The parent bits of the other processors are set to 0 (these processor groups are children). Thereafter, each thread (corresponding to a task) of the same process (corresponding to a job) is allocated to the selected processor group.

FIG. 3 shows an example of a program to be executed in parallel. Which part of the program is executed in parallel is as described in the section of "Problems to be Solved by the Invention".

FIG. 4 is an image of a machine language instruction sequence for executing the program of FIG. 3 in parallel. The numbers attached to the left side of the instruction sequence are conveniently added as machine language instruction addresses. In the present embodiment, both the parent processor and the child processor group execute the same instruction sequence starting from exactly the same address.

In the instruction sequence, switch_to_sing
le_mode instruction and switch_to_p
The ara_mode instruction is an instruction newly provided in the present embodiment. The operation of this instruction differs depending on whether the processor executing the instruction is a parent or a child, that is, the value of the parent bit.

(1) switch_to_single
_Mode instruction execution When the parent bit is 1 (in the case of the parent processor),
When the switch_to_single_mode instruction is decoded, the processor outputs a signal indicating that processing from the child processor to the barrier (synchronization point set by the plurality of processors in advance by a program) from the child processor group via the synchronization information bus 40 (this signal). Is called a barrier signal), and after receiving the above signals from all the child processors, it is confirmed that synchronization has been achieved between all the processors (barrier synchronization). The parent processor is switch_to_
Decoding the single_mode instruction means that the processing has been completed up to the barrier), and issues an instruction to the synchronization information bus 40 to change the mode to single.

When the parent bit is 0 (for a child processor), switch_to_single_mo
Upon decoding the de instruction, the processor sends a signal to the synchronization information bus 40 indicating that the processor has completed processing up to the barrier, and then stops updating the program counter. That is, each child processor enters a state in which instruction fetching and execution are suspended, and the parent processor waits for all child processors to reach the barrier before executing subsequent instructions.

(2) switch_to_para_m
Execution of mode instruction When the parent bit is 1 (in the case of the parent processor),
When the switch_to_para_mode instruction is decoded, the parent processor instructs the synchronous information bus 40 to change the mode to parallel, and sends the program counter of the instruction being executed at that time to the synchronous information bus 40. When the mode is changed to parallel, the child processor receives the program counter sent to the synchronization information bus 40 and restarts updating the program counter from the value. That is, the parent processor releases the suspended state (stall state) of the child processor and resumes from the instruction being executed at that time. When the parent bit is 0 (for a child processor), switch_to_par
Decoding the a_mode instruction causes the processor to do nothing.

Switch_to_single_mo
Since the operations of the de instruction and the switch_to_para_mode instruction are as described above, the machine language instruction sequence in FIG. 4 is executed as follows. That is, the instruction sequence 1002 is executed only by the parent processor, and the instruction address 920 is transmitted to the child processor by the instruction 1003.
The parent and child processors execute the instruction sequence 1004 in parallel.
Here, the instruction sequence 1002 corresponds to 3100 in FIG. 3, and the instruction sequence 1004 corresponds to 3200. “Compute_my_addr” in the instruction sequence 1002 is an abbreviation of an instruction sequence for calculating addresses of data to be assigned to the respective processors independently of each other.
The instruction 1005 causes the child processor to stop executing, and the parent processor confirms that barrier synchronization has been established.
Execute 006. In addition, the parent again by instruction 1007,
The child processors start parallel execution of the instruction sequence 1008,
The instruction 1009 returns to execution of only the parent processor. Here, the instruction sequence 1006 corresponds to 3300 in FIG.
The instruction sequence 1008 corresponds to 3400.

That is, the program shown in FIG.
First, processing is started by the parent processor and the child processor group, but switch_to_single_m
By the mode instruction, the child processor group is in a suspended state,
It will be processed only by the parent processor. After that, switch_to_para_mod is performed by the parent processor.
When the e instruction is processed, the value of the program counter of the parent processor for resuming the program is notified to the child processor group, and the program processing is performed by all the processors from the value of the program counter. Also, swi
When the tch_to_single_mode instruction is executed, the same processing as described above is repeated. The above operation is the sequence of instruction sequence parallel execution based on the mode bits.

The cache coherent operation based on the mode bits will be described below.

First, an outline of the operation will be described with reference to FIG. A
In this embodiment, the cache coherent operation in the SMP mode and the parallel mode is the same as that in the SMP mode. That is, the coherence of the data cache is shown in FIG.
Perform based on. There is no coherence in the instruction cache.

In the ASMP mode and the single mode,
Only the parent processor executes the instruction sequence, but the coherent mechanism operates so that the result of the execution by the parent processor is reflected in the data cache of the child processor. That is, the cache line written by the parent processor is Sh.
The data line broadcast to all child processors with the D attribute and read by the parent processor is
Broadcast to all child processors with the V attribute. As for the instruction cache, the child processor suspends (stalls) the execution of the instruction, but controls so that the line transfer result for the instruction fetch generated by the parent processor is also taken into its own instruction cache. As described above, the contents of the caches of the respective processors which were separated in the parallel mode gradually change to the contents of the cache of the parent processor during execution in the single mode (details will be described later).

FIG. 7 shows a state transition method for maintaining the coherence of the data cache while realizing the above. FIG.
(A) shows how each state transits and what kind of bus transaction occurs due to an access occurring in the own processor. FIG. 7B shows how the state of its own cache changes due to a transaction generated from the bus, and what kind of bus transaction is generated.

For example, when a store instruction is executed from the own processor to a line of V, a broadcast is generated to another processor at the same time as writing to the line of the own processor. D (see FIG. 7)
(A)). On the other hand, if the same line is V in another processor, the bus transaction Broadca
st, the line is fetched into the cache, and the state is changed to Sh. The process proceeds to D (see FIG. 7B). The correct operation of this state transition will be described later using the machine language instruction sequence in FIG.

FIGS. 8 and 9 show a configuration for realizing the processor operation and the cache coherent operation based on the above mode bits.

FIG. 8 is a configuration diagram of the data unit 50. The data cache state storage mechanism 79 stores the address of the data line held in the data cache 51 and the state thereof. The value of the mode bit in the instruction unit 53 is output to the signal line 67.

When the signal line 67 indicates the SMP mode and a load store request is received from the load store unit 56 via the signal lines 60-0 and 60-1,
According to the state transition of FIG. 6A, the combinational circuit 80 sends signals for controlling the bus transaction generation circuits 71 to 76, the line fetch instruction circuit 77 to the data cache, and the cache state change circuit 78 to the signal lines 101 to 107,
93.

Specifically, for example, when a store request is sent to the signal line 6
0-1 and the store address is input to signal line 6
It is assumed that the value is input to 0-0. The data cache state storage mechanism 79 compares the store address with the state of the cache, and indicates the state of the line of the access request destination, that is, “I”, “V”, “D”, or “Sh.D” on the signal line 91. Send out. In addition, the signal line 92 outputs Cas in response to the store request.
The address of the line to be touted is sent out. For example, "V" is indicated on the signal line 91, and C
If there is no line to be stalled, the combination circuit 80 activates the invalidation transaction generation circuit 73,
An invalidation transaction is generated for the address / command bus 41 via the encoding circuit 81. Further, the combination circuit 80 activates the state change circuit 78 and changes the state of the access request destination line to “D”.

A transaction generated from the bus is input to signal line 18-0-1. Combination circuit 80 takes in the lines to bus transaction generation circuits 71 to 76 and the data cache in accordance with the state transition of FIG. 6B. The instruction circuit 77 sends out a signal line for controlling the cache state changing circuit 78.

The operation when the signal line 67 indicates the ASMP and the parallel mode is the same as the operation in the SMP mode in the present embodiment.

When the signal line 67 indicates the ASMP and single mode, the combination circuit 80 operates as shown in FIG.
According to the state transition of (b), a signal line for controlling the bus transaction generation circuits 71 to 76, the line fetch instruction circuit 77 for the data cache, and the cache state change circuit 78 is transmitted.

Specifically, for example, a store request is sent to the signal line 60.
-1 and its store address is
It is assumed that the value is input to −0. The data cache state storage mechanism 79 sends out V on the signal line 91, and
If the line to be done is not shown on signal line 92, combinational circuit 80 activates broadcast transaction generation circuit 76. The broadcast transaction generation circuit 76 is connected to the data cache 5 through a signal line 65.
For 0, the line on which the store result is reflected is sent to the data bus 4
2 and the encoding circuit 8
1 and a broadcast transaction is generated for the address / command bus 41. Further, the combination circuit 80 activates the state change circuit 78 and changes the state of the access request destination line to Sh. Change to D.

FIG. 9 is a block diagram of the instruction unit 53.

The instruction cache state storage mechanism 153 stores the address of the instruction line held in the instruction cache 52. The program counter 131 indicates the address of the instruction to be executed. As a result of checking the instruction address in the instruction cache state storage mechanism 153, if the instruction to be sought is not in the instruction cache 52, the state change circuit 13
4. Send the instruction line fetch request via the signal line 18-1-0. When an instruction line fetch request is issued, the state change circuit 134 sends a line fetch instruction to the instruction cache on a signal line 66-1 and an instruction cache state change instruction on a signal line 155. When there is an instruction to be sought in the instruction cache 52, an instruction request is sent to the instruction cache 52 via a signal line 66-0,
Instructions are sent via 2. The instruction is a decoding circuit 120
If the instruction is a normal operation or load store instruction, the decoded result is sent to a signal line 68 to control the operation unit 57 or the load store unit 56. The instruction modulates the ASMP, swi in FIG.
tch_to_single_mode instruction (100
1) and the switch_to_para_mode instruction (1003), the decoded result is the signal line 15
3 is sent. The program counter 131 is connected to the signal line 1
58, each time an instruction is fetched. The above is the operation of the common instruction unit 53 regardless of the mode bits.

Next, the operation of the instruction unit 53 related to the mode bits will be described.

When the mode bit 152 indicates the SMP mode, the combinational circuit 122 that operates according to the combination of the output 153 from the decoder 120 and the output 152 from the mode 121 does not output anything. That is, the operation of the instruction unit 53 is as described above.
The to_single_mode instruction (1001) and the switch_to_para_mode instruction (100
3) is ignored.

When the mode bit 152 indicates the ASMP mode, the switch line_switch_to_si
ngle_mode instruction (1001) and switchc
When the h_to_para_mode instruction (1003) is sent, the combinational circuit 122 includes a PC (program counter) fetch circuit 123 and a PC (program counter) update suppression circuit 12 for suppressing update of the program counter.
4. I-line fetch instruction circuit 125, barrier sending circuit 126 for sending a signal for notifying that the program processing in the own processor has reached a barrier point, mode Broad for notifying the child processor of the mode change A -Cast circuit 127, a barrier completion wait circuit 128 that activates the mode broadcast circuit 127 when all child processors are notified of arrival at a barrier point, and a PC transmission circuit 129 that transmits a program counter value to another processor as follows. To control.

That is, parent = 1, para = 1
Indicates switch_to_single
When the _mode instruction is sent to the signal line 153, the barrier completion wait circuit 128 and the mode broadcast circuit 12
7 is started. The barrier completion wait circuit 128 is connected to the signal line 14
When it is notified to −0 that all child processors have reached the barrier point, the mode broadcast circuit 127 is activated.
Switchc when parent = 1 and para = 0
When the h_to_para_mode instruction is sent to the signal line 153, the mode broadcast circuit 127 and the program counter sending circuit 129 that sends the program counter value to another processor are activated.

On the other hand, if parent = 0 and para = 1, switch_to_single_m
When the "mode" instruction is sent to the signal line 153, the barrier sending circuit 126 and the program counter update inhibiting circuit 124 are activated. When an instruction to switch the mode in parallel is input to the signal line 14-0 when parent = 0 and para = 0, the mode bit 121 is set to para = 1 and the program counter fetch circuit 123 is set via the combinational circuit 122. It starts and controls to take in the program counter sent to the signal line 14-0.

The contents of the cache when the machine language instruction sequence shown in FIG. 4 is executed will be described with reference to FIGS. 6, 7, and 10A. It is assumed that the cache can hold four data in one line.

FIG. 10 shows each of the instruction strings 1001 to 10 in FIG.
9 shows the contents of the instruction cache and the data cache of the parent processor (PE0) and the child processors (PE1 to PE3) when four processors are executed. In FIG. 10, since the child processors perform the same operation, only the contents of the cache of PE1 are shown. The contents of the instruction cache are indicated by instruction addresses given for convenience in FIG. In the figure, an instruction or data marked with * indicates that a cache miss or fetching of broadcasted data has occurred. A in the figure
(1) When displayed as shown in (1) to (4), starting from A (1)
A (1), A (2), A (3),
Assume that A (4) is in the cache.

When the instruction 1001 in FIG. 4 is executed, P
Assume that an instruction cache miss has occurred in both E0 and PE1. PE1 suppresses updating of the program counter, and enters a stop (stall) state. PE0 to PE3 enter the single mode, and PE0 starts executing the instruction sequence 1002. P
Assuming that no data is stored in the data cache of E0, all of P, S, A (1)-are line-transferred. At this time, the data cache of PE1 (child processor) fetches P, S, A (1)-according to FIG. 7B [from state I to LTreq or LTreq-forS
Transition by T]. Valid only for PE0 (parent processor)
d and others (child processors) are Sh. D. Also P
E1 (The child processor fetches the same address 910 as the PE0 in the instruction cache. That is, while the child processor is in the suspended state, the update of the instruction and data cache of the child processor is performed together with the instruction and data cache update of the parent processor. Since these fetching processes are performed under the influence of the line transfer of PE0, the processing time does not increase.

When PE0 (parent processor) executes the instruction 1003, the parent processor makes the mode of the synchronous information bus parallel and outputs the program counter.
PE1 (child processor) takes in the program counter, and all processors start parallel execution of the instruction sequence 1004. Since the same line as that of PE0 is stored in the instruction cache of PE1, no instruction cache miss occurs.
Since S is stored in the data cache of PE1, no cache miss occurs for S. A
For (5) to B (5), a cache miss occurs. Since the execution of the instruction sequence 1004 is performed based on the state transition in FIG. 6, the contents of the caches of PE0 and PE1 differ considerably. In PE1, B (5) ~ is Dirty
Is held in the state of.

When the instruction 1005 is executed, when the PE1 (child processor) reaches the barrier point, it sends a barrier signal indicating this to the synchronization information bus 40 and enters the stall state. When the instruction 1005 is executed, the PE0 (parent processor) waits for barrier signals from the PE1 to PE3 (child processors), and upon receiving all of them, sets the mode to single.

In the execution of the instruction sequence 1006, the cache coherence control follows the state transition of FIG. Therefore PE1
B (5) to B (16) changed by P0 to P3 are broadcast each time PE0 refers, and all PEs are sh. It holds B (5) to B (16) of the D attribute. For example, PE0 (parent processor) uses Sh. D, and the PEs 1 to 3 (child processors) change the state from the state I of FIG.
Move to D.

The instruction 1007 is executed in the same manner as the instruction 1003. The instruction sequence 1008 is executed in parallel by all PEs. However, since PE1 has already fetched B (5) to cache, no miss occurs.

For comparison, FIG. 5 shows a machine language instruction sequence image when the program of FIG. 3 is executed in parallel by the conventional method.
FIG. 10B shows the contents of the cache when this instruction sequence is executed in the normal SMP mode, that is, in accordance with the state transition of FIG.

FIG. 5A shows an instruction sequence executed by the parent processor, and FIG. 5B shows an instruction sequence executed by the child processor group.
Store_begin_ of the instruction 2003 in FIG.
The addr instruction represents a sequence for activating the child processor and notifying the child processor of the execution start address. Loadall_en of the instruction 2005 in FIG.
The d instruction represents a sequence for counting the end flags notified by the child processor. As shown in FIG. 5B, it is assumed that the child processor performs the spin wait when it reaches the non-parallel execution part of the program.

As apparent from FIG. 10B, in the conventional method, the instruction cache of PE1 (child processor) misses when entering the parallel part of the program (2004, 2).
008). Data cache misses that did not occur in the embodiment of the present invention have occurred in 2004 and 2008.

It is apparent from the above that the conventional method has a larger penalty for cache misses and hinders performance improvement by one-process parallel execution.

[0075]

As described above, according to the present invention, a mode in which a plurality of processes are simultaneously executed by a plurality of processors (SMP mode) or a mode in which one process is executed in parallel by the first plurality of processors (ASMP mode) is described. Is provided, and the operation of the content matching control circuit is switched according to the information, so that a cache coherent control method suitable for each mode can be selected. For example, in the SMP mode, by keeping the contents of the cache of each processor as independent as possible, it is possible to improve the throughput of executing a plurality of processes without activating the coherent mechanism unnecessarily. On the other hand, in the ASMP mode, a cache coherent method suitable for a program execution part (a mode in which a parallel operation part of a process is executed and a mode in which a non-parallel operation part is executed) can be adopted.
The performance of parallel execution of processes can be improved.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a processor system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a processor of the present invention.

FIG. 3 is an example program.

4 is a machine language instruction sequence image of the program of FIG. 3 in the present invention.

FIG. 5 is an image of a machine language instruction sequence in the prior art of the program of FIG. 3;

FIG. 6 is a state transition diagram illustrating a cache coherence scheme.

FIG. 7 is a state transition diagram illustrating a cache coherence scheme.

FIG. 8 is a configuration diagram of a data cache coherent mechanism of the processor of the present invention.

FIG. 9 is a configuration diagram of an instruction cache coherent mechanism of the processor of the present invention.

FIG. 10 shows cache contents of the present invention and the prior art.

FIG. 11 shows the configuration of an operation switching mode bit according to the present invention.

[Explanation of symbols]

 51 data cache, 52 instruction cache, 50 data units, 53 instruction units, 121 mode bits, 40 synchronization information bus, 71 to 77 data cache coherent circuit, 123 to 129 instruction cache coherent circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Naobu Sukekawa 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd.

Claims (7)

[Claims] 1. A system comprising: a plurality of processors each having a cache; a connection line connecting the group of processors; and a content matching control circuit between the caches; a first plurality of processors in the group of processors. Comprises first information for identifying a mode in which a plurality of processes are simultaneously executed by the first plurality of processors or a mode in which one process is executed in parallel by the first plurality of processors; A multiprocessor system for switching the operation of the content matching control circuit according to 2. The multiprocessor system according to claim 1, wherein said content matching control circuit comprises a plurality of functional units, and further comprises a circuit for selecting which one of said functional units to activate according to said information. 3. The mode in which one process is simultaneously executed by the first plurality of processors further includes a mode in which a parallel operation part of the process is executed and a mode in which a non-parallel operation part is executed. Means for switching between a mode for executing the operation part and a mode for executing the non-parallel operation part, and switching the operation of the content matching control circuit according to the mode for executing the parallel operation part and the mode for executing the non-parallel operation part 2. The multiprocessor system of claim 1, further comprising: 4. A mode in which the content matching control circuit is composed of a plurality of functional units, wherein the one process is simultaneously executed by the first plurality of processors, and a non-parallel operation part is executed. 4. The multiprocessor system according to claim 3, further comprising a circuit for selecting the functional unit such that, in some cases, each cache of the first plurality of processors is updated with the same entry. 5. A mode in which the content coincidence control circuit is composed of a plurality of functional units, wherein the one process is simultaneously executed by the first plurality of processors, and a mode in which a parallel operation part is executed. 4. The multiprocessor system according to claim 3, further comprising a circuit for selecting the functional unit so that each cache of the first plurality of processors is updated with an individual entry. 6. The content matching control circuit according to claim 1, wherein said mode is a mode in which one process is simultaneously executed by said first plurality of processors, and said mode is a mode in which a non-parallel operation part is executed. 4. The multiprocessor system according to claim 3, wherein each cache of the plurality of processors is updated with the same entry. 7. The first plurality of processors comprises one parent processor and another child processor, and the operation of the content matching control circuit is changed according to the parent processor or the child processor. Multiprocessor system.