JPH1091575A - Digital video storage server and data transfer method thereof - Google Patents

Abstract

(57) Abstract: The present invention reduces I / O bus contention between data transfer from a disk device 153 to a memory 134 and data transfer from a memory 134 to a network 123. Also, the wait cycle of the bus due to the latency generated at the time of memory read is reduced. SOLUTION: Two data transfers are performed by an I / O bus 107.
And the I / O bus 103. Although the transfer path from the storage adapter 150 to the memory 134 has a long pipeline stage, data is transferred at high speed in parallel by a continuously issued write command and a pipeline operation. As a transfer path from the memory 134 to the communication adapter 120, a path having a small number of passing buses is selected, and the wait cycle of the bus is reduced. In the case of data transfer from the network 123 to the disk device 153, the memory 144 is used as a buffer, and a path with a small number of buses that passes when reading the memory is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital video storage server having a storage device for storing digital video data and having a function of transmitting and receiving the digital video data to and from an external network.

[0002]

2. Description of the Related Art In recent years, with the development of ATM technology, communication capacity has been expanded, video / audio data has been digitized, compression technology has been developed, and storage prices, such as hard disks, have been reduced. The market is rising. One of them is the existing CAT
Video on demand (V
OD) Services have been proposed.

[0003] On the other hand, in the editing field for creating video titles, great movements are taking place along with the development of digital technology. Conventionally, video data has been recorded on magnetic tape. Cut editing employs a method of dubbing a necessary portion of video data from a tape to another tape, and has been performed by a dedicated editing device including title input, audio editing, and the like. In recent years, there is a growing need to use graphics, titles, and the like created on computer hardware for video. In addition, by storing video data on a hard disk and editing it, it is possible to reduce the time required for winding and the like in the case of tape, and it is possible to reduce video degradation by converting to digital video. A non-linear editing system has been devised which edits a file on a computer basis.

[0004] Many of these systems store video data on a local disk for editing. This limits the amount of video data that can be used for editing work. In addition, since it is impossible to share video data, it is necessary to copy data when editing work is shared. CSS (Client Server) that records video data on a large-scale storage and shares it using a network
There is a demand for a (System) type non-linear editing system.

Bus performance is one of the factors that determine the performance of a digital video storage server, such as a VOD server that delivers a requested video in the VOD service or a video server for editing.

The computer constituting the digital video storage server is generally composed of two buses. One is a system bus connecting the CPU and the main memory. The other is a magnetic disk device or display device,
An I / O bus for connecting network devices and the like. The main I / O buses are VME bus, S bus, ISA bus,
There are an EISA bus, a GIO bus and the like. In recent years, CQ publisher interface special issue "OpenDesign" No.
The PCI bus described in 7 "Details of PCI Bus and Steps to Application" is often used.

[0007] Since the digital video storage server stores video data input from the network in a data storage device such as a magnetic disk, the sustained performance of the I / O bus affects the performance of the system.

[0008] As a technology for accelerating the digital video storage server, a technical report of the Institute of Television Engineers of Japan, ITE Techni.
cal Report: Vol. 18, No. 2
0. pp1-6. VIR "94-13.CE 94-1
2 (Mar 1994) (March 18, 1994), "High multiplex reading method of digital moving image information", as shown on page 5, data read from the magnetic disk is performed from the VME bus side and transmitted to the network (FDDI). VSB (VME Subsystem)
A method using the (Bus) side has been devised. Japanese Patent Laid-Open No. 4-291439 discloses a technique for improving the performance of a video server by using a two-port memory.

FIG. 7 is a diagram showing a configuration example of a computer operating as a digital video storage server. 200
Denotes an arithmetic processing unit (CPU), and 202 denotes a main storage device (M
M, hereinafter referred to as host memory), 203 is an I / O bus,
A bridge 201 connects the CPU 200, the host memory 202, and the I / O bus 203. I / O bus 20
3 is a PCI (Peripheral Component)
nt Interconnect) bus. 204
Is a bus connecting the CPU 200 and the bridge 201, 2
A bus 05 connects the host memory 202 and the bridge 201. The communication adapter 22 is connected to the I / O bus 203.
0 and the storage adapter 250 are connected. The communication adapter 220 includes a bus adapter (BA) 221 and an ATM conversion circuit 222. ATM conversion circuit 222
Is a circuit connected to the network 223 to assemble and reassemble ATM cells. Bus adapter 2
Reference numeral 21 controls data transfer between the host memory 202 and the ATM conversion circuit 222 via the I / O bus 203 and the bridge 201. The storage adapter 250 includes a bus adapter (BA) 251 and a SCSI control circuit 252. The SCSI control circuit 252 is connected to the disk devices 253 and 254 via the SCSI cable 255, and controls data transfer between the disk devices 253 and 254 having a SCSI interface and the host memory 202. Storage Adapter 250
Controls data transfer between the host memory 202 and the SCSI control circuit 252 via the I / O bus 203 and the bridge 201. In the digital video storage server having such a configuration, when video data stored in the disk devices 253 and 254 is delivered to the network 223, data transfer via the I / O bus 203 and the bridge 201 occurs twice. For this reason, bus contention occurs due to these two data transfers, and only half of the throughput performance of the I / O bus 203 can be used to deliver video data.

FIG. 8 is a timing chart showing an example of a read cycle of the I / O bus 203. The figure shows an example in which data is transferred from the host memory 202 to the communication adapter 220 or the storage adapter 250. The adapter is the initiator and the host memory 202 is the target. The signals in FIG. 8 are, in order from the top, a bus clock (CLK), an address data bus (AD), a command /
Bus enable (C / BE #), initiator ready (IRDY #), and target ready (TRDY #). The adapter card that has acquired the right to use the bus is CLK2
Issues an address and a read command. The address is an address of the host memory 202. A memory read operation is performed by controlling the host memory 202 for the address. The initiator has asserted IRDY # because it is ready to receive data. However, the target host memory 202 takes a long time to fetch the data at the specified address.
Is deasserted. Therefore, from CLK3 to CLK3
Up to 5 wait cycles occur. Host memory 2
02 completes preparations for data transfer, the TR
DY # is asserted to transfer the first data. Subsequently, four data are transferred in CLK7 to CLK9, and the bus transaction ends.

FIG. 9 is a timing chart showing an example of a write cycle of the I / O bus 203. The figure shows an example in which data is transferred from the communication adapter 220 or the storage adapter 250 to the host memory 202. The adapter is an initiator and the host memory 202 is a target. An address and a write command are issued in CLK2. In the case of writing to the target, in many cases, a wait cycle does not occur by writing to the buffer of the bridge 201 and then writing through to the host memory 202. Therefore, data transfer can be performed continuously from CLK3 to CLK6, and writing can be generally completed with a smaller number of clocks than a bus transaction for reading. Further, in a write transaction, a pipeline operation is possible by forwarding a command and data on a bus, and high-speed data transfer is possible.

As shown in the above example, the read cycle has a long wait cycle due to the latency time of the memory, and the bus throughput decreases. Latency time increases as the number of data pipeline stages increases,
The bus performance is accordingly reduced.

[0013]

According to the above prior art, there is a problem that bus contention occurs due to two data transfers in the digital video storage server, and the transfer throughput of video data is limited. In a read transaction, a wait cycle occurs until the data specified by the address arrives before the bus, resulting in a problem that the bus efficiency is reduced. In particular, when the bus is configured in multiple stages by the bus bridge, the efficiency of the read transaction decreases.

An object of the present invention is to reduce bus contention when transferring video data between a video storage device and a network, and to provide a digital video storage server having a transfer path with a small latency time for memory reading and a digital video storage server. It is to provide a data transfer method.

[0015]

SUMMARY OF THE INVENTION The present invention provides a first memory card connected to a first I / O bus together with one of a communication adapter and a storage adapter, and one of the other of the communication adapter and the storage adapter. A second memory card connected to a second I / O bus,
A digital video storage server having a bridge interposed between a first I / O bus and a second I / O bus, and a bus interconnecting the first memory card and the second memory card. Features.

The present invention also relates to a data transfer method for a digital video storage server configured as described above, wherein one adapter supplies a second I / O bus, a second memory card, and the bus. The data is written to the memory in the first memory card, the data is read from the memory of the first memory card, and the data is transferred to the other adapter via the first I / O bus. I /
An O bus, a first memory card, data is written to a memory in a second memory card via the bus, data is read from a memory of the second memory card, and a second I / O
The method is characterized in that data is transferred to one adapter via the O bus.

[0017] Two video data transfers when transferring video data between the video storage device and the network are performed in two ways.
Since one I / O bus is used properly, bus contention can be reduced. Further, since data is read from the memory via a path having a small number of circuit stages, efficient data transfer at the time of memory reading is possible, and thus the data transfer performance of the system can be improved.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of the digital video storage server of the present embodiment. 100 is a CPU, 102 is a host memory, 103 is an I / O bus, 101 is a CPU 10
0, a bridge connecting the host memory 102 and the I / O bus 103 (Host to PCI Bridge). 104, a bus connecting the CPU 100 and the bridge 101; 105, a host memory 102 and the bridge 10;
1 is a bus that connects to Reference numeral 107 denotes an I / O bus. Reference numeral 106 denotes a bridge (PCI to PCI Bridge) connected to the I / O bus 103 and the I / O bus 107.
e), enabling data transfer between the I / O bus 103 and the I / O bus 107. Bridge 101 and Bridge 1
06 enables data transfer between the host memory 102 and various adapter cards connected to the I / O bus 107. Reference numeral 120 denotes a communication adapter, and the I / O bus 10
3 and an ATM conversion circuit 122 connected to the network 123. Another computer such as a client is connected to the end of the network 123. Reference numerals 130 and 140 are memory cards for temporarily storing and holding video data, which are connected to the I / O bus 103 and the I / O bus 107, respectively. 131 and 141 are I / O bus 103 and I / O bus, respectively.
A bus adapter (BA) connected to the O bus 107. Reference numerals 134 and 144 denote random accessible memories. 133 and 143 are memory control circuits (MC) for controlling the memories 134 and 144, respectively. 13
2 and 142 are I / O bus 103 and I / O bus 1, respectively.
07 and a bus adapter (BA) mutually connected via a bus 135. Bus adapter 1
32 and 142, the I / O bus 103 and the memory 1
Data transfer between the I / O bus 107 and the memory 134 is possible. Reference numeral 150 denotes a storage adapter, which includes a bus adapter 151 connected to the I / O bus 107 and a SCSI control circuit 152 connected to the disk devices 153 and 154 via a SCSI cable 155.

The CPU 100 can be constituted by a general-purpose microprocessor such as a Pentium processor or an alpha processor. I / O bus 103 and I / O bus 1
07 is PCI (Peripheral Compon)
ent Interconnect) bus. The bridge 101 can be constituted by a general-purpose chip set, and the bridge 106 is a general-purpose PC.
It can be configured by an I-PCI bridge.

The bridge 106 shown in FIG. 1 transfers a bus transaction relating to the memory space mapped to the I / O bus 107 from the I / O bus 103 to the I / O bus 107.
Transfer to Of the bus transactions issued to the I / O bus 107, those other than the memory space managed by the bridge 106 are the I / O bus 103.
Transfer to Similarly, the bridge 101 accesses the host memory 102 in accordance with the mapped memory space or issues a bus transaction to the I / O bus 103.

The memory 134 can be accessed with two addresses, a physical address seen from the I / O bus 103 side and an address seen from the I / O bus 107 side.
I / O by using different addresses to access
The access can be made via the bus 103 and the bus adapter 131, or by another route via the bridge 106, the I / O bus 107, the bus adapter 142, and the bus adapter 132. Similarly, the memory 144
By using different addresses to access,
It is possible to access via the O bus 103 and the bus adapter 142, or to access via another route via the bridge 106, the I / O bus 107 and the bus adapter 141.

The communication adapter 120 is the network 1
23, the data received from the bus adapter 121 and the I / O
Bus 103, bus adapter 132, bus adapter 142
Can be transferred to the memory 144 via the. The data stored in the memory 144 is transferred to the bus adapter 14.
1. Data can be transferred to the disks 153 and 154 via the I / O bus 107 and the bus adapter 151.

FIG. 2 is a diagram showing the flow of data when the video data stored in the disk devices 153 and 154 is transferred to another computer via the network 123 in the digital video storage server shown in FIG. It is. In FIG. 2, 200, 201, 202, 203, 2
04, 205, 206, 207 and 209 are respectively a SCSI control circuit 152, a bus adapter 151, a bus adapter 142, a bus adapter 132 and a memory control circuit 1
33, a buffer provided in the memory control circuit 133, the bus adapter 131, the bus adapter 121, and the ATM conversion circuit 122. Also, 211, 214 and 215 are
A bus adapter 132 and a memory control circuit 133,
This bus connects between the memory control circuit 133 and the bus adapter 131, and between the bus adapter 121 and the ATM conversion circuit 122. The control software executed on the CPU 100 issues a data transfer command to the SCSI control circuit 152. The video data of the disk devices 153 and 154 are read by the SCSI control circuit 152, and are read by the bus adapter 151, the I / O bus 107, and the bus adapter 14.
2, memory 135 via bus 135 and bus adapter 132
34. Next, the control software executed on the CPU 100 issues a data transfer command to the ATM conversion circuit 122. The video data on the memory 134 is output to the network 123 via the bus adapter 131, the I / O bus 103, and the bus adapter 121, and further via the ATM conversion circuit 122. Since data transfer is performed through the above route, bus contention does not occur, and the data transfer performance of the video server can be improved. Further, since the data transfer from the disk devices 153 and 154 to the memory 134 is a data write operation via the I / O bus 107 and the bus 135, the I / O is performed by a pipeline operation that forwards the data one after another.
A wait cycle as shown in FIG. 8 by the O bus 107 and the bus 135 does not occur. ATM conversion circuit 12
When the second device reads data from the memory 134, the number of intervening bus adapters and bridges is small, so that a read bus transaction can be executed with a small number of wait cycles.

FIG. 3 shows a data flow when video data transferred via the network 123 is stored in the disk devices 153 and 154. CPU 100
The control software executed above issues a data transfer command to the ATM conversion circuit 122. The ATM conversion circuit 122 converts the received data into a bus adapter 121, an I / O
The data is transferred to the memory 144 via the O bus 103, the bus adapter 132, the bus 135, and the bus adapter 142.
Next, the control software executed on the CPU 100 is:
A data transfer command is issued to the SCSI control circuit 152. The SCSI control circuit 152 transfers the video data in the memory 144 to the disk devices 153 and 1 via the bus adapter 141, the I / O bus 107, and the bus adapter 150.
Transfer to 54. Since data transfer is performed through such a path, bus contention does not occur, and the data transfer performance of the digital video storage server can be improved.

FIG. 4 is a diagram showing the timing of the data transfer shown in FIG. The video data is transferred by repeatedly performing a data write operation from the buffer 200 to the memory 134 and a data read operation from the memory 134 to the buffer 209. The data transfer by these two operations can operate in parallel because they pass through different buses. In a data write operation, data is transferred at high speed in parallel by a continuously issued write command and a pipeline operation. On the other hand, in the data read operation, the issued read command occupies the bus until the data arrives, so that the speed is lower than that in the data write operation, which determines the system performance. As shown in FIG. 4, according to the present embodiment, a bus transaction can be completed in 11 clocks to perform a 4-word read operation. The timing of the data transfer shown in FIG. 3 is the same, and the bus transaction can be completed in 11 clocks to perform the 4-word read operation.

As shown in FIG. 5, instead of the data transfer path shown in FIG. 2, video data of the disk devices 153 and 154 are transferred to the SCSI control circuit 152 and the bus adapter 15.
1. The data is transferred to the memory 144 via the path of the I / O bus 107 and the bus adapter 141, and the video data in the memory 144 is transferred to the bus adapter 142, the bus 135, and the bus adapter 13.
2. I / O bus 103, bus adapter 121 and ATM
It is assumed that the data is transferred to the network 123 via the path of the conversion circuit 122. At this time, the data transfer timing is shown in FIG.
It becomes what is shown in. When data is read from the memory 144, the data passes through the bus 135, so that the time for the read data to arrive at the buffer 209 becomes longer. Therefore, 15 clocks are required to perform a 4-word read operation, which is slower than the data transfer path in FIG.

As described above, the memory 134 is used for outputting video data, and the memory 1 is used for inputting video data.
By selectively using the two memories 134 and 144 so as to use the memory 44, the data read operation can be performed at a high speed, thereby improving the data transfer throughput performance of the entire system.

Instead of the SCSI control circuit 152, another disk interface, for example, a control circuit for controlling a fiber channel or the like may be used. Instead of the ATM conversion circuit 122, a control circuit for transmitting and receiving data to and from other networks such as FDDI and Ethernet other than ATM may be used. Further, the I / O bus 103 and the I / O
A plurality of communication adapters 120 and storage adapters 150 can be connected to the bus 107. Further, a configuration in which the storage adapter 150 is directly connected to the I / O bus 103 and the communication adapter 120 is connected to the I / O bus 107 is also possible. Further, a configuration in which the communication adapter 120 is connected to the I / O bus 103 via another bridge is also possible.

[0030]

According to the present invention, different I / Os are used for two data transfers in the digital video storage server.
Since the buses are properly used, bus contention can be reduced. Further, since a data transfer path with a small latency time at the time of memory reading is provided, the efficiency at the time of memory reading can be improved, and the data transfer performance of the system can be improved. Furthermore, since efficient data transfer in both directions from the video storage device to the network and from the network to the video storage device is possible, it can be applied as a VOD server and as a server connected to a video data editing device.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital video storage server according to an embodiment.

FIG. 2 is a diagram showing a data flow when data is transferred from the disk devices 153 and 154 of the embodiment to a network 123.

FIG. 3 is a diagram showing a data flow when data is transferred from the network 123 to the disk devices 153 and 154 according to the embodiment.

FIG. 4 is a timing chart of the data transfer shown in FIG. 2;

FIG. 5 is a diagram for explaining another flow of data when data is transferred from the disk devices 153 and 154 to the network 123.

FIG. 6 is a timing chart of the data transfer shown in FIG. 5;

FIG. 7 is a configuration diagram of a conventional digital video storage server.

FIG. 8 is a timing chart showing an example of a conventional read cycle of the I / O bus 203.

FIG. 9 is a timing chart showing an example of a conventional write cycle of the I / O bus 203.

[Explanation of symbols]

103: I / O bus, 106: bridge, 107: I /
O bus, 120: communication adapter, 130: memory card, 135: bus (between memory cards), 140: memory card, 150: storage adapter

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hiroshi Yamashita 890 Kashimada, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Information and Communication Development Division, Hitachi, Ltd.

Claims (5)

[Claims] 1. A communication adapter connected to an external network, a storage adapter connected to an external storage device, a first memory card, a second memory card,
A CPU for controlling the communication adapter, the storage adapter, the first memory card, and the second memory card, wherein one of the communication adapter and the storage adapter and the first memory card are connected to a first memory card; An I / O bus, and the other of the communication adapter and the storage adapter and the second memory card are connected to a second I / O bus, and the first I / O bus and the second I / O bus are connected to the second I / O bus. An I / O bus is connected via a bridge, and a first memory card and a second memory card are mutually connected by another bus. Data is written to a memory in the first memory card via the second I / O bus, the second memory card, and the bus, and data is read from the memory of the first memory card. To transfer data to the other adapter via the first I / O bus, and from the other adapter to the first I / O bus, the first memory card, and the second memory card via the bus. A digital video storage server, wherein data is written to a memory in the internal memory, data is read from a memory of a second memory card, and data is transferred to one adapter via a second I / O bus. Method. 2. The digital video storage server according to claim 1, wherein control software is executed by said CPU, and data transfer between said adapter and any of said memory cards is started by said control software. Data transfer method. 3. A communication adapter connected to an external network, a storage adapter connected to an external storage device, a first memory card, a second memory card,
A CPU for controlling the communication adapter, the storage adapter, a first memory card, and a second memory card;
One of the communication adapter and the storage adapter, a first memory card and a first I / O bus connecting the CPU, and the other of the communication adapter and the storage adapter and a second memory card A first I / O bus connecting the first I / O bus and the second I / O bus, and a bridge interposed between the two I / O buses;
A digital video storage server comprising a memory card and a bus for interconnecting the second memory card. And executing data from one of the adapters into a second I / O bus, a second memory card, and a memory in the first memory card via the bus. Data is read from the memory of the memory card and the data is transferred to the other adapter via the first I / O bus, and the first I / O bus, the first memory card, and the bus are transferred from the other adapter to the other adapter. A program for writing data to a memory in the second memory card via the second memory card, reading data from the memory of the second memory card, and transferring the data to one adapter via the second I / O bus 4. The digital video storage server according to claim 3, further comprising means. 5. A communication adapter connected to an external network, a storage adapter connected to an external storage device, a first memory card, a second memory card,
A digital video storage server having the communication adapter, the storage adapter, and a CPU that controls a first memory card and a second memory card, wherein the digital video storage server stores video data held by one of the communication adapter and the storage adapter. The first memory card is written to a memory in the first memory card through a path passing through the second memory card, and is connected to a path connecting the first memory card and the other of the communication adapter or the storage adapter. The video data read from the memory of the second adapter is transferred to the other adapter, and the video data held by the other adapter is written to the memory in the second memory card through a path passing through the first memory card, Read from the memory in the second memory card through the path connecting the memory card and one adapter Digital video storage server, characterized in that a transferable data transfer path video data on one of the adapter has.