JPH1083696A - Semiconductor memory test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce memory capacity and the number of memories by converting the fail data to parallel data and performing a high speed transfer. SOLUTION: A memory part 1 is constituted of plural memories FD0-FD15, and a shift register 2 is constituted of plural flip-flop FL0-FL15, and the fail data sent at a serial signal are converted to a parallel signal. The fail data converted to the parallel signal are transferred to a first hold register 3, and are transferred to respective memories of the memory part 1 by enable signals from a first/CS generation part 4 and a second/CS generation part 5. By accelerating a fail data fetch period of a fail analysis memory, the memory capacity and the number of memories are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory test apparatus for testing a semiconductor memory, and more particularly to a failure analysis memory used in a semiconductor memory test apparatus.

[0002]

[Prior art]

(Semiconductor Memory Test Apparatus) FIG. 6 shows the basic configuration of the entire semiconductor memory test apparatus. FIG. 6 is a block diagram showing the configuration of the semiconductor memory test device.

In FIG. 6, a semiconductor memory test apparatus comprises a timing generator 10, a pattern generator 20, a waveform shaper 30, a logic comparator 40, and a failure analysis memory 50, and the output of the waveform shaper 30 is Memory 60
Is connected and the test is performed.

The timing generator 10 is a circuit for generating a reference clock for generating a test pattern for a memory test. The pattern generator 20 outputs an address signal, test data, and a control signal to be supplied to the memory under test 60 according to the reference clock generated by the timing generator 10. These signals are output to the waveform shaper 30, shaped into a predetermined waveform required for a memory test by the waveform shaper 30, and applied to the memory under test 60.

In the memory under test 60, data writing and reading are performed at the timing of the control signal. The output data read from the memory under test 60 is output to the logical comparator 40. The logical comparator 40 compares the expected value (data in a normal state of the memory) output from the pattern generator 10 with the output data read from the memory under test 60, and determines whether the memory 60 under test agrees or disagrees. Is determined.

If the expected value and the read output data do not match, the contents are stored as fail data in a failure analysis memory 50 described below.

(Failure Analysis Memory) FIG. 7 is a block diagram showing the structure of the failure analysis memory shown in FIG.

In FIG. 7, a failure analysis memory 50 includes an address selection section 51 for selecting and outputting a predetermined bit from an address signal generated by the pattern generator 20, and fail data (failure information) of a memory under test 60. And a memory control unit 5 for specifying a memory cell of the memory unit 53 in which the fail data is stored.
And 2.

[0009] The address selection unit 51 is provided with the pattern generator 20.
And outputs the upper address to the memory controller 52 and the lower address to the memory unit 53, respectively. The memory control unit 52 specifies the memory cell of the memory unit 53 by the output signal from the address selection unit 51 and the fail data sent from the logical comparator 40, and assigns the memory cell under test to the specified memory cell of the memory unit 53. 60 fail data are stored.

After the memory test is completed, the memory under test 60 is analyzed by examining the contents of the failure analysis memory 50.

(RAMBUS DRAM) Next, as an example of the memory under test 60, a RAMBUS DRAM (hereinafter referred to as RDRA) capable of writing and reading data at high speed.
M) will be described.

RDRAM is a DRAM capable of transferring packet data at high speed in synchronization with a reference clock.
And has a maximum data transfer rate of 500 MB / S or 533 MB / S.

FIG. 8 is a block diagram showing a configuration of the RDRAM. 8, the RDRAM 70 includes a DRAM unit 72 as a storage element, and a slave logic unit 71 as an interface unit with a bus and a control line.

The DRAM section 72 has the same structure as a conventional DRAM cell. The column address and the row address output via the slave logic unit 71 are decoded by the column decoder 721 and the row decoder 722, and the data is stored in the DRAM cell array 723 specified by the column address and the row address, respectively. The column decoder 721 has a built-in sense amplifier for amplifying a signal, which is different from a conventional DRAM cell in that the sense amplifier has a latch function. The RDRAM 70 enables high-speed data transfer by using a sense amplifier as a cache memory.

The RDRAM 70 is a type of memory called a burst memory, and transfers data at the time of writing and reading in a burst. The data transfer of the RDRAM 70 is performed in units of 8 words, and the burst length can be varied up to 256 words. Also, since it is not necessary to externally specify addresses of 3 bits corresponding to 8 words as a transfer unit, it is not necessary to input these addresses. The data burst start address is stored in a request packet including a read command, a write command, and a plurality of other commands.

The slave logic unit 71 designates a burst length of write data or read data, or controls a bit mask, a byte mask, and the like by using a plurality of instructions in these request packets.

By the way, a plurality of RDRAMs 70 are connected in series (as shown in FIG.
Of the RDRAM of the next stage.
When configuring one memory space (connected to In),
Each RDRAM 70 is provided by the slave logic unit 71.
Is performed.

FIG. 9 is a circuit diagram showing a case where a plurality of RDRAMs are connected and used. As shown in FIG. 9, a plurality of RDRAMs 0 to RDRAMn serving as slaves are connected in series to a master device serving as a master (Master), and each RDRA is transmitted by a request packet transferred from the master device via BusData [8: 0].
The operations of M0 to RDRAMn are controlled.

At the time of writing to the RDRAM or reading from the RDRAM, a write data packet and a read data packet as shown in FIG. 10 are placed on BusData [8: 0] in addition to the request packet. The "Okay" signal shown in FIG. 10 indicates that the RDRAM has received the request packet.

In the connection shown in FIG. 9, RxCLK is used as a clock for writing and Tx is used as a clock for reading.
CLK, the master device and RDRAM0 to RDRAM
Data skew and clock skew between the RAMs n are suppressed. This enables high-speed data transfer.

(Method of Loading Fail Data in Failure Analysis Memory) Next, a conventional method of loading fail data into a failure analysis memory will be described by taking as an example the case of testing a burst memory such as an RDRAM.

FIGS. 11A and 11B are diagrams showing a method for taking in fail data of a failure analysis memory of a conventional semiconductor memory test apparatus. FIG. 11A is a circuit diagram, and FIG. 11B is a diagram showing a storage format. FIG. 11 illustrates a memory under test (MUT) having a 4-bit width.

As shown in FIG. 11A, in a conventional failure analysis memory, a memory under test (MUT) is used as a memory unit.
1 bit SRAM corresponding to the bit width of
SRAMs are prepared for the bit width of the memory under test (four in FIG. 11A). When a failure occurs in an arbitrary bit in such a state, the x1SRA corresponding to each bit is output by the output of the logical comparator including the EXNOR circuit.
The / CS terminal of M is set to enable “L”. At this time, since the input data of each x1 SRAM is always set to “H”, “1” indicating a failure is written at the same address as the memory under test.

Although a high-speed SRAM is used for the memory section shown in FIG. 11A, when the memory under test operates at a higher speed than the SRAM of the failure analysis memory, the memory shown in FIG. Fail data is taken in using an interleave method.

FIG. 12 is a diagram for explaining the configuration of an interleaved failure analysis memory. Interleaving refers to reading and writing data while alternately arranging and switching memories. For example, if data is read from a plurality of memories with an access time of 100 ns while being shifted by 50 ns, data can be read with an access time of substantially 50 ns. Obtainable. FIG. 12 shows an interleave operation by eight memories (referred to as eight ways; each memory is referred to as a bank), and includes data D1 to D1.
8, D9 to D16,... Are stored in banks # 1 to # 8, respectively.

Here, in the case of the failure analysis memory shown in FIGS. 11A and 11B, all memories used in the interleave operation (FD0 to FD3 in FIG. 11A correspond to one bank) are accessed. Since it is used to speed up the time, the memory capacity for taking in the fail data is the capacity of one bank.

[0027]

However, the conventional semiconductor memory test apparatus as described above has a high operating speed of R.
Even if a high-speed SRAM is used for the memory section when fail data of a burst memory such as a DRAM is taken into the failure analysis memory, the RDRAM operates at a much higher speed than the SRAM. Using interleave had to work.

When the interleave operation is performed, a large number of SRA
Even if M is used, it is not possible to obtain a storage capacity in proportion thereto, so that a large number of expensive SRAMs have to be used when taking in fail data of a large-capacity RDRAM. Accordingly, there has been a problem that the component cost of the failure analysis memory increases and the mounting area of the failure analysis memory also increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and reduces the memory capacity and the number of memories required for a failure analysis memory while maintaining high-speed operation. It is an object of the present invention to provide a semiconductor memory test device in which the number is reduced.

[0030]

In order to achieve the above object, a semiconductor memory test apparatus according to the present invention includes a fail data which is failure information among test results of the memory under test in order to judge pass / fail of the memory under test. A semiconductor memory test apparatus provided with a failure analysis memory for storing the fail data in serial data format output in the order of addresses of the memory under test in the failure analysis memory, and outputting the data as parallel data. When,
A first hold register that simultaneously reads and temporarily holds parallel data output from the shift register, and a memory unit that holds fail data corresponding to an address of the memory under test in each memory bit, A CS signal generator for outputting an enable signal for transferring the parallel data held in the first hold register to the memory unit; and a fail signal corresponding to the fail data while transferring the fail data to the memory unit. A second hold register for holding the address data.

In the semiconductor memory test apparatus configured as described above, serial data format fail data is converted into parallel data by the shift register, and is simultaneously transferred to the memory unit via the first hold register with a predetermined number of bits. Will be transferred. Therefore, the fail data can be transferred to the memory unit at a higher speed than the conventional method of transferring the fail data to the memory unit one bit at a time corresponding to each bit of the memory under test.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

The semiconductor memory test apparatus of the present invention is different from the conventional semiconductor memory test apparatus in the format of fail data fetching of the failure analysis memory and the method of fetching fail data. The other configuration is the same as the conventional configuration, and the description thereof will be omitted.

In the following, a burst memory RD
A case where a test of the RAM is performed will be described as an example.

First, a description will be given of a fail data fetch format of the failure analysis memory of the semiconductor memory test apparatus of the present invention. FIG. 1 is a diagram showing a fail data fetch format of a failure analysis memory of the semiconductor memory test device of the present invention.

In the conventional fail data fetching format, as shown in FIG. 11B, each bit of the failure analysis memory is arranged corresponding to each bit of the memory under test. In the semiconductor memory test apparatus of the present invention, a failure analysis memory composed of an arbitrary number of bits is used like a 1-bit memory (in FIG. 1, a 16-bit failure analysis memory is used like a 1-bit memory). Yes), for example 1
Six memories FD0 to FD15 are allocated to addresses # 0 to #F. Then, these memories FD0 to FD15
Are prepared for the number of bits (BusData 0 to 8) of the memory under test. Note that, as described above, RDRAM
Performs burst transfer in units of eight words, so that fail data at the time of reading is output to the failure analysis memory in units of eight words.

Next, a description will be given of a method for taking in fail data of the failure analysis memory of the semiconductor memory test apparatus of the present invention. FIG. 2 is a circuit diagram illustrating a method of writing fail data to a failure analysis memory of the semiconductor memory test device of the present invention. FIG. 3 is a circuit diagram showing a configuration of the first / CS generator shown in FIG. FIG. 2 shows a circuit for one bit (BusData0) of the memory under test. B for BusData1 to BusData8
Since the circuit configuration is similar to usData0, the description thereof is omitted.

In FIG. 2, the memory unit 1 is constituted by a plurality of (16 bits) memories FD0 to FD15.
For example, an SRAM for holding fail data. The shift register 2 includes a plurality of flip-flops FL.
0 to FL15, and converts fail data sent as a serial signal to a parallel signal.

The fail data converted into the parallel signal is transferred to the first hold register 3 by a first storage signal or a second storage signal output in synchronization with a burst address # 7 or #F described later. You.

The first hold register 3 is composed of a plurality of flip-flops FF0 to FF15, and temporarily stores fail data corresponding to addresses # 0 to #F. The contents of the fail data held in the first hold register 3 are stored in the memories FD0 to FD15 of the memory unit 1 by the enable signals output from the first / CS generating unit 4 and the second / CS generating unit 5. Is forwarded to

The second hold register comprises two registers FFAD1 and FFAD2, and is a circuit for temporarily holding an address corresponding to fail data.

When the burst start address and the burst address are generated by the pattern generator (see FIG. 6), a signal obtained by adding these two addresses is applied to the failure analysis memory. The burst address indicates lower addresses # 0 to #F made up of lower 4 bits of an address signal output from the pattern generator, and an address selector (FIG. 6).
). Therefore, the address shown in FIG. 2 indicates the upper address obtained by cutting out the lower 4 bits from the address signal of the pattern generator.

In FIG. 3, the first / CS generation unit 4
A plurality of flip-flops operating as a shift register, fail data, and a higher address (# 8) of a burst address
To #F) or a JK flip-flop holding a fail flag detected by taking the logical product of the signals FA0 representing the lower order (# 0 to # 7), and the next clock after the burst address becomes # 7. (Reference clock)
Generates a first / CS enable signal. And the first
Immediately after the / CS enable signal is generated. Since the configuration and operation of the second / CS generator 5 are the same as those of the first / CS generator 4,
The description is omitted.

The operation of reading out burst data from the RDRAM as the memory under test in such a configuration will be described.

First, when the burst length is 8 words, when burst addresses # 0 to # 7 are sent, fail data as a serial signal is stored in the flip-flops FL0 to FL7 of the shift register 2 one bit at a time. You. When the burst address is # 7, a first storage signal is output from the address selection unit (see FIG. 6),
Fail data stored in the flip-flops FL0 to FL7 is transferred to the flip-flops FF0 to FF7 of the first hold register 3, respectively.

Here, when a failure occurs in any of burst addresses # 0 to # 7, the first / CS generation unit 4 outputs the first / CS enable signal in synchronization with the first storage signal. Is done. At this time, the first hold register 3
In this case, "1" indicating a failure is stored in one of the flip-flops FL0 to FL7 corresponding to the address where the failure has occurred, and the / CS terminal of one of the memories FD0 to FD7 connected to the output of the flip-flop is "L". "become. Data D of each memory FD0 to FD7 of the memory unit 1
Since “H” is always applied to the terminal, “1” is stored in the memory corresponding to the address where the failure has occurred, and is taken into the memory unit 1 as fail data.

On the other hand, when the burst length is 16 words, that is, when the burst address is output from # 0 to #F, the fail data fetch operation for the burst addresses # 0 to # 7 is performed in the same manner as in the case of 8 words. Done in

Next, when the burst addresses # 8 to #F are sent, the fail data is stored in the flip-flop F of the shift register 2 as in the burst addresses # 0 to # 7.
These are stored in L8 to FL15, respectively. Then, at the time of the burst address #F, the second storage signal is output, and the fail data stored in the shift register 2 is transferred to the flip-flops FF8 to FF15 of the first hold register.

Here, if a failure occurs in any of burst addresses # 8 to #F, a second / CS generation signal is generated from second / CS generation section 5 in synchronization with the second storage signal. I do. At this time, in the first hold register 3, "1" indicating a failure is stored in one of the flip-flops FF8 to FF15 corresponding to the address where the failure has occurred, and the memories FD8 to FD8 connected to the outputs of the flip-flops FF8 to FF15. Any of / FD15 / CS
Each of the memories FD8 to FD of the memory unit 1 is set to the “L” level.
Since “H” is always applied to the data D terminal of D15, “H” is applied to the memory corresponding to the address where the failure has occurred.
1 "is stored in the memory unit 1 as fail data.

The address output from the pattern generator is the same as the register FFAD1 or the register FFA of the second hold register 6 at the start of the storage of the fail data.
The data at that address is held during the fail data fetch operation.

The above operation is repeated even when the burst length changes, and it is possible to cope with a case where fail data having a longer burst length is transferred.

FIG. 4 is a timing chart showing the fail data fetch operation of the failure analysis memory of the semiconductor memory test apparatus of the present invention.

In the conventional fail data fetching method, the fail data storage period in the failure analysis memory is x1S
It was the same as the cycle of storing the fail data in the RAM. For this reason, when fail data of a high-speed burst memory is stored, a plurality of memories are interleaved and the number of banks (the number of memories) is increased at the same time in order to shorten the storage cycle.

However, in the present invention, the fail data storage cycle for the failure analysis memory and the fail data storage cycle for the x1 SRAM are different. That is, the storage cycle of the fail data in each x1 SRAM is the same as the conventional one, but the storage cycle of the failure data in the failure analysis memory is 16 times the conventional storage cycle of the fail data.
Double.

Therefore, fail data can be fetched at a higher speed than in the prior art, and there is no need to perform an interleave operation, so that the memory capacity can be reduced.

Accordingly, even when fail data of a burst memory such as a large-capacity RDRAM is taken in, it is not necessary to use a large number of expensive high-speed SRAMs. The mounting area is also reduced.

FIG. 5 shows the effect of the failure data fetching method of the failure analysis memory according to the present invention. In FIG. 5, 18M (2M × 9) bits RD
RDAM indicates the case where the fail data of the RAM is fetched.
The storage cycle required to capture the fail data is 2 ns,
Further, the data fetch cycle of the x1 SRAM is 32 ns.

As shown in FIG. 5, in the conventional fail data fetching method, x1 SRA having an access time of 32 ns is used.
To acquire data every 2 ns at M, 16 ways (3
(2 ns / 2 ns = 16). Here, the number of memories required to store the fail data of 18 M bits is 18 in a 1 M bit x1 SRAM. In order to prepare this for 16 ways, the number of x1 SRAMs required as a failure analysis memory is 18 × in total.
16 = 288.

On the other hand, in the fail data capturing method of the present invention, the fail data capturing cycle is 32 ns / 16 = 2.
ns, so there is no need to perform interleaving. In addition, since the capacity for one bit is 2M, a memory of 256 kw × 1 (the actual depth only needs to be up to 128 kW) is one memory.
You only have to use six. X1 SRAM required as a failure analysis memory to prepare the same number of bits as the memory under test
Is 16 × 9 = 144 in total.

Therefore, the failure analysis memory of the semiconductor memory test device of the present invention has a memory capacity of 1/8 of the conventional memory capacity.
And half the number of memories.

[0061]

Since the present invention is configured as described above, the following effects can be obtained.

A shift register for serially storing fail data in the serial data format outputted in the order of addresses of the memory under test and outputting the same as parallel data is stored in the failure analysis memory, and parallel data outputted from the shift register are simultaneously read and temporarily stored. A first hold register for holding a fail data corresponding to an address of a memory under test in each memory bit;
C that outputs an enable signal for transferring the parallel data held in the first hold register to the memory unit
By providing an S signal generating unit and a second hold register for holding address data corresponding to the fail data while transferring the fail data to the memory unit, the fail data is stored in one bit corresponding to each bit of the memory under test. Fail data can be transferred to the memory unit at a higher speed than in the conventional method of transferring data to the memory unit bit by bit, and there is no need to perform an interleaving operation, so that the memory capacity can be reduced.

Therefore, even when fail data of a burst memory such as a large-capacity RDRAM is taken in, it is not necessary to use many expensive high-speed SRAMs, so that the cost of parts for manufacturing a failure analysis memory is reduced, and failure analysis is performed. The mounting area of the memory does not increase.

[Brief description of the drawings]

FIG. 1 is a diagram showing a fail data fetch format of a failure analysis memory of a semiconductor memory test device of the present invention.

FIG. 2 is a circuit diagram illustrating a method of writing fail data to a failure analysis memory of the semiconductor memory test device of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a first / CS generation unit shown in FIG. 2;

FIG. 4 is a timing chart showing a fail data fetch operation of the failure analysis memory of the semiconductor memory test device of the present invention.

FIG. 5 is a diagram showing the effect of the fail data fetching method of the failure analysis memory of the semiconductor memory test device of the present invention.

FIG. 6 is a block diagram showing a configuration of a semiconductor memory test device.

FIG. 7 is a block diagram showing a configuration of a failure analysis memory shown in FIG. 6;

FIG. 8 is a block diagram showing a configuration of an RDRAM.

FIG. 9 is a circuit diagram showing a case where a plurality of RDRAMs are connected and used.

FIG. 10 is a format diagram showing a configuration of transfer data of the RDRAM.

11A and 11B are diagrams showing a method of capturing fail data in a failure analysis memory of a conventional semiconductor memory test device, wherein FIG. 11A is a circuit diagram and FIG. 11B is a diagram showing a storage format.

FIG. 12 is a diagram illustrating the configuration of an interleaved failure analysis memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory part 2 Shift register 3 1st hold register 4 1st / CS generation part 5 2nd / CS generation part 6 2nd hold register

Claims (1)

[Claims] In order to determine the quality of a memory under test,
In a semiconductor memory test device including a failure analysis memory for storing fail data that is failure information among test results of the memory under test, a serial data format output to the failure analysis memory in the order of addresses of the memory under test. A shift register that sequentially stores the fail data and outputs the data as parallel data; a first hold register that simultaneously reads and temporarily holds the parallel data output from the shift register; A memory section for holding corresponding fail data in each memory bit, a CS signal generating section for outputting an enable signal for transferring the parallel data held in the first hold register to the memory section, During the transfer of the fail data to the memory unit, A second holding register for holding the address data corresponding to the yl data, a semiconductor memory testing device characterized in that it comprises a.