JPH1069460A - Bus control device - Google Patents

Abstract

(57) [PROBLEMS] To optimally set an access cycle of a peripheral device according to a use condition when a central processing unit and peripheral devices connected thereto are integrated on one chip. SOLUTION: A central processing unit 1 includes a pseudo access circuit 5,
The counter 2 is accessed by accessing the peripheral devices 4, 6, 8 having the peripheral devices 7, 9, and the time until the pseudo access circuits 5, 7, 9 of the peripheral devices output data is counted by the clock 14 of the central processing unit. The measured values are set in the access cycle registers 10 to 12 provided for each peripheral device. Thereafter, when accessing the central processing unit 1 and each of the peripheral devices 4, 6, and 8, the access is performed in the access cycle set in the registers 10 to 12. This access cycle setting operation is performed immediately after reset release or immediately after the clock of the central processing unit is switched.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including a central processing unit (hereinafter referred to as a CPU), and more particularly, to an access from a CPU of a peripheral device connected to a CPU integrated on a single chip in the semiconductor integrated circuit. The present invention relates to a bus control device for determining a cycle.

[0002]

2. Description of the Related Art When a CPU and peripheral devices connected to the CPU are integrated on one chip, an access cycle from the CPU to the peripheral device has conventionally been handled by the following three methods. One is a method in which the number of access cycles is handled by software. Another method is to operate with handshake. The last one is a method of setting it fixed by hardware. In the method corresponding to software, the program is fixed and operated by a program (normally written in a read-only memory) mounted on a microcomputer. In this case, since the access cycle is set with a margin according to the normal specification, it is not possible to operate the integrated circuit at an optimum access cycle at the time of operation, and it is not possible to improve the performance in the application field where real-time performance is required . When operating by handshaking, it is necessary to add a circuit for handshaking to each peripheral device, which causes an increase in the area of the integrated circuit. When fixed in hardware, it is difficult to set the number of access cycles to the optimum value in the operating state as in the case of setting by software. Further, when the peripheral device is replaced, the bus control device must be redesigned, which increases the number of development steps.

[0003]

SUMMARY OF THE INVENTION At least a CPU and a C
In a semiconductor integrated circuit integrated on a single chip including a peripheral device connected to a PU by a bus, the processing capability may be controlled by an access cycle of a built-in CPU to a peripheral device connected by a bus. For example, in a built-in ROM, a high-speed read time may be longer than a CPU machine cycle. Normally, performance is not regulated if one cycle access is assumed, but if the machine cycle of the CPU is accelerated, the reading speed of the built-in ROM cannot be followed, and two or more cycles are required for access. It becomes like this. As described above, the performance has been improved by originally realizing it in one cycle. However, since there are circuits that can follow the high speed and circuits that cannot follow the speed, it is impossible to optimize the number of cycles according to the frequency. This is a factor that hinders the improvement of the processing capacity.

Accordingly, the present invention makes it possible to prevent the deterioration of the processing performance by automatically optimizing the access cycle of the built-in assets integrated on one chip according to the conditions such as the clock frequency to be used. It is an object of the present invention to provide a bus control device.

[0005]

According to one aspect of the present invention, there is provided a CPU, at least one peripheral device accessible from the CPU, a bus control device, and a clock for the CPU. In a semiconductor integrated circuit in which a counter device for counting clocks is integrated on one chip, the bus control device has an access cycle register that specifies an access cycle of the peripheral device, and the bus control device has an access cycle register when the CPU accesses the peripheral device. The peripheral device has a path for generating a pseudo-access using an address from the CPU, and generates a control signal at a timing corresponding to the data output of the peripheral device; Writing the count value of the counter device counted up by a clock to the access cycle register A bus control device and controls the access cycle of the peripheral device using the access cycle register.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit in which a CPU, at least one peripheral device accessible from the CPU, a bus control device, and a counter device for counting a clock of the CPU are integrated on one chip. In the above, the bus control device has an access cycle register that defines an access cycle of the peripheral device, and the CPU generates an access to the peripheral device immediately after releasing a reset state, and the peripheral device receives a signal from the CPU. The counter device having a path for generating a pseudo access using an address, generating a control signal at a timing corresponding to a data output of the peripheral device, and counting up with a clock of the CPU by the control signal. Is written to the access cycle register, and the access cycle Register a bus control device and controls the access cycle of the peripheral device using.

According to a third aspect of the present invention, there is provided a semiconductor integrated circuit in which a CPU, at least one peripheral device accessible from the CPU, a bus control device, and a counter device for counting the clock of the CPU are integrated on one chip. In the above, the bus control device has an access cycle register that defines an access cycle of the peripheral device, and the CPU is configured to immediately reset the at least one
A peripheral device having a path for generating a pseudo-access using an address from the CPU by generating an address which can be commonly accessed by more than one peripheral device, and a timing corresponding to a data output of the peripheral device; The control signal is generated, and the count value of the counter device, which is counted up by the clock of the CPU by the control signal, is written into the access cycle register, and the access cycle of the peripheral device is controlled using the access cycle register. A bus control device.

According to a fourth aspect of the present invention, there is provided a CPU, at least one or more peripheral devices connected to the CPU via a first bus, and at least one peripheral device connected to the CPU via a second bus.
In a semiconductor integrated circuit in which one or more peripheral devices, a bus control device that controls the first bus and the second bus, and a counter device that counts the clock of the CPU are integrated on one chip, the bus control device includes: An access cycle register that defines an access cycle of the peripheral device, wherein when the CPU accesses the peripheral device, the peripheral device has a path for generating a pseudo access using an address from the CPU; Generating a control signal at a timing corresponding to the data output of the peripheral device, writing the count value of the counter device, which is counted up by the clock of the CPU with the control signal, into the access cycle register, Controlling an access cycle of the peripheral device using an access cycle register; A bus control device according to claim.

According to a fifth aspect of the present invention, there is provided a CPU capable of switching an operating frequency during operation, at least one or more peripheral devices accessible from the CPU, a bus control device,
A counter device for counting the clock of the CPU
In a semiconductor integrated circuit integrated on a chip, the bus control device has an access cycle register that specifies an access cycle of the peripheral device, and initializes the counter immediately after a change in the operating frequency of the CPU.
Accesses the peripheral device, the peripheral device has a path for generating a pseudo access using an address from the CPU, and generates a control signal at a timing corresponding to the data output of the peripheral device. Writing the count value of the counter device, which is counted up by the CPU clock by the control signal, to the access cycle register, and controlling the access cycle of the peripheral device using the access cycle register. It is a control device.

With the above configuration, in a semiconductor integrated circuit in which a CPU and peripheral devices connected to the CPU via a bus are integrated on one chip, when the CPU accesses the peripheral device, an optimum access cycle corresponding to the access speed of the peripheral device is obtained. Can be automatically set, so that especially the real-time processing can be optimized.

[0011]

FIG. 1 is a block diagram showing a hardware configuration according to a first embodiment of the present invention. 1 is a CPU, 2 is a counter that counts the number of clocks using the clock of the CPU, 3 is a bus control device that controls a bus connected to the CPU, 4 is a first peripheral device, 6 is a second peripheral device, 8 is a third peripheral device, 10 is an access cycle register of the first peripheral device, 11 is an access cycle register of the second peripheral device, and 12 is an access cycle register of the third peripheral device. For example, FIG. 1 shows that the first peripheral device 4 is a ROM, the second peripheral device 6 is a RAM,
The third peripheral device 8 is an IO device, each of which is a CP.
This shows a case in which U1 is connected via a bus.

The CPU 1 controls each of the peripheral devices 4, 6, 8
, An address for generating a pseudo access is issued, and the peripheral devices 4, 6, 8 are accessed. On the other hand, the counter 2 is counted up by the clock 14 of the CPU 1. In the cycle in which the address is issued, the value of the counter is "0", but the count-up is performed in synchronization with one clock cycle. The value of this counter defines the access cycle of each peripheral device. Control signals 20, 21, and 22 generated by the pseudo accesses in the peripheral devices 4, 6, and 8 are sent to the access cycle registers 10, 11, and 12 of the peripheral devices, respectively, and are used as read clocks of the count value 23 of the counter 2 as read clocks. used. The control signal is added to the pseudo-access circuits 5, 7, 9 created by the peripheral devices 4, 6, 8 with the same circuit configuration as the access path from the normal CPU 1, so that the read signals are not originally used for read access. The control signal can be generated at the same timing as the data output. As a result, it is possible to define the optimum number of access cycles under use conditions for access from the CPU 1. The bus controller 3 generates a bus control signal 16 based on the values 17, 18, and 19 of the access cycle registers 10, 11, and 12 of each peripheral device, and transfers data between the CPU 1 and each of the peripheral devices 4, 6, and 8. Control is executed efficiently.

There are the following methods for accessing the peripheral devices. The first method is that when the address transferred from the CPU 1 is first applied to the first peripheral device 4 and the control signal 20 for the pseudo access of the first peripheral device 4 returns to the access cycle register 10. When the CPU 1 issues an address to the second peripheral device 6 and the control signal 21 for the pseudo access of the second peripheral device 6 returns to the access cycle register 11, the third peripheral device 8 Address to CP
When U1 issues and the control signal 22 for the pseudo access of the third peripheral device 8 returns to the access cycle register 12, the access cycle registers 10, 1
After the setting of 1, 12 is completed, it is possible to shift to the normal operation. In this manner, the pseudo access is generated individually for each peripheral device, and the access cycle register is sequentially set sequentially.

The second method is to define a common address space for pseudo-access to define an access cycle. In this case, each of the peripheral devices 4, 6, 8
Have an address space commonly accessed and are accessed simultaneously. FIG. 2 shows memory up of a peripheral device. Although the address space originally used by each of the peripheral devices 4, 6, and 8 is different, a certain address space 27 is used.
Are set so that they can be accessed simultaneously. CPU
1 to issue an address in the address space 27 which can access the peripheral devices 4, 6, 8 in common, and access is performed simultaneously. In each of the peripheral devices 4, 6, and 8, in response to the access, the output data is a signal that defines the timing of the pseudo access.

A third method describes a sequence for entering the above pseudo access cycle. The CPU 1 shifts from the reset state to the operating state when the reset signal is released, but generates an address for generating a pseudo access immediately after the reset is released. Each peripheral device outputs a control signal according to the access as shown in the figure, and sets an access cycle register. For example, in FIG. 3, when the control signal of the first peripheral device is output, the value of the counter is “2”, so “2” is set in the access cycle register 10. Similarly, in the example in the figure, the values of “3” and “4” are set in the access cycle registers of the second peripheral device and the third peripheral device, respectively. By doing so, the access cycle registers 10, 11, and 12 can be set in the initial setting stage after the reset state is released, and in the operating state, the CPU 1 sends the peripheral devices 4, 6, 8
Can be operated with the optimal number of cycles according to the use conditions, so that the processing capacity can be improved and the user needs to consider the number of access cycles to the peripheral devices 4, 6, 8 inside the integrated circuit. Because there is no, program development can be performed easily.

In the fourth method, a case where the clock frequency can be switched will be described. The case where the clock frequency of the CPU is changed in the operating state is seen in portable devices and the like,
When there is no input such as an interrupt, the operation is performed with a low-speed clock, and when performing some processing, switching to the high-speed clock is performed. This is an effective means for reducing power consumption in the operating state. FIG. 4 shows a sequence when the clock is switched from high speed to low speed. When the clock is switched, a clock switching control signal is output. Immediately after this, the counter 2 is initialized, the common address space 27 is accessed once, a pseudo access is generated, and the access cycle according to each clock frequency is defined in the same sequence as in the third embodiment. , The optimum access cycle according to the clock frequency can be automatically set.

[0017]

As described above, according to the present invention, the CPU
It is possible to automatically set the optimum number of accesses as the number of access cycles by the peripheral device accessed from the device according to the use conditions (temperature, voltage, etc.), thereby improving the processing performance. . Further, since the user does not need to consider the number of access cycles to the peripheral device inside the integrated circuit, the program can be easily developed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an access cycle determination device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of an address space map according to the present invention;

FIG. 3 is an operation timing diagram as an example of the present invention.

FIG. 4 is another example operation timing diagram of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Central processing unit 2 Counter 3 Bus control unit 4 First peripheral device 6 Second peripheral device 8 Third peripheral device 10 Access cycle register of first peripheral device 11 Access cycle register of second peripheral device 12 Second Third peripheral device access cycle register 5 First peripheral device pseudo access generation unit 7 Second peripheral device pseudo access generation unit 9 Third peripheral device pseudo access generation unit 20 First peripheral device pseudo access Control signal for pseudo-access of the second peripheral device 22 control signal for pseudo-access of the third peripheral device

Claims (5)

[Claims] 1. A semiconductor in which a central processing unit, at least one or more peripheral devices accessible from the central processing unit, a bus control unit, and a counter unit for counting a clock of the central processing unit are integrated on one chip. In the integrated circuit, the bus control device has an access cycle register that defines an access cycle of the peripheral device, and when the central processing unit generates an access to the peripheral device, the peripheral device is transmitted from the central processing device. Has a path for generating pseudo-access using the address of
A control signal is generated at a timing corresponding to a data output of the peripheral device, and a count value of the counter device, which is counted up by a clock of the central processing unit by the control signal, is written in the access cycle register, and the access cycle A bus control device for controlling an access cycle of the peripheral device using a register. 2. A semiconductor in which a central processing unit, at least one or more peripheral devices accessible from the central processing unit, a bus control unit, and a counter device for counting a clock of the central processing unit are integrated on one chip. In the integrated circuit, the bus control device has an access cycle register that defines an access cycle of the peripheral device. Immediately after releasing a reset state, the central processing unit accesses the peripheral device, and the peripheral device A path for generating a pseudo-access using an address from the central processing unit; generating a control signal at a timing corresponding to a data output of the peripheral device; Write the count value of the counter device counted up in the access cycle register A bus control device for controlling an access cycle of the peripheral device using the access cycle register. 3. A semiconductor in which a central processing unit, at least one peripheral device accessible from the central processing unit, a bus control unit, and a counter device for counting a clock of the central processing unit are integrated on one chip. In the integrated circuit, the bus control device has an access cycle register that specifies an access cycle of the peripheral device, and an address that the central processing unit can immediately access in common to the at least one peripheral device immediately after releasing a reset state. The peripheral device has a path for generating a pseudo access using an address from the central processing unit, and generates a control signal at a timing corresponding to the data output of the peripheral device, Count value of the counter device which is counted up by a clock of the central processing unit by a control signal A bus control device which writes the following into the access cycle register and controls an access cycle of the peripheral device using the access cycle register. 4. A central processing unit, at least one or more peripheral devices connected to the central processing unit by a first bus, and at least one or more peripheral devices connected to the central processing unit by a second bus. In a semiconductor integrated circuit in which a peripheral device, a bus control device that controls the first bus and the second bus, and a counter device that counts a clock of the central processing unit are integrated in one chip, the bus control device is An access cycle register for defining an access cycle of the peripheral device, wherein when the central processing unit accesses the peripheral device, the peripheral device generates a pseudo access using an address from the central processing unit A control signal is generated at a timing corresponding to the data output of the peripheral device, and the control signal is used to trigger the CPU of the central processing unit. A bus control device, wherein a count value of the counter device counted up by a lock is written in the access cycle register, and an access cycle of the peripheral device is controlled using the access cycle register. 5. A central processing unit capable of switching an operating frequency during operation, at least one or more peripheral devices accessible from the central processing unit, a bus control unit, and a clock of the central processing unit. In a semiconductor integrated circuit in which a counter device for counting is integrated on one chip,
The bus control device has an access cycle register that defines an access cycle of the peripheral device, initializes the counter device immediately after a change in the operating frequency of the central processing unit, and allows the central processing device to access the peripheral device. The peripheral device has a path for generating a pseudo-access using an address from the central processing unit, and generates a control signal at a timing corresponding to the data output of the peripheral device. A bus control device, wherein a count value of the counter device counted up by a clock of the central processing unit is written in the access cycle register, and an access cycle of the peripheral device is controlled using the access cycle register.