JPH1055272A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To rewrite a part of a mask program without changing an LSI. During operation, a built-in ROM is accessed by a program pointer, and its instruction code is read by a decoder.
To decode. The interrupt address detector 9 monitors the pointer 6 being executed, and notifies the interrupt controller 11 when the value written in the register 10 and the value of the pointer 6 match each other. Interrupt controller 11
Performs a process of loading the start address of the internal RAM 5 into the pointer 6, and thereafter the pointer 6 accesses the internal RAM 5 and replaces a part of the instruction code of the internal ROM 4 with the instruction code of the internal RAM 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for electronic equipment such as a digital cellular radio telephone system, and more particularly to a digital signal processing device.

[0002]

2. Description of the Related Art Conventionally, a digital signal processing device (hereinafter abbreviated as DSP) used in electronic equipment has a built-in ROM, which stores an instruction code in the built-in ROM, and a program pointer is stored in the built-in ROM. The instruction code is decoded by the decoder with reference to only the above, and the DSP is operated. Also, by writing the instruction code using a mask at the time of manufacturing the LSI, it is not necessary to write the instruction code after manufacturing.

[0003]

However, in the above-mentioned conventional DSP, when it is necessary to change even a part of the instruction code of the built-in ROM, all of the LSI manufacturing steps are performed.
There was a problem that we had to do it again.

An object of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a semiconductor device which can replace a part of a mask program without changing an LSI.

[0005]

According to the present invention, in order to achieve the above object, a part of an instruction code stored in a built-in ROM is replaced with an instruction code stored in a built-in RAM. Part of the mask program can be replaced without changing the LSI.

[0006]

According to the first aspect of the present invention, there is provided a program pointer which makes it possible to refer to an internal RAM as well as an internal ROM, and monitors the program pointer to store an instruction code of the internal ROM. Means for generating an interrupt for replacing with an instruction code of a RAM, wherein a part of the instruction code stored in the internal ROM is replaced with an instruction code stored in the internal RAM. Thereby, a part of the mask program can be replaced without changing the LSI.

According to a second aspect of the present invention, there is provided an internal ROM for storing an instruction code, an internal RAM for storing an instruction code to be replaced, a program pointer for sequentially indicating the address of the instruction code during operation, and a program pointer. A semiconductor device comprising: an interrupt address detecting unit that monitors the value of the above and generates an interrupt notification when the value matches a preset value; and an interrupt controller that receives the interrupt notification and stores the head address of the internal RAM in a program pointer. This is an apparatus, and by replacing a part of the instruction code stored in the internal ROM with the instruction code stored in the internal RAM, it is possible to replace a part of the mask program without changing the LSI.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration inside a DSP according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an operation unit which performs each operation of the DSP. Reference numeral 2 denotes a decoder, which is connected to the operation unit 1 and decodes an instruction code. An instruction register 3 temporarily stores an instruction code. Reference numeral 4 denotes a built-in ROM, which stores an instruction code. Reference numeral 5 denotes a built-in RAM, which stores a replacement instruction code. 6 is a program pointer, and D
During the SP operation, the addresses of the instruction codes are sequentially indicated. Reference numeral 7 denotes an internal bus, which is connected to the arithmetic unit 1, the program pointer 6, the interrupt register 10, the interrupt controller 11, and the external bus 8 to transmit and receive data necessary for the DSP operation. An external bus 8 is connected to the CPU 12, the external memory 13, the internal bus 7, the built-in RAM 5, and the like to transmit and receive data. Reference numeral 9 denotes an interrupt address detection unit which monitors the program pointer 6. An interrupt register 10 controls the interrupt address detection unit 9. An interrupt controller 11 controls the program pointer 6 and the like when an interrupt occurs. 12 is CP
U controls each unit in the apparatus. Reference numeral 13 denotes a memory referred to by the CPU 12. The replacement instruction code is stored in the built-in RAM 5 via the CPU 12 and the external bus 8 in advance.

Next, the operation of this embodiment will be described. During the DSP operation, the contents of the internal ROM 4 at the address indicated by the program pointer 6 are stored in the instruction register 3. The decoder 2 decodes the contents of the instruction register 3 and transmits the processing to the operation unit 1. The arithmetic unit 1 performs arithmetic processing on the decoded content. Interrupt register 1
When 0 is set, the interrupt address detector 9 operates. The interrupt address detector 9 monitors the program pointer 6, and notifies the interrupt controller 11 when the address set in the interrupt register 10 matches the address of the program pointer 6. Upon receiving this notification, the interrupt controller 11 generates an interrupt and stores the start address of the internal RAM 5 in the program pointer 6. As a result, the program pointer 6 starts to sequentially point to the address of the internal RAM 5. Built-in RAM5
After the instruction code for storing the return address of the internal ROM 4 in the program pointer 6 is set at the end of the replacement instruction code, the instruction code of the internal RAM 5 is executed, and then the return address of the internal ROM 4 is stored in the program pointer 6. Will be stored. Thereafter, the program pointer 6 points to the address of the internal ROM 4 as before.

As described above, according to the present embodiment, DS
Since the program pointer 6 in P can refer to the built-in RAM 5 similarly to the built-in ROM 4, and the interrupt address detecting unit 9 monitors the program pointer 6 to generate an interrupt, a part of the instruction code of the built-in ROM 4 Can be replaced with the instruction code of the built-in RAM 5.

[0011]

According to the present invention, as apparent from the above embodiment, a part of the instruction code stored in the built-in ROM is replaced by the instruction code stored in the built-in RAM. This has the effect that a part of the mask program can be replaced without making any changes.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration inside a DSP according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Operation part 2 Decoder 3 Instruction register 4 Built-in ROM 5 Built-in RAM 6 Program pointer 7 Internal bus 8 External bus 9 Interrupt address detection part 10 Interrupt register 11 Interrupt controller 12 CPU 13 Memory

Claims (2)

[Claims] 1. A program pointer which makes it possible to refer to an internal RAM similarly to an internal ROM, and means for monitoring the program pointer and generating an interrupt for replacing an instruction code of the internal ROM with an instruction code of the internal RAM. A semiconductor device comprising: 2. An internal ROM for storing an instruction code, an internal RAM for storing an instruction code to be replaced, a program pointer for sequentially pointing to the address of the instruction code during operation, and a value of a program pointer which is monitored in advance. A semiconductor device comprising: an interrupt address detection unit that generates an interrupt notification when the value matches the interrupted value; and an interrupt controller that receives the interrupt notification and stores the start address of the internal RAM in a program pointer.