JPH10242420A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) An object of the present invention is to provide a DRAM in which a memory cell portion and a peripheral circuit portion are mixedly mounted, in which a fine contact hole can be formed in a self-aligned manner with respect to a gate electrode. And a second insulated gate transistor capable of sufficiently reducing a parasitic resistance while suppressing a short channel effect.
The most important feature is that the insulated gate transistor can be integrated on the same substrate. For example, a cell region on a semiconductor substrate is provided.
1a has multiple MOs based on the minimum design rule.
An SFET 20A is formed, and each gate electrode 21 is formed.
Gate sidewalls 22A are formed on sidewall portions of A by sidewall insulating films 22a. Further, at least one MOSFET 20B is formed in the peripheral circuit region 11b, and a gate sidewall 22B is formed on sidewall portions of the gate electrode 21B by sidewall insulating films 22a and 22b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to, for example,
The present invention relates to a semiconductor device having a MIS structure in which a second insulated gate transistor is integrated on the same substrate and a method of manufacturing the same. In particular, a DRAM (Dynamic Random) in which a memory cell portion and a peripheral circuit portion are mixedly mounted. Access Me
mory).

[0002]

2. Description of the Related Art In general, miniaturization and high integration of an insulated gate transistor formed on a semiconductor substrate reduce the area occupied by the element, increase the current driving force of the element, and reduce the parasitic capacitance. This is useful for improving the performance of LSI.

[0003] At the research level, a prototype of a CMOS typically having a gate length of 0.1 μm or less has been successfully produced, and its high performance has actually been confirmed.

A serious obstacle to such a miniaturization technique is a short channel effect in which the absolute value of the threshold voltage decreases as the gate length decreases.

In order to prevent this, a so-called scaling law has been proposed. As the element is miniaturized accordingly, the impurity concentration in the substrate is increased, or the thickness of the insulating film or the source / drain region (impurity diffusion) is reduced. The junction depth of the layer (layer) must be reduced.

In particular, reducing the junction depth of the impurity diffusion layer is becoming increasingly important as a practical solution for suppressing the short channel effect.

On the other hand, for example, in order to reduce the parasitic resistance of the insulated gate transistor by using the salicide technique, it is necessary to increase the depth of the impurity diffusion layer at a distance from the channel to a certain degree or more.

This is because the formation of silicide on the source / drain region increases the junction leakage current between the impurity diffusion layer and the substrate by forming the impurity diffusion layer having a sufficient depth. We are trying to prevent it.

As a structure for this purpose, an extension structure has been proposed. First, in order to suppress the short channel effect, ion implantation for forming a shallow junction is performed to form a region called an extension.

After forming a side wall (gate side wall) on the side wall portion of the gate electrode, except for the gate side wall portion, a subsequent salicide process is taken into consideration.
Ion implantation for sufficiently forming a deep junction of the impurity diffusion layer is performed.

In this manner, a deep junction impurity diffusion layer is formed at a position away from the channel by the length of the gate side wall from the end of the extension region having the shallow junction.

That is, a gate side wall forming process is used for forming the above-mentioned extension structure. Conventionally, the gate side wall length is the same in all the elements constituting the LSI.

Therefore, for example, when a memory cell section and a peripheral circuit section for driving the memory cell section are mixedly mounted on one chip, a transistor having a small channel width used in the memory cell section and a high current driving force are required. It is becoming impossible to match the gate side wall length with a transistor having a large channel width used in a peripheral circuit section.

The reason is that a pattern reduced to the limit of the lithography technique is used in the memory cell portion,
This is because the design rules of the transistors in the peripheral circuit portion are close to isolated patterns.

For example, in a memory cell portion, when a contact hole is opened in a source / drain region, a SAC (Self-A) using an etching selectivity of a silicon nitride film and a silicon oxide film provided on a gate sidewall or the like is used.
It is common to use ligned contact technology.

However, if the gate sidewall length is not scaled according to the design rule (scaling rule), the gate sidewall cannot be formed. Therefore, S
It becomes difficult to open a contact hole by the AC technique, and it becomes impossible to form a memory cell portion.

As described above, for the transistor in the memory cell portion, it is necessary to reduce the gate side wall length in accordance with the scaling rule.

On the other hand, when the gate side wall length is scaled down, problems occur in the transistors in the peripheral circuit section. In particular, as described above, when silicide is formed in the impurity diffusion layer of a transistor, the junction depth of the impurity diffusion layer needs to be sufficiently large in order to reduce the junction leakage current caused by the silicide.

However, in this case, if the gate side wall length is small, the lateral diffusion of impurities below the gate side wall becomes large, which adversely affects the short channel effect.

In the transistor of the peripheral circuit section,
In order to increase the current driving force while suppressing the short channel effect, it is necessary to sufficiently increase the gate side wall length and sufficiently reduce the resistance of the extension region below the gate side wall.

[0021]

As described above, in the prior art, a transistor in which the gate side wall length needs to be reduced in accordance with the scaling rule and a transistor in which the gate side wall length is made sufficiently large and the extension under the gate side wall are provided. There is a drawback in that it is not possible to satisfy both requirements simultaneously with a transistor that requires a sufficiently low resistance in the region.

Accordingly, the present invention provides a first insulated gate transistor capable of forming a fine contact hole in a self-aligned manner with respect to a gate electrode, and a sufficient parasitic resistance while suppressing a short channel effect. The second that can be relaxed
It is an object of the present invention to provide a semiconductor device capable of integrating the above-mentioned insulated gate type transistors on the same substrate and achieving high density and high performance, and a method of manufacturing the same.

[0023]

In order to achieve the above object, in a semiconductor device according to the present invention, there is provided a MIS comprising at least first and second insulated gate transistors integrated on a semiconductor substrate. In a mold structure, the first
The sidewall insulating film formed on the side wall portion of the gate electrode in the second insulated gate transistor has a longer side wall length than the side wall insulating film formed on the side wall portion of the gate electrode in the insulated gate type transistor. It is configured to be formed.

In the semiconductor device of the present invention,
A semiconductor substrate divided into a memory cell region and a peripheral circuit region by a field region, and first semiconductors integrated in the memory cell region on the semiconductor substrate and formed of a first insulator on sidewall portions of the gate electrode, respectively. A plurality of first insulated gate transistors each having a sidewall insulating film formed thereon, and a first insulator and a second insulator provided in a peripheral circuit region on the semiconductor substrate, and on sidewall portions of the gate electrode. And at least one second insulated gate transistor formed with a second sidewall insulating film.

In the semiconductor device of the present invention,
A semiconductor substrate divided into a memory cell region and a peripheral circuit region by a field region, and first semiconductors integrated in the memory cell region on the semiconductor substrate and formed of a first insulator on sidewall portions of the gate electrode, respectively. A plurality of first insulated gate transistors each having a sidewall insulating film formed thereon, and a first insulator and a second insulator provided in a peripheral circuit region on the semiconductor substrate, and on sidewall portions of the gate electrode. A second sidewall insulating film composed of
And at least one second insulated gate transistor having a low resistance region selectively provided on the surface of the diffusion region.

In the semiconductor device according to the present invention,
A semiconductor substrate divided into a memory cell region and a peripheral circuit region by a field region, and first semiconductors integrated in the memory cell region on the semiconductor substrate and formed of a first insulator on sidewall portions of the gate electrode, respectively. A plurality of first insulated gate transistors each having a sidewall insulating film formed thereon, and a first insulator and a second insulator provided in a peripheral circuit region on the semiconductor substrate, and on sidewall portions of the gate electrode. A surface of the semiconductor substrate between at least one second insulated gate transistor having a second side wall insulating film formed of: and the first and second insulators And a third insulator provided so as to cover.

In the semiconductor device according to the present invention,
In the memory cell region on the semiconductor substrate, each has a gate electrode in which a side wall insulating film of a length d made of a first insulator is formed, and the maximum space between each gate electrode is 2 (d
+ X), a plurality of first
An insulated gate transistor, a gate electrode in which a side wall insulating film having a length d of a first insulator is formed in a peripheral circuit region on the semiconductor substrate, and the side wall insulating film on a surface of a diffusion region A plurality of second insulation layers each having a low resistance region provided at a position separated by the distance x from each other and arranged such that the maximum space between the gate electrodes is larger than 2 (d + x). And a gate transistor.

In the method of manufacturing a semiconductor device according to the present invention, each gate electrode of a plurality of first insulated gate transistors for forming a memory cell portion is provided in a memory cell region on a semiconductor substrate; Forming at least one gate electrode of at least one second insulated gate transistor for forming a peripheral circuit portion in a peripheral circuit region on the semiconductor substrate, and then forming each gate electrode in the first insulated gate transistor On the side wall of
Forming a first sidewall insulating film made of an insulating material;
Forming a second sidewall insulating film made of the first insulator and the second insulator on a sidewall portion of the gate electrode in the second insulated gate transistor.

Further, according to the method of manufacturing a semiconductor device of the present invention, a step of forming a field region and separating an element region on a semiconductor substrate into a memory cell region and a peripheral circuit region; A plurality of gate electrodes of a plurality of first insulated gate transistors for forming a memory cell portion, and a gate of at least one second insulated gate transistor for forming a peripheral circuit portion in the peripheral circuit region Forming each of the electrodes;
Depositing a first insulator over the entire surface of the semiconductor substrate, selectively removing the first insulator, and forming a sidewall portion of each gate electrode in the first insulated gate transistor; Forming a first side wall insulating film on each side wall portion of the gate electrode in the insulated gate type transistor, depositing a second insulator over the entire surface of the semiconductor substrate, And selectively forming a second side wall insulating film on a side wall portion of the gate electrode in the second insulated gate transistor.

According to the semiconductor device and the method of manufacturing the same of the present invention, the side wall insulating film of the gate electrode in the first insulated gate transistor is scaled down in accordance with the scaling rule while the gate electrode in the second insulated gate transistor is scaled down. Can be made sufficiently large. As a result, a transistor that requires the sidewall insulating film length to be reduced in accordance with the scaling rule, and a transistor that requires a sufficiently large sidewall insulating film length and a sufficiently small resistance in the extension region below the sidewall insulating film. It is possible to satisfy both requirements simultaneously.

Further, according to the present invention, by defining the space between the gate electrodes of the first insulated gate transistor and the second insulated gate transistor, the surface of the diffusion region can be selectively formed without using a lithography process. It is possible to form a patterned low resistance region.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 schematically shows a semiconductor device according to a first embodiment of the present invention, taking as an example a DRAM in which a memory cell portion and its peripheral circuit portion are mounted on the same chip. .

This DRAM is, for example, a semiconductor substrate 1
1 on which first and second insulated gate transistors (MO
(SFET) 20A, 20B.

The gate side wall (first side wall insulating film) 22A formed on the side wall of the gate electrode 21A in the MOSFET 20A is larger than the MOSFET side wall.
The gate side wall (second side wall insulating film) 22B formed on the side wall portion of the gate electrode 21B in 20B is configured to have a longer side wall length.

That is, in the semiconductor substrate 11, an element isolation region (field region) 12 is selectively formed on the surface, and a memory cell portion forming region (cell region) 11a and a peripheral circuit portion forming region (peripheral circuit region) are formed. 11b).

For example, a plurality of MOSFETs 20A are provided in the cell region 11a. Each MOS
The FET 20A has a gate electrode 21A provided on the semiconductor substrate 11 via a gate insulating film 23A.

A shallow junction extension region (diffusion region) 24A serving as a source / drain region is provided on the surface of the semiconductor substrate 11 between the respective gate electrodes 21A.

The extension region 24A of a part (or all) of the MOSFET 20A includes:
The extension structure is realized by partially forming the impurity diffusion region 25A having a deep junction.

On each gate electrode 21A, a mask material for etching the gate electrode and a SAC (to be described later) are formed.
In the (Self-Aligned Contact) step, a silicon nitride film 26A is provided as a cap material at the time of opening a contact to a source / drain region.

The side walls of the gate electrode 21A in each MOSFET 20A are provided with the gate side walls 22A by a side wall insulating film 22a made of, for example, a silicon nitride film (first insulator).

In this case, each of the MOSFETs 20A is designed based on the minimum design rule, and both the gate length and the gate width are reduced.

The MOSFET 20A formed at the outermost periphery of the cell region 11a among the MOSFETs 20A.
The gate electrodes 21A 'of A are electrically independent dummy gate electrode patterns.

By providing the dummy gate electrode pattern, the SAC step can be performed by using the original outermost MOSFET.
It can be applied to 20A.

On the other hand, in the peripheral circuit region 11b, for example, one MOSFET 20B is provided. This MOSFET 20B has a gate electrode 21B provided on the semiconductor substrate 11 via a gate insulating film 23B.

A shallow junction extension region 24B serving as a source / drain region is provided on the surface of the semiconductor substrate 11 between the gate electrode 21B and the element isolation region 12.

At each end of the extension region 24B, a deep junction impurity diffusion region 25B is partially formed to realize an extension structure.

The impurity diffusion region 25B of the MOSFET 20B is formed such that its junction depth is sufficiently larger than that of the impurity diffusion region 25A of the MOSFET 20A.

On the gate electrode 21B, a mask material at the time of etching the gate electrode and a SAC process are used.
A silicon nitride film 26B is provided as a cap material at the time of contact opening to the source / drain regions.

The side wall of the gate electrode 21B in the MOSFET 20B is provided with a gate side wall 22 having a longer side wall than the gate side wall 22A of the MOSFET 20A.
B is formed.

Gate sidewall 22B of MOSFET 20B
Are substances having an etching selectivity to each other, for example,
It is composed of a side wall insulating film 22a made of a silicon nitride film and a side wall insulating film 22b made of a silicon oxide film (second insulator).

The MOSFETs 20A and 20B
Are formed on the semiconductor substrate 11, each gate electrode 21A (including a dummy gate electrode 21A '), 21A
An interlayer insulating film 31 is deposited so as to cover B.

The surface of the interlayer insulating film 31 is formed by CMP (Ch
It has been flattened beforehand by emical mechanical polishing) technology.

In the interlayer insulating film 31, contact holes 32A and 32B are selectively formed. Of the contact holes 32A and 32B, the cell region 11a
The contact hole 32A provided in the gate electrode 21A of the MOSFET 20A is formed by the SAC technique.
The holes are opened in a self-aligned manner.

By implanting impurity ions through the contact holes 32A, the deep junction impurity diffusion regions 25A are formed on the surface of the semiconductor substrate 11 corresponding to the opening positions. Is performed.

The contact hole 32B provided in the peripheral circuit region 11b is formed, for example, by the MOSF
It is formed on the source / drain region of the ET 20B with a sufficient alignment margin (alignment margin).

Then, each of the contact holes 32A, 32A,
32B, wiring contact portions (diffusion layer contact portions) 33 connected to the source / drain regions of the MOSFETs 20A and 20B are formed, respectively.
Are integrated with the memory cell section and the peripheral circuit section.

According to the DRAM having such a configuration, in the MOSFET 20A in the memory cell portion, the side wall length of the gate side wall 22A can be scaled down according to the scaling rule.

At the same time, the MOSFET 20B in the peripheral circuit section
In this case, the side wall length of the gate side wall 22B can be sufficiently increased.

Therefore, in the memory cell portion, a fine contact hole 32A can be opened in a self-aligned manner with respect to the gate electrode 21A, while in the peripheral circuit portion, a deep contact hole necessary for forming silicide and suppressing a short channel effect is formed. Source / drain regions having a junction structure can be easily formed.

As a result, it is possible to further improve the device performance based on the scaling rule, which is approaching the limit.

FIGS. 2 to 6 schematically show a main part of a process for manufacturing the above-described DRAM.

First, as shown in FIG.
For example, STI (Shallow Trench Isolati
on) (or the LOCOS method) to form the element isolation regions 12 respectively.

Then, after a gate electrode material is deposited on the semiconductor substrate 11 via a substance to be the gate insulating films 23A and 23B, etching is performed using the silicon nitride films 26A and 26B as a mask, and the gate electrode 21A ( (Including the dummy gate electrodes 21A ') and 21B.

In this case, each MO is stored in the cell region 11a.
The gate electrode 21A and the dummy gate electrode 21A 'of the SFET 20A are formed by, for example, reducing both the gate length and the gate width to about 0.1 μm.

In the peripheral circuit region 11b, a MOS
The gate electrode 21B of the FET 20B is formed, for example, with a gate length of about 0.1 μm and a gate width of about 10 μm to 20 μm in order to obtain a large current.

Next, as shown in FIG. 3, ion implantation for forming the extension regions 24A and 24B is performed.

In an n-type MOSFET, As is 15 ke
5 × 10 ¹⁴ cm ^{-2 in} V, B in p-type MOSFET
F ₂ ions may be implanted at about 10 × 10 ¹⁴ cm ⁻² at 10 keV. In some cases, a step of forming a shallow junction by performing pre-amorphization using Si or Ge may be used.

Under this condition, the sheet resistance becomes several times higher than that of the impurity diffusion layer serving as the source / drain region in a normal transistor. However, since the distance between adjacent transistors is small in the inside of the memory cell portion or the like, there is no significant problem.

The extension areas 24A and 24B
Is formed, a silicon nitride film is deposited and
Etching back is performed by an E (Reactive Ion Etching) process.

Thus, the side walls of the gate electrodes 21A and 21A 'of the MOSFET 20A are respectively
A gate side wall 22A having a scaled down gate side wall length of about 50 nm or less is formed by the side wall insulating film 22a.

At the same time, a sidewall insulating film 22a having a gate sidewall length of about 50 nm is formed on the sidewall of the gate electrode 21B of the MOSFET 20B.

Next, as shown in FIG. 4, for example, a silicon oxide film-based TEOS (Tetra Ethoxy Silane) having a practical etching selectivity with respect to the silicon nitride film for forming the side wall insulating film 22a. 3.) Deposit the film 41.

Next, as shown in FIG. 5, the TEOS film 41 is etched back by an RIE process while leaving the side wall.

Then, in the MOSFET 20B, the side wall insulating film 22b is formed further outside the side wall insulating film 22a, and the gate side wall 22B by the side wall insulating films 22a and 22b is formed on the side wall of the gate electrode 21B. .

On the other hand, in the MOSFET 20A, since the space between the gate electrodes 21A and 21A 'is narrow, the TE
The side wall insulating film 22b made of the OS film 41 is not formed.

That is, in this case, the side wall insulating films 22b are formed on the outer peripheral portions of the dummy gate electrodes 21A ', respectively, and the TEOS between the gate electrodes 21A and 21A' is formed.
The film 41 is not etched, and the TEOS film 41 remains.

Thereafter, impurity diffusion region 25B having a deep junction is formed.
Is performed (not shown) for forming a mask, and ion implantation is performed.

In an n-type MOSFET, As is set to 50 ke
About 3 × 10 ¹⁵ cm ^{-2 in} V, B in p-type MOSFET
F ₂ ions may be implanted at 35 keV at about 3 × 10 ¹⁵ cm ⁻² .

As a result, each of the extension regions 24B of the MOSFET 20B is separated from the gate electrode 21B by the length of the gate side wall 22B (that is, the side wall insulating film 2 is farther than the gate side wall 22A).
An impurity diffusion region 25B having a deep junction is formed at a position separated by the length of 2b), thereby reducing the contact resistance.

Next, as shown in FIG.
For example, a silicon oxide film-based substance which becomes 1 is deposited on the entire surface, and its surface is flattened by a CMP process.

As the interlayer insulating film 31, it is important to use a material having a practical etching selectivity with respect to the silicon nitride film for forming the sidewall insulating film 22a.

Then, by etching the interlayer insulating film 31 in accordance with the resist pattern 42 by the RIE process, the contact hole 32A connected to the source / drain region of the MOSFET 20A and the MOSFE
A contact hole 32B connected to the source / drain region of T20B is opened.

In this case, the TEOS film 41 remaining between the gate electrodes 21A and 21A 'of the MOSFET 20A is removed together with the interlayer insulating film 31, but the sidewall insulating film 22a is not removed.

As a result, the SAC process can be applied to MOSFET 20A, so that contact hole 3 is self-aligned with gate electrode 21A.
2A can be opened.

Further, the outermost peripheral gate electrode 21A 'of the MOSFET 20A has a dummy gate electrode pattern. Therefore, by performing the SAC process using the dummy gate electrode 21A ', it is possible to prevent the contact hole 32A from being formed on the element isolation region 12 with displacement.

Therefore, it is possible to eliminate the problem that the element isolation region 12 is over-etched and the junction leakage current increases.

Note that the MOSFET 20B has an S
Even without performing the AC step, the contact hole 32B can be formed with a sufficient misalignment margin between the gate electrode 21B and the element isolation region 12.

Further, after removing the resist pattern 42, masking (not shown) for forming the impurity diffusion region 25A having a deep junction is performed, and ion implantation is performed through the contact hole 32A. Then, RTA (Ra) for activating the ion-implanted impurities is performed.
pid Thermal Annealing).

As a result, the extension area 24A
The impurity diffusion of a deep junction at a position separated from the gate electrodes 21A and 21A 'by the length of the gate side wall 22A (that is, a position separated by the length of the side wall insulating film 22a). The region 25A is formed to reduce the contact resistance.

In this case, the ion implantation conditions are changed so that the junction depth of the formed impurity diffusion region 25A is smaller than the junction depth of the impurity diffusion region 25B in the MOSFET 20B.

In particular, when the element isolation by the STI method described above is employed, damage due to ion implantation is reduced for the purpose of suppressing crystal defects in a cell region 11a such as a memory cell having a small element isolation width. It is necessary to do it.

As described above, without deteriorating the performance of the MOSFET 20B, the MO, such as the dose and the acceleration energy, can be reduced.
Only the conditions for forming the impurity diffusion region 25A in the SFET 20A can be arbitrarily changed.

Thereafter, each contact hole 32A, 32
A conductive wiring material is deposited on the interlayer insulating film 31 so as to fill B. Then, the wiring material is patterned to form the MOSFETs 20A and 20B.
By forming the wiring contact portions 33 connected to the source / drain regions of the DRAM, the memory cell portion and the peripheral circuit portion of the DRAM shown in FIG. 1 are realized.

In the first embodiment, the source of MOSFET 20B in the peripheral circuit section is simply
Although the case where the extension structure is employed in the drain region has been described as an example, the present invention is not limited to this, and it is also possible to employ a salicide process to reduce the parasitic resistance.

FIG. 7 schematically shows a main part of a manufacturing process of the DRAM according to the second embodiment of the present invention.

In this case, the D according to the first embodiment described above
As in the manufacturing process of the RAM, first, the MOSFET 2
After performing a process up to the step of forming a deep junction impurity diffusion region 25B outside the extension region 24B serving as the source / drain region of the substrate 0B (see FIG. 5).
A refractory metal (for example, a Ti film) 51 for a salicide process is deposited on the entire surface by a sputtering method.

Then, RTA is performed and MOSFET2
The silicide layer 52 is formed only on the surface of the source / drain region 0B (see FIG. 7A).

At this time, unreacted Ti is dissolved by using a mixed solution of sulfuric acid and hydrogen peroxide solution, and between the gate electrodes 21A and 21A 'for the cell region 11a, and the gate electrode for the peripheral circuit region 11b. A short circuit between 21B and the silicide layer 52 on the surface of the source / drain region is prevented.

As a result, the silicide layer 52 is formed between the position separated from the gate electrode 21B by the length of the gate side wall 22B and each element isolation region 12.

That is, the sidewall insulating films 22a and 22b on the surface of the source / drain region of the MOSFET 20B
The silicide layer 52 is formed at a position sufficiently distant from the gate electrode 21B by the length of the gate electrode 21B.

Next, for example, a silicon oxide film-based substance to be an interlayer insulating film 31 is deposited on the entire surface, and its surface is flattened by a CMP process.

Then, by etching the interlayer insulating film 31 in accordance with the resist pattern 42 by the RIE process, the contact hole 32A connected to the source / drain region of the MOSFET 20A and the MOSFE
A contact hole 32B connected to the silicide layer 52 on the source / drain region of T20B is opened.

Further, after removing the resist pattern 42, masking (not shown) for forming the impurity diffusion region 25A having a deep junction is performed, and ion implantation is performed through the contact hole 32A. Then, RTA for activating the ion-implanted impurities and for phase transition of the silicide layer 52 is performed.

Thus, the extension area 24A
Are located at positions away from the gate electrodes 21A and 21A 'by the length of the gate side wall 22A.
The impurity diffusion region 25A, which is shallower than the junction depth of the impurity diffusion region 25B in the OSFET 20B but is deeper than the extension region 24A, is formed to lower the contact resistance (see FIG. 7B).

Thereafter, each contact hole 32A, 32
A conductive wiring material is deposited on the interlayer insulating film 31 so as to fill B. Then, by patterning the wiring material to form the wiring contact portions 33, respectively, a memory cell portion and a peripheral circuit portion of the DRAM configured to reduce the parasitic resistance by the salicide process are realized. (See FIG. 7 (c)).

According to such a configuration, substantially the same effect as that of the DRAM according to the above-described first embodiment can be expected, and the current driving capability can be enhanced while preventing a short channel effect in the MOSFET 20B in the peripheral circuit portion. In some cases, the silicide layer 52 can be selectively formed only in the source / drain regions of the MOSFET 20B after the length of the gate side wall 22B is sufficiently increased.

Thus, the junction depth of the source / drain region can be made sufficiently deep, and the resistance of impurity diffusion region 25B outside gate side wall 22B can be made sufficiently small.

Therefore, the junction leak current caused by the formation of the silicide layer 52 can be easily reduced in the peripheral circuit portion while the junction transistor in the cell portion is kept small.

In addition, since the silicide layer 52 can be selectively formed only on the impurity diffusion region 25B exposed after the formation of the sidewall insulating film 22b, it is necessary to pattern the silicide layer which has been conventionally required. Lithography step can be omitted.

The wiring contact portion 33 of the MOSFET 20A is not limited to the case where the wiring contact portion is integrally formed using a wiring material. For example, a portion of the wiring contact portion may be made of polysilicon doped with an impurity such as phosphorus (P) or the like. It is also possible to easily use a metal such as tungsten (W).

FIG. 8 schematically shows a main part of a manufacturing process of the DRAM according to the third embodiment of the present invention.

In this case, the D according to the first embodiment described above
As in the manufacturing process of the RAM, first, the MOSFET 2
After the step of depositing the TEOS film 41 for forming the side wall insulating film 22b on the side wall of the gate electrode 21B at 0B (see FIG. 4), the SAC step
A contact hole 61 connected to the source / drain region of the MOSFET 20A is opened.

If necessary, masking (not shown) for forming the impurity diffusion region 25A having a deep junction is performed.
Perform ion implantation.

Further, a contact portion 62 is formed by burying a conductive material such as polysilicon or W heavily doped with P in the contact hole 61 thus opened (see FIG. 8A).

Next, by the RIE process, the TEOS
The film 41 is etched back while leaving the side wall.

As a result, the side wall insulating films 22b are formed outside the side wall insulating films 22a of the gate electrodes 21B in the MOSFET 20B, respectively.
Only on the side wall portion B, a gate side wall 22B is formed by the side wall insulating films 22a and 22b.

In the MOSFET 20A, a sidewall insulating film 22b is formed also on the outer peripheral portion of the dummy gate electrode 21A 'and on the sidewall portion of the contact portion 62 in which a conductive material is embedded in the contact hole 61. However, the TE between the gate electrodes 21A and 21A 'is
The OS film 41 is left without being etched.

Thereafter, impurity diffusion region 25B having a deep junction is formed.
Is performed (not shown) for forming a mask, and ion implantation is performed.

Thereby, impurity diffusion regions 25B having a deep junction are formed at positions apart from gate electrode 21B by the length of gate side wall 22B with respect to extension region 24B of MOSFET 20B, respectively. Low resistance is achieved.

Further, after forming an impurity diffusion region 25B having a deep junction by ion implantation outside the extension region 24B of the MOSFET 20B, a high melting point metal (not shown) for a salicide process is deposited on the entire surface by a sputtering method. Let it.

Then, RTA is performed, and MOSFET2
Silicide layers 52 are formed on the surface of the source / drain region 0B and the surface of the contact portion 62 in which a conductive material is embedded in the contact hole 61, respectively (see FIG. 8B).

Next, after the unreacted high-melting-point metal is dissolved and removed using a mixed solution of sulfuric acid and hydrogen peroxide solution, an interlayer insulating film 31, for example, a silicon oxide film-based substance is deposited on the entire surface. Then, the surface is flattened by a CMP process.

Then, the MOSFET is formed by the RIE process.
A contact hole 32A connected to the silicide layer 52 on the surface of the contact portion 62 at 20A;
A contact hole 32B connected to the silicide layer 52 on the source / drain region of the OSFET 20B is opened.

The contact holes 32A, 32B
A wiring material having conductivity is deposited on the interlayer insulating film 31 so as to fill the inside. Then, by patterning the wiring material to form the wiring contact portions 33, respectively, it is possible to not only reduce the parasitic resistance by the salicide process but also to form the MOSFE.
The memory cell portion and its peripheral circuit portion of the DRAM configured to suppress the contact resistance of T20A are also reduced (see FIG. 8C).

According to such a configuration, substantially the same effects as those of the DRAM according to the second embodiment can be expected, and a part of the wiring contact portion 33 of the MOSFET 20A in the memory cell portion can be reduced in resistance. Since polysilicon or the like is used, the contact resistance of the memory cell portion can be formed to be lower.

In addition, for the MOSFET 20A,
The contact resistance can be reduced without forming the impurity diffusion region 25A having a deep junction with the extension region 24A. Therefore, ion implantation for forming a deep junction between the source / drain regions is performed at least by M
It only needs to be performed once for the OSFET 20B.

In each of the MOSFETs 20A and 20B, the respective contact holes 32A and 32B
Can be opened by using the silicide layer 52 as a barrier metal.

In any case, since the source / drain regions in MOSFET 20A are not themselves silicided, it is possible to keep the junction leak current small, which is particularly suitable for integration of memory elements.

The MOSFET 20A in the memory cell portion
In the above, the contact holes 32A can be formed in the gate electrodes 21A and 21A 'in a self-aligned manner.

FIG. 9 schematically shows a main part of a manufacturing process of the DRAM according to the fourth embodiment of the present invention.

In this case, the D according to the first embodiment described above
As with the RAM manufacturing process,
After the steps up to the step of forming the side wall insulating film 22a are performed on each of 20A and 20B (see FIG. 3), a silicon nitride film (third insulator) 71 is deposited on the entire surface.

The silicon nitride film 71 has such a thickness that it is not removed by the SAC process while taking into consideration the etching selectivity with the interlayer insulating film 31, and is used for forming the sidewall insulating film 22a. It is formed sufficiently thinner than a silicon nitride film.

After depositing the silicon nitride film 71,
A TEOS film 41 for forming the sidewall insulating film 22b is deposited on the entire surface (see FIG. 9A).

Next, by the RIE step, the TEOS
The film 41 is etched back while leaving the side wall (FIG. 9B)
reference).

In this case, the MOSFET 20B is etched by etching so that the silicon nitride film 71 remains.
Then, a sidewall insulating film 22b is formed outside the sidewall insulating film 22a via a thin silicon nitride film 71, and a gate sidewall 22B for the gate electrode 21B is formed.

In the MOSFET 20A, the side wall insulating film 22b is also formed on the outer peripheral side wall of the dummy gate electrode 21A '.
The TEOS film 41 in between remains without being etched.

Thereafter, impurity diffusion region 25B having a deep junction is formed.
Is performed (not shown) for forming a silicon nitride film, and ion implantation is performed through the silicon nitride film 71.

Thus, a deep junction impurity diffusion region 25B is formed at a position away from the gate electrode 21B by the length of the gate side wall 22B with respect to the extension region 24B of the MOSFET 20B. Low resistance is achieved.

Next, for example, a silicon oxide film-based material to be an interlayer insulating film 31 is deposited on the entire surface, and its surface is flattened by a CMP process.

Then, the MOSFET is formed by the RIE process.
A contact hole 32A connected to the source / drain region of 20A and a contact hole 32B connected to the source / drain region of the MOSFET 20B are opened.

In this case, in MOSFET 20A, interlayer insulating film 31 and TEOS film 41 are selectively etched to form, for example, gate electrodes 21A,
Contact holes 32A are formed in a self-aligned manner with respect to 21A 'and element isolation region 12.

The silicon nitride film 71 remaining in the contact holes 32A and 32B is removed by, for example, wet etching using hot phosphoric acid or dry etching.

In the case of wet etching using hot phosphoric acid, the silicon oxide film is hardly etched, so that only the thin silicon nitride film 71 can be removed.

As a result, with respect to the element isolation region 12,
Even when the contact holes 32A are formed in a self-aligned manner, it is possible to prevent the element isolation region 12 from being excessively etched and increase the junction leak current.

Thereafter, each contact hole 32A, 32
A conductive wiring material is deposited on the interlayer insulating film 31 so as to fill B. Then, the wiring material is patterned to form the MOSFETs 20A and 20B.
Forming the wiring contact portions 33 connected to the source / drain regions of the gate electrodes 21A and 21A, respectively.
The memory cell portion and its peripheral circuit portion of the DRAM configured so that the contact hole 32A can be opened in a self-alignment manner for both A 'and the element isolation region 12 are realized (FIG. 9). (C)).

According to such a structure, substantially the same effects as those of the DRAM according to the first embodiment can be expected, and the gate electrodes 21A, 21A 'and the element isolation region can be formed without increasing the junction leakage current. 12, the contact hole 32A can be opened in a self-aligned manner.

In the DRAM according to the fourth embodiment, the outermost peripheral gate electrode 21A 'of the memory cell portion does not necessarily need to be an electrically independent dummy gate electrode pattern, but is electrically active. Even if the gate electrode 21A is made simple, the element isolation region 12 is not cut off,
It is possible to suppress an increase in junction leak current due to the opening of the contact hole 32A.

Next, the M in the peripheral circuit portion of the DRAM is
Another method when a silicide layer is formed on the source / drain region of the OSFET 20B will be described.

FIG. 10 shows a schematic configuration of a DRAM according to the fifth embodiment of the present invention. 2A is a plan view of a main part showing a layout pattern of the DRAM, and FIG. 2B is a cross-sectional view of the main part.

This DRAM is, for example, a semiconductor substrate 1
1, a plurality of first and second MOSFETs 20 respectively.
A and 20B have a MIS structure.

The MOSF constituting the memory cell portion
Except for the ET 20A, a part (or all) of the peripheral circuit portion is configured such that a silicide layer 52 having a lower resistance than that is provided on the surface of the source / drain region 24B in the MOSFET 20B. .

Hereinafter, the manufacturing process of the DRAM having the above configuration will be briefly described.

First, each gate electrode 21A of the MOSFET 20A is formed in the cell region 11a on the semiconductor substrate 11 separated by the element isolation region 12 via the gate insulating film 23A. In addition, the peripheral circuit area 11
b through the gate insulating film 23B.
The respective gate electrodes 21B of the SFET 20B are formed.

Note that a gate electrode 21B 'is also formed on the element isolation region 12 without the gate insulating film 23B.

Each of these gate electrodes 21A, 21B, 21
B 'is the silicon nitride film 26A or silicon nitride film 2
6B are formed as mask materials at the time of gate electrode etching.

Thereafter, an impurity is implanted into the surface of the semiconductor substrate 11 to form a source / drain region 24A of the MOSFET 20A and a source / drain region 24B of the MOSFET 20B.

Next, a silicon nitride film is deposited on the entire surface, and is etched back, so that each MOS
A sidewall insulating film 22a to be a gate sidewall 22A is formed on a sidewall portion of the gate electrode 21A in the FET 20A.

At the same time, a side wall insulating film 22a to be a part of the gate side wall 22B is formed on the side wall portions of the gate electrodes 21B and 21B 'in each MOSFET 20B.

Further, after the TEOS film 41 is deposited on the entire surface, it is etched back by the RIE method to fill the space between the gate electrodes 21A with the TEOS film 41, and to form a sidewall insulating film only on the side wall of the gate electrode 21B. 22b is formed, and a gate sidewall 22B is formed by the sidewall insulating film 22b and the sidewall insulating film 22a.

Next, a high melting point metal (for example, a Ti film or a TiN film) for a salicide process is deposited on the entire surface by a sputtering method or a CVD method, and then RTA is performed.
Is performed, a silicide layer 52 having a lower resistance than the source / drain region 24B is formed on the surface of the source / drain region 24B in at least a part of the MOSFET 20B.

After removing the excessive high melting point metal, a first interlayer insulating film 31a is deposited on the entire surface of the semiconductor substrate 11, and the surface is flattened by the CMP technique.

Then, the first interlayer insulating film 31a is
By the SAC technology, for example, the MOSFET 20A
A contact hole 32A connected to the source / drain region 24A is opened in one of the gate electrodes 21A in a self-alignment manner.

In the first interlayer insulating film 31a, for example, the contact hole 3 connected to the silicide layer 52 is formed with respect to the silicide layer 52 formed on the surface of the source / drain region 24B of the MOSFET 20B.
2B is opened with a sufficient alignment margin (alignment deviation margin).

The contact hole 32B 'is formed on the gate electrode 21B' provided on the element isolation region 12.
Of the silicon nitride film 26B on the surface thereof. For example, after opening a contact hole 32B 'for the first interlayer insulating film 31a, the silicon nitride film 26B remaining in the contact hole 32B' may be removed by hot phosphoric acid or the like.

Then, each of the contact holes 32A,
The wiring material is embedded in each of 32B and 32B ',
A bit line contact portion (wiring contact portion) 33A connected to the source / drain region 24A in the MOSFET 20A, and a diffusion layer contact portion (wiring contact portion) 33 connected to the silicide layer 52 on the surface of the source / drain region 24B in the MOSFET 20B.
B and an on-gate contact portion 33B 'connected to the surface of the gate electrode 21B' are formed.

Thereafter, on the first interlayer insulating film 31a in the cell region 11a, the bit line 34 to which the bit line contact portion 33A is connected is formed on the first interlayer insulating film 31a in the peripheral circuit region 11b. On top, the diffusion layer contact portion 33
B is connected to the on-gate contact portion 33B '.
The wiring 35 of the layer is formed respectively.

After the second interlayer insulating film 31b is deposited on the entire surface, the diffusion connected to the source / drain region 24A of the MOSFET 20A is formed in the first and second interlayer insulating films 31a and 31b in the cell region 11a. Layer contact part 3
6 is formed.

Then, a plurality of storage electrodes 37 connected to the diffusion layer contact portion 36 are formed on the second interlayer insulating film 31b in the cell region 11a, and a capacitor insulating film (not shown) is formed. Through the plate electrode 3
8 is formed.

Thereafter, an insulating film 39 is deposited on the entire surface to form a memory cell portion and a peripheral circuit portion of the DRAM.

In the memory cell portion and the peripheral circuit portion of the DRAM having the above-described configuration, for example, the interval Sa between the gate electrodes 21A in the memory cell portion is Sa <2 (x + d).
And each gate electrode 21B of the peripheral circuit portion.
Each is designed so that the interval Sb between them satisfies Sb> 2 (x + d).

Here, d is the side wall length of the side wall insulating film 22a,
x is the side wall length of the side wall insulating film 22b.

In practice, in consideration of the size (C) of the diffusion layer contact portion 33B in the peripheral circuit portion, the interval Sb between the gate electrodes 21B is Sb> 2 (x + d).
It is desirable to design so as to be + C.

According to such a configuration, the TEOS is provided between each gate electrode 21A in the memory cell portion by a single process.
With the film 41 buried, the side wall insulating film 22b can be formed only on the side wall of each gate electrode 21B in the peripheral circuit portion.

As a result, the silicide layer 52 can be formed only on the surface of the source / drain region 24B of the MOSFET 20B in the peripheral circuit portion, which is exposed after the formation of the sidewall insulating film 22b.

That is, the silicide layer 52 always has a distance equal to the length x of the side wall insulating film 22b between the silicide layer 52 and the side wall insulating film 22a on the surface of the source / drain region 24B of each MOSFET 20B in the peripheral circuit portion. It is formed to have.

As described above, when the silicide layer 52 is selectively formed only on the surface of the source / drain region 24B of the MOSFET 20B in the peripheral circuit portion for high-speed signal processing, the silicide layer 22b is formed by forming the sidewall insulating film 22b. The silicide layer 52 is formed by exposing the surface of the source / drain region 24B of the MOSFET 20B in the peripheral circuit portion where the layer 52 is formed, and automatically forming the silicide layer 52 on the exposed portion. Patterning can be omitted.

Therefore, even when the processing speed in the peripheral circuit section is to be improved, a DRAM in which the memory cell section and the peripheral circuit section are mounted together can be easily realized without increasing the number of lithography steps. It becomes something.

FIG. 11 shows a schematic configuration of a DRAM according to the sixth embodiment of the present invention.

In this DRAM, for example, in the structure according to the above-described fifth embodiment, a contact portion 63 is further formed by burying doped polysilicon between gate electrodes 21A of MOSFETs 20A in the memory cell portion. In addition, the source / drain region 24 in at least a part of the MOSFET 20B
When the silicide layer 52 is formed on the surface of B, the silicide layer 52 is also formed on the upper surface of the contact portion 63 at the same time.

According to the DRAM having the structure according to the sixth embodiment, for example, by using polysilicon capable of lowering resistance for a part of the bit line contact portion 33A and the diffusion layer contact portion 36 of the MOSFET 20A,
The D of the configuration according to the above-described third embodiment, for example, the contact resistance of the OSFET 20A can be kept low.
Almost the same effects as the RAM can be expected.

FIG. 12 schematically shows a main part of a manufacturing process of the DRAM according to the seventh embodiment of the present invention. Here, only the peripheral circuit portion related to the formation of the silicide layer 52 is shown.

For example, as in the case of manufacturing the DRAM having the configuration according to the fifth embodiment, the side wall insulating film 22a is already formed on the side wall portions of the gate electrodes 21B and 21B '.
(See FIG. 12 (a))
A TEOS film 41 is deposited on the entire surface (see FIG. 12B).

Next, the TEOS film 41 is etched back by isotropic etching to form the gate electrode 21 of each MOSFET 20A in the memory cell portion.
While the TEOS film 41 is left between A, the T
The EOS film 41 is entirely removed (see FIG. 12C).

Next, a high melting point metal (for example, a Ti film or a TiN film) 51 for a salicide process is deposited on the entire surface by sputtering or CVD (FIG. 1).
2 (d)), RTA is performed to form a silicide layer 52 on the interface between the refractory metal 51 and the source / drain region 24B.
Is formed (see FIG. 12E).

Thereafter, by removing the excess refractory metal 51, a silicide layer 52 having a lower resistance than the source / drain region 24B can be formed on the surface of the source / drain region 24B in at least a part of the MOSFET 20B. (See FIG. 12 (f)).

As described above, even when the entire TEOS film 41 in the peripheral circuit portion is removed by isotropic etching, the MOSFET 20B can be removed without a lithography process.
Layer 5 on the surface of the source / drain region 24B of FIG.
2 can be formed, and the processing speed in the peripheral circuit section can be improved.

FIG. 13 schematically shows a main part of a manufacturing process of the DRAM according to the eighth embodiment of the present invention. Here, only the peripheral circuit portion related to the formation of the silicide layer 52 is shown.

For example, as in the case of manufacturing the DRAM having the configuration according to the fifth embodiment, the side wall insulating film 22a is already formed on the side wall of each of the gate electrodes 21B and 21B '.
After performing the steps up to forming a silicon nitride film, a silicon nitride film 71 is deposited on the entire surface (see FIG. 13A).

Then, a TEOS film 41 is further deposited on the silicon nitride film 71 (see FIG. 13B).

Next, the TEOS film 41 is etched back by isotropic etching, and a TE is provided between the gate electrodes 21A of the MOSFETs 20A in the memory cell portion.
While leaving the OS film 41, the TEOS film 41 in the peripheral circuit portion
Are all removed (see FIG. 13C).

Next, after removing the silicon nitride film 71 existing on the surface of the source / drain region 24B for forming at least the silicide layer 52, the refractory metal 51 for the salicide step is removed by sputtering or CVD. It is deposited by a method (see FIG. 13D).

Next, RTA is performed to obtain a high melting point metal 51.
A silicide layer 52 is formed at the interface between the gate and the source / drain region 24B (see FIG. 13E).

Thereafter, by removing the excess refractory metal 51, a silicide layer 52 having a lower resistance than the source / drain region 24B can be formed on the surface of the source / drain region 24B in at least a part of the MOSFET 20B. (See FIG. 13 (f)).

Before the TEOS film 41 is deposited as in the DRAM having the configuration according to the eighth embodiment, the TEO
When the silicon nitride film 71 having a sufficient etching selectivity is formed between the silicon nitride film 71 and the S film 41, not only the silicide layer 52 can be formed without a lithography step, but also the TEOS film 41 is removed. Since the silicon nitride film 71 acts as a stopper in the process, damage such as scuffing on the surface of the semiconductor substrate 11 can be reduced.

In each of the above embodiments, a case has been described in which the gate side wall 22B of the peripheral circuit portion is formed using a silicon oxide film and a silicon nitride film. However, the present invention is not limited to this. For example, it can be formed by a combination of organic low dielectric films.

The second insulator for forming the side wall insulating film 22b is, for example, an oxide film to which an impurity such as phosphorus or boron is added, phosphorus glass or BPS.
It is also possible to use G or the like.

The side wall insulating film 22b and the interlayer insulating film 3
Although the case where both 1 and 31a are formed using a silicon oxide film-based material has been described, the present invention is not limited to this.

The following shows other examples of the structure of MOSFET 20B used in the peripheral circuit section, for example, in the DRAM having the structure according to the fifth embodiment (see FIG. 10).

FIG. 14 shows a MOSF in the case where a gate side wall 22B is formed on a side wall portion of a gate electrode 21B by a side wall insulating film 22a and a side wall insulating film 22b.
It is an example of ET20B.

In this case, in addition to the case where the first interlayer insulating film 31a is formed using the same material as the side wall insulating film 22b,
For example, as shown in FIG. 3A, the side wall insulating film 22b can be formed using a different material.

A MOSFE used for a peripheral circuit portion
As T20B, the first interlayer insulating film 31a is simply
In addition to using the same material or a different material as the sidewall insulating film 22b, the extension structure is formed by partially forming the impurity diffusion region 25B having a deeper junction than the source / drain region 24B. You may make it implement | achieve.

FIG. 13B shows an example in which the first interlayer insulating film 31a is formed by using the same material as the side wall insulating film 22b in the case of realizing the extension structure, and FIG. This is an example in the case of using different materials.

FIG. 15 shows a MOSFET 20B in the case where a thin silicon nitride film 71 is provided between a sidewall insulating film 22a and a sidewall insulating film 22b of a gate sidewall 22B formed on a sidewall portion of a gate electrode 21B. It is an example.

In this case, the first interlayer insulating film 31a can be formed using the same material as the side wall insulating film 22b, for example, as shown in FIG.

A MOSFE used in a peripheral circuit section
As T20B, for example, as shown in FIG.
The first interlayer insulating film 31a and the side wall insulating film 22b can be formed using different substances, or simply the first
Is formed using the same material or a different material as the side wall insulating film 22b.
An extension structure may be realized by partially forming an impurity diffusion region 25B having a junction deeper than the drain region 24B.

FIG. 23C shows an example in which the first interlayer insulating film 31a is formed by using the same material as the side wall insulating film 22b in the case of realizing the extension structure, and FIG. This is an example in the case of using different materials.

The side wall insulating film 22a and the side wall insulating film 22
In the case where the silicon nitride film 71 is provided between the contact hole 32b and the contact hole 32B, for example, as shown in FIG. Since the silicon nitride film 71 extends to the silicide layer 52, the semiconductor substrate 11
Can be prevented from being damaged by etching.

This is not limited to the case where the first interlayer insulating film 31a and the side wall insulating film 22b are formed using the same material, but the first interlayer insulating film 31a and the side wall insulating film 22b are formed using different materials. The same applies to the case where the extension structure is realized and the case where the extension structure is realized.

FIG. 17 shows that a silicon nitride film 22a 'for forming a side wall insulating film 22a of a gate side wall 22B formed on a side wall portion of a gate electrode 21B is replaced with a silicide layer 5.
MOSF when extended to 2
It is an example of ET20B.

Such a silicon nitride film 22a 'can be easily formed, for example, by omitting the etching back for forming the side wall insulating film 22a.

In this case, the first interlayer insulating film 31a can be formed using the same material as the side wall insulating film 22b, for example, as shown in FIG.

Also, the MOSFE used in the peripheral circuit section
As T20B, for example, as shown in FIG.
The first interlayer insulating film 31a and the side wall insulating film 22b can be formed using different substances, or simply the first
Is formed using the same material or a different material as the side wall insulating film 22b.
An extension structure may be realized by partially forming an impurity diffusion region 25B having a junction deeper than the drain region 24B.

[0214] By the way, FIG. 17C shows an example in which the first interlayer insulating film 31a is formed by using the same material as the side wall insulating film 22b when the extension structure is realized, and FIG. This is an example in the case of using different materials.

In the case where the silicon nitride film 22a ′ is provided so as to extend to the silicide layer 52,
For example, as shown in FIG.
Even if the position of the opening slightly shifts due to misalignment of the mask at the time of opening the hole, it is possible to prevent the semiconductor substrate 11 from being damaged by etching.

This is not limited to the case where the first interlayer insulating film 31a and the side wall insulating film 22b are formed using the same material, but the first interlayer insulating film 31a and the side wall insulating film 22b are formed using different materials. The same applies to the case where the extension structure is realized and the case where the extension structure is realized.

Further, as described in the DRAM according to the fifth embodiment, each gate electrode 21 of the memory cell portion is formed.
Designing the space Sa between A to be Sa <2 (x + d) and the space Sb between the gate electrodes 21B of the peripheral circuit portion to be Sb> 2 (x + d) means that the silicide layer 52 is not formed. DRA according to the first embodiment described above
Also when applied to M, it is very effective in easily realizing the extension structure in the peripheral circuit portion without increasing the lithography process.

Of course, various modifications can be made without departing from the scope of the present invention.

[0219]

As described above in detail, according to the present invention, a first insulated gate transistor capable of forming a fine contact hole in a self-aligned manner with respect to a gate electrode and a short channel effect are provided. It is possible to provide a semiconductor device and a method for manufacturing the same, which can integrate a second insulated gate transistor capable of sufficiently reducing parasitic resistance while suppressing the same on the same substrate, and which can achieve high density and high performance. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part illustrating a schematic configuration of a semiconductor device according to a first embodiment of the present invention, taking a DRAM as an example;

FIG. 2 is also a schematic cross-sectional view of a main portion for illustrating a manufacturing process of the DRAM.

FIG. 3 is also a schematic cross-sectional view of a main portion for describing a manufacturing process of the DRAM.

FIG. 4 is a schematic cross-sectional view of a main portion for illustrating a manufacturing process of the DRAM.

FIG. 5 is also a schematic cross-sectional view of a main portion for illustrating a manufacturing process of the DRAM.

FIG. 6 is also a schematic cross-sectional view of a main portion for illustrating a manufacturing process of the DRAM.

FIG. 7 is a schematic cross-sectional view of a main part showing a manufacturing process of the DRAM according to the second embodiment of the present invention;

FIG. 8 is a schematic cross-sectional view of a main part showing a manufacturing process of the DRAM according to the third embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view of a main part showing a manufacturing process of a DRAM according to a fourth embodiment of the present invention.

FIG. 10 is a DRAM according to a fifth embodiment of the present invention.
The schematic block diagram which shows the principal part of FIG.

FIG. 11 is a DRAM according to a sixth embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view showing a main part of FIG.

FIG. 12 is a DRAM according to a seventh embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view of a main part showing a manufacturing process of FIG.

FIG. 13 shows a DRAM according to an eighth embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view of a main part showing a manufacturing process of FIG.

FIG. 14 shows an MO in a peripheral circuit section of the DRAM.
FIG. 9 is a schematic cross-sectional view showing another configuration example of the SFET.

FIG. 15 shows an MO in a peripheral circuit section of the DRAM.
FIG. 9 is a schematic cross-sectional view showing another configuration example of the SFET.

FIG. 16 is a schematic cross-sectional view showing a configuration example of a peripheral circuit portion of the DRAM.

FIG. 17 shows an MO in a peripheral circuit section of the DRAM.
FIG. 9 is a schematic cross-sectional view showing another configuration example of the SFET.

FIG. 18 is a schematic cross-sectional view showing a configuration example of a peripheral circuit portion of the DRAM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate 11a ... Cell area 11b ... Peripheral circuit area 12 ... Element isolation area (field area) 20A ... First insulated gate transistor (MOSFE)
T) 20B: Second insulated gate transistor (MOSFE)
T) 21A, 21B, 21B '... gate electrode 21A' ... dummy gate electrode 22A, 22B ... gate side wall 22a, 22b ... side wall insulating film 22a '... silicon nitride film 23A, 23B ... gate insulating film 24A, 24B ... extension region 25A, 25B ... impurity diffusion regions 26A, 26B ... silicon nitride film 31 ... interlayer insulating film 31a ... first interlayer insulating film 31b ... second interlayer insulating film 32A, 32B, 32B '... contact hole 33 ... wiring contact part 33A ... Bit line contact part 33B ... Diffusion layer contact part 33B '... Gate contact part 34 ... Bit line 35 ... First layer wiring 36 ... Diffusion layer contact part 37 ... Storage electrode 38 ... Plate electrode 39 ... Insulating film 41 ... TEOS Film 42: resist pattern 51: refractory metal 52: silicide layer 61 contact hole 62, 63 contact part 71 silicon nitride film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yusuke Yukiyama 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Inside the Toshiba Yokohama office

Claims (64)

[Claims] 1. A semiconductor device comprising at least a first and a second
In the semiconductor device having the MIS structure in which the insulated gate transistor is integrated, the second insulated gate transistor may be formed by a second insulating film.
A semiconductor device, characterized in that the side wall insulating film formed on the side wall portion of the gate electrode in the insulated gate transistor has a longer side wall length. 2. The semiconductor device according to claim 1, wherein a memory cell section is formed by said first insulated gate transistor. 3. The semiconductor device according to claim 1, wherein a peripheral circuit section is constituted by said second insulated gate transistor. 4. The first insulating gate type transistor according to claim 1, wherein a side wall insulating film formed on a side wall portion of the gate electrode is made of a first insulator. Semiconductor device. 5. A side wall insulating film formed on a side wall portion of a gate electrode in the second insulated gate transistor comprises a first insulator and a second insulator. 3. The semiconductor device according to any one of 3. 6. The semiconductor device according to claim 5, wherein the first insulator and the second insulator have an etching selectivity with respect to each other. 7. The semiconductor device according to claim 6, wherein said first insulator is silicon nitride, and said second insulator is silicon oxide. 8. The semiconductor device according to claim 1, wherein a contact hole is formed in a self-aligned manner with respect to a gate electrode of the first insulated gate transistor. 9. The semiconductor device according to claim 8, wherein a gate electrode of said first insulated gate transistor includes an electrically independent dummy gate electrode pattern. 10. The method according to claim 1, wherein a junction depth of the diffusion region in the first insulated gate transistor is smaller than a junction depth of the diffusion region in the second insulated gate transistor. Semiconductor device. 11. A semiconductor substrate divided into a memory cell region and a peripheral circuit region by a field region; and a first insulator formed on a side wall portion of a gate electrode integrated in the memory cell region on the semiconductor substrate. A plurality of first insulated gate transistors each having a first sidewall insulating film formed thereon; a first insulator provided in a peripheral circuit region on the semiconductor substrate; A semiconductor device, comprising: at least one second insulated gate transistor in which a second sidewall insulating film made of a second insulator is formed. 12. The semiconductor device according to claim 11, wherein the first insulator and the second insulator have an etching selectivity with respect to each other. 13. The semiconductor device according to claim 11, wherein said first insulator is silicon nitride, and said second insulator is silicon oxide. 14. The semiconductor device according to claim 11, wherein at least one of the plurality of first insulated gate transistors has a contact hole formed in the gate electrode in a self-aligned manner. 3. The semiconductor device according to claim 1. 15. The semiconductor device according to claim 1, wherein, of the plurality of first insulated gate transistors, a gate electrode of the transistor at an outermost peripheral portion thereof is a dummy gate electrode pattern that is electrically independent. 11 or 14
The semiconductor device according to any one of the above. 16. The semiconductor device according to claim 11, wherein the junction depth of the diffusion region in the first insulated gate transistor is smaller than the junction depth of the diffusion region in the second insulated gate transistor. Semiconductor device. 17. A semiconductor substrate divided into a memory cell region and a peripheral circuit region by a field region, and a first insulator formed on a side wall portion of a gate electrode integrated in the memory cell region on the semiconductor substrate. A plurality of first insulated gate transistors each having a first sidewall insulating film formed thereon; a first insulator provided in a peripheral circuit region on the semiconductor substrate; At least one second insulated gate type having a second side wall insulating film formed of a second insulator and having a low resistance region selectively provided on a surface of the diffusion region; A semiconductor device comprising a transistor. 18. The semiconductor device according to claim 18, wherein the low-resistance region is located between the second insulated gate transistor and the second insulated gate transistor.
18. The semiconductor device according to claim 17, wherein said semiconductor device is provided at a position separated by a side wall length of said side wall insulating film. 19. The semiconductor device according to claim 17, wherein said first insulator and said second insulator have an etching selectivity with respect to each other. 20. The semiconductor device according to claim 17, wherein said first insulator is silicon nitride, and said second insulator is silicon oxide. 21. A method according to claim 17, wherein at least one of the plurality of first insulated gate transistors has a contact hole formed in the gate electrode in a self-aligned manner. 3. The semiconductor device according to claim 1. 22. A transistor according to claim 21, wherein a gate electrode of the transistor at the outermost periphery of the plurality of first insulated gate transistors is a dummy gate electrode pattern that is electrically independent. 17 or 21
The semiconductor device according to any one of the above. 23. The method according to claim 17, wherein the junction depth of the diffusion region in the first insulated gate transistor is smaller than the junction depth of the diffusion region in the second insulated gate transistor. Semiconductor device. 24. The semiconductor device according to claim 21, wherein a conductive material is buried in the contact hole. 25. The semiconductor device according to claim 24, wherein a low resistance region is provided on a surface of the conductive material. 26. A semiconductor substrate divided into a memory cell region and a peripheral circuit region by a field region, and a first insulator integrated on a memory cell region on the semiconductor substrate and formed on sidewall portions of a gate electrode. A plurality of first insulated gate transistors each having a first sidewall insulating film formed thereon; a first insulator provided in a peripheral circuit region on the semiconductor substrate; At least one second insulated gate transistor formed with a second sidewall insulating film formed of a second insulator; and between the first insulator and the second insulator. A third insulator provided so as to cover a surface of the semiconductor substrate. 27. The semiconductor device according to claim 26, wherein the third insulator has an etching selectivity with respect to at least the second insulator. 28. The semiconductor device according to claim 2, wherein the third insulator is formed thinner than the first insulator.
28. The semiconductor device according to any one of 6 and 27. 29. The semiconductor device according to claim 26, wherein the first insulator and the second insulator have an etching selectivity with respect to each other. 30. The semiconductor device according to claim 26, wherein the first insulator and the third insulator are silicon nitride, and the second insulator is silicon oxide.
30. The semiconductor device according to any one of items 29. 31. At least one of the plurality of first insulated gate transistors has a contact hole formed in the gate electrode and the field region in a self-aligned manner. 27. The semiconductor device according to claim 26. 32. A gate electrode of a transistor at the outermost periphery of the plurality of first insulated gate transistors is a dummy gate electrode pattern that is electrically independent. 26 or 31
The semiconductor device according to any one of the above. 33. The junction according to claim 26, wherein the junction depth of the diffusion region in the first insulated gate transistor is smaller than the junction depth of the diffusion region in the second insulated gate transistor. Semiconductor device. 34. A memory cell region on a semiconductor substrate, each having a gate electrode in which a side wall insulating film having a length d of a first insulator is formed, and a maximum space between each gate electrode is 2 A plurality of first insulated gate transistors arranged so as to be smaller than (d + x), and a sidewall insulating film having a length d of a first insulator in a peripheral circuit region on the semiconductor substrate. A gate electrode formed,
And a low resistance region provided on the surface of the diffusion region at a position apart from the sidewall insulating film by the distance x, respectively, and the maximum space between the gate electrodes is 2 (d +
A semiconductor device, comprising: a plurality of second insulated gate transistors disposed so as to be larger than x). 35. A side wall insulating film made of a second insulator is further provided outside a side wall insulating film made of the first insulator on a side wall portion of each gate electrode in the second insulated gate transistor. 35. The semiconductor device according to claim 34, wherein: is formed. 36. The semiconductor device according to claim 34, wherein said x corresponds to a sidewall length of a sidewall insulating film made of said second insulator. 37. The semiconductor device according to claim 35, wherein a third insulator is provided under the sidewall insulating film made of the second insulator. 38. The method according to claim 34, wherein the second insulator is buried between each gate electrode of the first insulated gate transistor except for a wiring contact portion. Semiconductor device. 39. A conductive material is buried between the respective gate electrodes of the first insulated gate transistor including the wiring contact part.
5. The semiconductor device according to 4. 40. The semiconductor device according to claim 39, wherein a low resistance region is provided on a surface of the conductive material. 41. A memory cell region on a semiconductor substrate, a gate electrode of a plurality of first insulated gate transistors for forming a memory cell portion, and a peripheral circuit in a peripheral circuit region on the semiconductor substrate. After forming at least one gate electrode of at least one second insulated gate transistor for forming a portion, the first insulated gate transistor is formed of a first insulator on a side wall portion of each gate electrode. First
Forming a second sidewall insulating film made of the first insulator and the second insulator on a sidewall portion of a gate electrode in the second insulated gate transistor. And a method for manufacturing a semiconductor device. 42. The method according to claim 41, wherein the first insulator and the second insulator are made of a material having an etching selectivity with respect to each other. 43. A silicon nitride as the first insulator, a silicon oxide as the second insulator,
43. The method for manufacturing a semiconductor device according to claim 41, wherein the semiconductor device is used for each. 44. The method according to claim 41, wherein at least one of the plurality of first insulated gate transistors has a contact hole formed in a self-aligned manner with respect to the gate electrode. The manufacturing method of the semiconductor device described in the above. 45. A semiconductor device according to claim 45, wherein the outermost peripheral portion of the plurality of first insulated gate transistors has a dummy gate electrode pattern that is electrically independent, and the transistor is formed. Claim 41 or 4 characterized by the above-mentioned.
5. The method of manufacturing a semiconductor device according to any one of 4. 46. The semiconductor device according to claim 41, wherein a junction depth of the diffusion region in the first insulated gate transistor is formed smaller than a junction depth of the diffusion region in the second insulated gate transistor. 13. The method for manufacturing a semiconductor device according to item 5. 47. A step of forming a field region and separating an element region on a semiconductor substrate into a memory cell region and a peripheral circuit region; and a plurality of first cells for forming a memory cell portion in the memory cell region. Forming at least one gate electrode of at least one second insulated gate transistor for forming a peripheral circuit portion in each of the gate electrodes of the insulated gate transistor and the peripheral circuit region; Depositing a first insulator on the substrate; selectively removing the first insulator, forming a sidewall portion of each gate electrode in the first insulated gate transistor;
A step of forming a first side wall insulating film on each side wall portion of the gate electrode in the second insulated gate transistor; a step of depositing a second insulator over the entire surface of the semiconductor substrate; The second insulator is selectively removed, and a sidewall portion of a gate electrode in the second insulated gate transistor is
Forming a second sidewall insulating film. 48. The method according to claim 47, wherein the first insulator and the second insulator are made of a material having an etching selectivity with respect to each other. 49. A silicon nitride as the first insulator, a silicon oxide as the second insulator,
49. The method for manufacturing a semiconductor device according to claim 47, wherein the method is used for each. 50. A semiconductor device comprising: a plurality of first insulated gate transistors each having an electrically independent dummy gate electrode pattern at an outermost peripheral portion thereof; The method for manufacturing a semiconductor device according to claim 47, wherein: 51. A method according to claim 51, wherein the plurality of first insulators are provided on the second insulator.
48. The method of manufacturing a semiconductor device according to claim 47, further comprising a step of forming a contact hole in at least one gate electrode of the insulated gate transistor in a self-aligned manner. 52. The method according to claim 51, further comprising a step of burying a conductive material in a contact hole formed in the second insulator. 53. The method according to claim 53, further comprising, after forming the second side wall insulating film, forming a diffusion region of the second insulated gate transistor again via the second side wall insulating film. The method for manufacturing a semiconductor device according to claim 47, wherein: 54. The method according to claim 47, further comprising a step of forming a low-resistance region on the surface of the diffusion region of the second insulated gate transistor after forming the second sidewall insulating film. 53. The method of manufacturing a semiconductor device according to any one of the items 53. 55. A step of forming a low resistance region on the surface of the diffusion region in the second insulated gate transistor and simultaneously forming a low resistance region on the surface of the conductive material embedded in the contact hole. The method for manufacturing a semiconductor device according to claim 52, further comprising: 56. A step of depositing an interlayer insulating film over the entire surface of the semiconductor substrate after forming the second sidewall insulating film; and a step of selectively forming a plurality of contact holes in the interlayer insulating film. 5. The method according to claim 4, further comprising:
55. The method of manufacturing a semiconductor device according to any one of 7, 53 and 54. 57. The method according to claim 56, wherein a material having an etching selectivity with respect to the first insulator is used as the interlayer insulating film. 58. The method according to claim 56, further comprising a step of flattening a surface of said interlayer insulating film. 59. The semiconductor according to claim 56, wherein at least one of said contact holes is opened in a self-aligned manner with respect to a gate electrode of said first insulated gate transistor. Device manufacturing method. 60. The method according to claim 5, further comprising a step of forming a diffusion region of the first insulated gate transistor again through the contact hole.
7. The method for manufacturing a semiconductor device according to item 6. 61. The semiconductor device according to claim 60, wherein a junction depth of the diffusion region of the first insulated gate transistor is smaller than a junction depth of the diffusion region of the second insulated gate transistor. The manufacturing method of the semiconductor device described in the above. 62. The method according to claim 47, further comprising a step of forming a third insulator over the entire surface of the semiconductor substrate after forming the first sidewall insulating film. 13. The method for manufacturing a semiconductor device according to item 5. 63. The third insulator may include the second insulator
63. The method of manufacturing a semiconductor device according to claim 62, wherein a substance having an etching selectivity to said insulator is used. 64. The method according to claim 62, wherein the third insulator is formed thinner than the first insulator.