JPH10233676A - Method for arraying local mutual connection line inside logic array block and programmable logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the number of wire segments utilizable for routing inside a logic array block(LAB) and to house many logic elements(LEs) inside the LAB in the form having excellent area efficiency by using a hierarchical mutual connection architecture among the LEs, among the LABs and among global mutual connections. SOLUTION: The LAB 100 is provided with the 16 pieces of the LEs 102 and the local mutual connection lines of two different types. The local mutual connection lines of the type indicated as full length(FL) local lines 104 are extended over the entire length of the LAB 100 and connected to all the 16 pieces of the LEs 102. A second type indicated as a half length(HL) local line 106 is divided into two segments and the respective segments are extended over the length of the half of the LAB 100. One output line 108 of each of the 16 pieces of the LEs 102 is connected to one of the four FL local lines 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to integrated circuits and, more particularly, to an improved architecture for a programmable logic device (PLD) that reduces the number of local interconnect wires required for larger logic block chunks.

[0002] Programmable logic devices are digital, digital devices used to implement custom logic functions.
User-configurable integrated circuit. In this specification,
The term PLD includes all digital logic configured by the end user, including programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), and erasable and complex PLDs. The basic building blocks of PLD are:
A logic element that can execute a limited logic function on a plurality of input variables. The logic elements typically comprise circuits, programmably implement "sum of products" logic, and further include one or more registers to implement sequential logic. Conventional PLDs combine many such logic elements through an array of programmable interconnects to facilitate the implementation of complex logic functions. Programmable logic devices are particularly widely applied because of their low upfront cost and variety for users.

[0003] A variety of PLD architecture approaches to arranging interconnect arrays and logic elements have been developed to optimize logic density and the ability to route signals between various logic elements. A successful example of a PLD architecture is Altera Corporation.
) manufactured by FLEX® and MAX
(Registered trademark) family of programmable logic devices. For example, FLEX® 8000 family logic devices utilize a large matrix of logic elements (LEs). In one commercial embodiment of these devices, each LE has a combinational logic (eg, AND, OR, NOT, XOR, NAND, N
OR, and many others) and registers that provide sequential logic functions. LEs are configured, for example, as groups of eight, forming larger logical array blocks (LABs). LAB has a variety of L
E has an internal interconnect structure. The plurality of LABs are arranged in a two-dimensional array and are programmably connectable to external pins of the device through global horizontal and vertical interconnect lines, and are also programmably connectable to each other. In one embodiment, programmability is achieved by a programmable multiplexer that connects global and local interconnect lines to each LE. This architecture has been quite successful and is considered a pioneer in the field of programmable logic.

[0004] Constant advances in semiconductor manufacturing technology have allowed more gates to be integrated on a chip. PLDs are designed with significantly higher logic densities for each new generation. Often the transition to the new generation requires a new PLD architecture to fine tune and optimize the performance of the device. New, higher density PLD
One of the design features of interest in re-evaluating
This is the number of LEs for each B. In a complex programmable logic device (CPLD) architecture, one L
Efforts are underway to determine the optimal number of LEs per AB. On the other hand, if the number of LEs per LAB is large, the fixed cost of the LABs can be amortized by the large number of LEs. On the other hand, each LE local output is
This causes the multiplexer to be wider for each of the inputs. That is, extra routing and multiplexing reduce efficiency, and adding more LE results in a LAB with less area efficiency. L
A larger AB also results in a longer local interconnect line, which places greater demands on the driver circuit.

[0005] Thus, there is a need for an improved PLD architecture design to provide an optimal balance between routing flexibility and logic density and to address new design challenges posed by more advanced process technologies.

[0006]

SUMMARY OF THE INVENTION The present invention provides a PLD that uses a hierarchical interconnect architecture between logic elements, between logic array blocks, and between global interconnects. In one embodiment, the invention comprises a first group of local interconnect lines coupling to the outputs of two or more LEs in a LAB and a separate segment coupled to a subset of LEs in the LAB. Two local interconnect lines. By eliminating the one-to-one correspondence between the number of LEs in the LAB and the number of local interconnect wires, the present invention increases the number of physical wire segments available for routing in the LAB and reduces area efficiency. It is possible to include more LEs in the LAB in a good way. This results in a smaller die area for a given number of LEs. Various driver circuits are also provided for driving signals on the novel hierarchical interconnect structure of the present invention.

Accordingly, in one embodiment, the present invention provides a plurality of logic array blocks arranged in a plurality of logic array blocks, each logic array block including a plurality of subsets of logic elements and a plurality of local interconnect lines. Provided is a programmable logic circuit including a logic element. The global interconnect array programmably couples the input and output terminals of the plurality of logic elements. Local interconnect lines are divided into a first type that couples to two or more logic element outputs in the logic array block and a second type that couples to a single logic element output in the logic array block.

In one embodiment of the present invention, a first type of local interconnect line extends along the entire length of the logic array block, couples to all logic elements in the logic array block, and has a second type of local interconnection line. The interconnect lines
Each line group extends along half the length of the logic array block and includes two line groups, each coupling to one half of a subset of the plurality of logic elements.

In another embodiment, the second type of local interconnect lines is such that each line group extends along a length of a quarter of the logic array block, each of which is a subset of a plurality of logic elements. Includes four groups of lines that combine into a quarter.

The nature and advantages of the PLD of the present invention with a hierarchical local interconnect will be better understood with reference to the following detailed description and drawings.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a logic array block (LAB) 10 according to one embodiment of the present invention.
A simplified example embodiment of zero is shown. A LAB as used in this description represents a grouping of logic elements (LEs) in a PLD architecture of any type consisting of a plurality of LABs.
Some LABs can be arranged in a two-dimensional array and interconnected by a network of programmable interconnects. An example of such a PLD is described in U.S. Pat. No. 5,436,5, entitled "Programmable Logic Array Integrated Circuit", owned by the assignee of the present invention, which is hereby incorporated by reference in its entirety for all purposes.
No. 75 describes this in detail.

The LAB 100 shown in FIG. 1 has sixteen logic elements (LEs) 102 and two different types of local interconnect lines. A local interconnect line of the type represented here as a full length (FL) local line 104 extends the entire length of the LAB 100 and connects to all 16 LEs 102. LAB1
00 includes four FL local lines 104. The second type, here represented as a half-length (HL) local line 106, is split into two segments, each segment extending over half the length of LAB 100.
This embodiment has eight HL local lines 10 connected to a subset of LEs in LAB 100 as shown.
8 includes two sets. The number of local interconnect lines and LEs shown in FIG. 1 are for illustrative purposes only and are not limiting.

FIG. 1 also shows the connection between the output of each LE 102 and the local interconnect lines 104 and 106.
One output line 108 of each of the 16 LEs 102
Connect to one of the four FL local lines 104 so that each FL local line 104 is shared by the four LE outputs. Output line 11 of each LE 102
0 connects to the HL local line 106. Because the FL and HL lines differ in length (ie, loading), in this embodiment, the LE output line connected to each local interconnect line requires a correspondingly different drive capability. As such, each LE is shown in FIG. 1 as having two output lines 108 and 110 that carry the same signal. Alternatively, depending on the resources within each LE, one output line (108) may hold the combined output signal, while the other (110) holds the registered one of the output signals. Various embodiments of the LE output driver circuit are described below in connection with FIGS. 4, 5, and 6.

Each LE 102 may have, for example, four inputs. Using, as an example, a PLD that uses a multiplexer to program the interconnections with the logic elements, such as those described in US Pat. No. 5,436,575, cited above, each input of LE 102 is dedicated. Receives the output of the multiplexer. The multiplexer receives, at a corresponding plurality of inputs, all of the FL and HL local lines, plus a predetermined number of additional LAB interconnect lines. FIG. 2 shows a simplified diagram of an exemplary input / output interconnect structure for a LAB. In this example, each LE 102 has four inputs A,
It has B, C, and D, and two outputs OUT1 and OUT2. In this example, there are a group of four FL local lines 104, eight HL local lines 106, and LAB lines 200. Output O of each LE
UT1 is connected to one of the four FL local lines 104, and the output OUT2 is connected to eight HL local lines 1
06. Each input of LE 102 receives the output of multiplexer (MUX) 202. Each MU
X202 has at its input the FL local line 10
4, HL local line 106 and LAB line 2
Receive all of 00.

[0015] The exemplary LAB 100 of FIG.
E102 and four FL local lines 104
Common to all six LEs, resulting in four LEs
The output will share one FL local line. The total local interconnect channel width in this embodiment is 8 + 4 = 12 lines. Thus, the interconnect architecture of the present invention is such that the outputs of all LEs are connected to dedicated local interconnect lines (ie, 1
Compared to the conventional approach (16 local interconnect lines for 6 LEs), the number of interconnect lines will be reduced by 25%.

Thanks to the reduced number of local interconnect lines made possible by the present invention, not only is the area used by the local interconnect channels reduced, but also the size of the input multiplexer 202 (FIG. 2). In other words, each MUX 202 receives four less inputs,
Therefore, the width is small. Assuming that the embodiment shown in FIG. 2 includes, for example, 20 LAB lines 200, each M
UX 202 is 20 + 4 + 8 = 3 instead of 36 input widths
This is two input widths. If the number of LABs and multiplexers in the CPLD is large, this will result in a significant reduction in total die area. That is, reducing only four local lines, as realized by the exemplary embodiment of the present invention shown in FIGS. 1 and 2, results in significant area savings. Shorter H compared to FL line
Reduction of the delay due to the L line is another advantage of the present invention.

Connections through various levels of interconnects (eg, global and local) within a CPLD are typically programmed by sophisticated software deployment and routing tools. As taught by the present invention, one of the factors considered in determining the number of FL and HL local lines is:
The ability of deployment and routing software to bundle LEs. For example, for a very efficient layout, an embodiment with four HL local lines for each group of four LEs is preferred. In such an embodiment, the more accurate name of this HL would be 1/4
It may be a long (or QL) local line. FIG. 3 shows such an alternative embodiment for a LAB in a PLD according to the present invention. This embodiment also has 16 LE10s.
2 but instead of two sets of half-length local interconnect lines, this embodiment provides four sets of quarter-length (QL) local interconnect lines 300, each connected to a set of four LEs 102. Including. That is, each set of QL local lines 300 includes four wires. Further, as shown, eight FL local lines 104 are connected to sixteen LEs 102. This local interconnect channel is the same width (12 wires) as the previous embodiment. Principles and advantages of operation similar to those shown in FIGS. 1 and 2 apply to this embodiment.

Those skilled in the art will appreciate that many variations of the hierarchical interconnect structure of the present invention are possible. For example, a PLD may be designed to have a LAB with a three level hierarchy within the internal interconnect lines. In other words, the LAB of the 16 LEs has different numbers of Qs
It may have different LE groupings relative to L, HL, and FL local lines. The optimal placement of a given interconnect architecture depends, among other considerations, on the type of process technology utilized (eg, the number of available metal interconnect layers) and the placement and routing software. It will depend on the mounting constraints.

According to the present invention, the ability to route within the LAB can be sacrificed at the expense of gaining area advantages. Because not all LEs in a LAB have dedicated local interconnect lines that can communicate with all other LEs in the same LAB, routing capabilities within the LAB can be somewhat compromised. In the exemplary embodiment shown in FIGS. 1 and 2, for example, every LE 100 is connected to every other LE 1
00 can be connected, but only up to four LEs can be connected from a related LE group to another group. Similarly,
In the exemplary embodiment of FIG. 3, each LE can be connected to any other LE in the LAB, but only up to eight LEs can be connected from related LEs to another. In this way, flexibility in terms of internal communication within the LAB may be somewhat reduced. However, with the use of intelligent placement and routing software, the above problems are almost insignificant. This is especially so considering that the probability that many LEs drive other local LEs is greatly reduced. For example, in a LAB containing eight LEs, the probability that five or more LE outputs will drive other local LEs is greatly reduced.

Furthermore, because the logic in the LAB is replaceable, intelligent placement and routing software can place the LEs that communicate with each other in the same group in the LAB. For example, two LEs that need to communicate with each other are placed in the same group and the HL line 106
(FIG. 1) or QL line 300 (FIG. 3) can be used to communicate with each other. The FL line needs to be used only when all of the HL line and the QL line are used, or only when the destination LE is in another group. In this way, it is possible to maximize the use of shorter, ie, faster, HL and QL lines and obtain the same level of mounting as when using only physically longer (ie, slower) FL lines. It is. That is, the benefits resulting from the significant area savings and speed improvements provided by the interconnect structure of the present invention are:
Outweighs insignificant damage that may be incurred in terms of local routing capabilities.

As briefly described above, the interconnect structure according to the present invention requires different driver circuits.
For example, in the exemplary embodiment of the invention described above, FL
The local line 102 is shared between a plurality of LEs 102. These lines are therefore driven by separate drivers with tri-state capability or through two separate pass transistors. FIG.
5 shows one embodiment of a driver circuit 400 for E output.
Driver circuit 400 includes a first driver element 402 having an output connected to a segmented local line (HL or QL), and a second driver element 404 having an output connected to the FL local line. Driver element 40
4 is tri-state capable and receives a tri-state control input 406. This allows one LE to drive the FL local line, while allowing other, eg, three, LEs sharing the same FL local line to be tri-stated. The driver elements 402 and 404 can be realized by using a known circuit. The control signal for tristate input 406 is:
It can be provided by a programmable element such as a static random access memory (SRAM) cell. Fuseable links, and other programmable elements, such as EEPROM cells, can also be used to provide tri-state signals.

Another embodiment of the driver circuit for the LE output is shown in FIG. This embodiment includes one driver element 500 that drives both FL and segmented (HL or QL) local lines through two separate pass transistors 502 and 504, respectively. The state of each pass transistor is controlled by a programmable element such as an SRAM cell. An alternative embodiment of the driver circuit of FIG. 5 is shown in FIG. Since the segmented (HL or QL) local line is not shared between the LE outputs, it is possible to remove one of the pass transistors and drive each HL or QL directly as shown in FIG. is there. The additional resources required to drive the local lines are negligible compared to the area savings made possible by the reduced interconnect channel width and input MUX size.

FIG. 7 shows a block diagram of an electronic system in which a PLD according to the present invention may be advantageously used. In the particular embodiment of FIG.
And I / O 711 to incorporate PLD 721. PLD 721 may be specifically coupled to memory 705 through connection 731 and to I / O 711 through connection 735. The system may be a digital computing system such as a general purpose computer or special purpose computer, a specialized digital switching network, or other processing system.

Among the various functions performed by processing unit 701, processing unit 701 directs data to appropriate system components for processing or storage, executes programs stored in memory 705, or
/ O711 can be used to interface with other systems. The processing device 701 may be any of the following. That is, a central processing unit (CPU), a microprocessor, a floating point coprocessor, a graphics coprocessor, a hardware controller, a microcontroller, a programmable logic device programmed for use as a controller, or other processing device. In some embodiments, the processing device 7
01 may be a separate and independent computing system. Processor 701 may be used to configure and program PLD 721.

In another embodiment, the source code is stored in memory 70
5, is compiled into a machine language, and is
1 can be performed. The processing unit 701 may not include a CPU, and in one embodiment, the instructions may be executed by one or more PLDs 721. Instead of storing the source code in memory 705, only the machine language representation of the source code may be stored in memory 705 for execution by processor 701. The memory 705 is a PLD 721
May be stored. Alternatively, memory 705 may be any of the following: That is, random access memory (RAM), read-only memory (ROM), fixed or flexible disk medium, PC card flash disk memory, tape,
Either any other storage and retrieval means or a combination of these storage and retrieval means.

The processing device 701 uses the I / O 711,
Provides input and output paths for a user interface. For example, a user can enter a logic function to be programmed into programmable logic device 721. The I / O 711 may be any of the following. That is, a keyboard, mouse, trackball, tablet device, text or graphical display, touch screen, pen tablet, printer, other input or output means, or a combination of these means.

PLD 721 can play a number of different roles in the system of FIG. The PLD 721 includes a processing device 7 that supports internal operation and external operation of the processing device
01 logical building blocks. PLD721
Are programmed to implement the logical functions necessary to perform a particular function within system operation.

In conclusion, the present invention provides various embodiments of a PLD with a hierarchical interconnect architecture between logic elements, between logic array blocks, and between global interconnects. The hierarchical interconnect structure divides the local interconnect lines inside the LAB into independent segments that are coupled to a subset of the LAB's LE. This eliminates the one-to-one correspondence between the number of LEs in the LAB and the number of local interconnect wires and provides a more area efficient interconnect architecture. While the above is a complete description of several embodiments of the present invention, various alternatives,
Variations and equivalents can be used. That is, the scope of the invention should not be determined in connection with the above description, but should instead be determined in connection with the full scope of the appended claims and their equivalents.

[Brief description of the drawings]

FIG. 1 is an exemplary PL with 16 LEs per LAB
FIG. 4 illustrates a hierarchical interconnect structure for D according to one embodiment of the present invention.

FIG. 2 illustrates a simplified input / output structure for an exemplary logic element in a LAB, according to one embodiment of the present invention.

FIG. 3 shows a second example of the hierarchical interconnection structure of the PLD of the present invention.
It is a figure which shows the Example of.

FIG. 4 is a diagram showing a first embodiment for connecting an LE output to a local line using two drivers.

FIG. 5 is a diagram showing a second embodiment for connecting an LE output to a local line using one driver and two pass transistors.

FIG. 6 is a diagram showing still another embodiment for connecting an LE output to a local line using one driver and one pass transistor.

FIG. 7 is a block diagram of an electronic system in which a PLD according to the present invention may be advantageously used.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Logic array block (LAB) 102 Logic element (LE) 104 Full length (FL) local line 106 Half length (HL) local line 108 Output line 110 Output line

Claims (20)

[Claims] 1. A programmable logic circuit, comprising: a plurality of logic array blocks, each logic array block having a plurality of logic elements each having a plurality of inputs and one output; A plurality of local interconnect lines selectively coupled to the plurality of inputs and outputs, respectively, wherein the plurality of local interconnect lines are coupled to two or more logic element outputs in the logic array block. And a second type coupled to a single logic element output in the logic array block, wherein the programmable logic circuit further comprises an input / output terminal of the plurality of logic array blocks and a circuit. A programmable logic circuit that includes a global interconnect array coupled to the logic circuit. 2. The method according to claim 1, wherein the plurality of logic elements are divided into a first group and a second group, and the second type of local interconnect lines are each coupled to the first group of logic elements. The programmable logic circuit of claim 1, wherein the programmable logic circuit is segmented into a first group and a second group each coupled to the second group of logic elements. 3. The second type of local interconnect of the second type, wherein the first group of local interconnect lines of the second type extend substantially parallel adjacent the first group of logic elements. The second group of connection lines extend substantially parallel adjacent to the second group of logic elements, and the first type of interconnect line is adjacent to all of the plurality of logic elements. 3. The programmable logic circuit of claim 2, wherein said programmable logic circuit extends substantially parallel. 4. The programmable logic circuit according to claim 2, wherein said first group and said second group of said plurality of logic elements each include half of said plurality of logic elements. 5. The plurality of logic elements are divided into four groups, and the second type of local interconnect lines are divided into four groups, each coupling to the four groups of the logic elements. Item 2. A programmable logic circuit according to item 1. 6. The logic array block includes sixteen logic elements, the first type of local interconnect line includes four wires, and the first type of local interconnect line includes a first one of the second type of local interconnect line. 3. The programmable logic circuit of claim 2, wherein the second group and the second group each include eight wires. 7. The logic array block includes sixteen logic elements, the first type of local interconnect line includes eight wires, and the four of the second type of local interconnect line. 6. The programmable logic circuit according to claim 5, wherein each of the groups includes four wires. 8. The programmable logic circuit according to claim 6, wherein each of said four wires of said first type of local interconnect line is shared by the outputs of four logic elements. 9. The programmable logic circuit according to claim 1, wherein said output of each of said plurality of logic elements is coupled to a local interconnect line through a respective driver circuit. 10. The driver circuit includes: a first driver element coupling the output of a logic element to a local interconnect line of the first type; and a driver circuit coupling the output of the logic element to the second type of local interconnect. The programmable logic circuit of claim 9, including a second driver element coupled to the interconnect line. 11. The programmable logic circuit according to claim 10, wherein said first driver element is programmably tri-statable. 12. The driver circuit couples the output of a logic element to the first type of local interconnect line through a first programmable pass transistor.
The programmable logic circuit of claim 9, comprising a driver element coupling the output of the logic element to the second type of local interconnect line through a second programmable pass transistor. 13. The driver circuit couples the output of a logic element to a local interconnect line of the first type through a programmable pass transistor and couples the output of the logic element to a local interconnect of the second type. 10. The programmable logic circuit according to claim 9, including a driver element coupled directly to the line. 14. A plurality of inputs each coupled to the plurality of local interconnect lines and one output each coupled to one of the plurality of inputs of each of the plurality of logic elements. The programmable logic circuit according to claim 1, further comprising a plurality of multiplexers. 15. A programmable logic device, comprising: a plurality of logic array blocks, each logic array block including a plurality of logic elements arranged adjacent to each other, each of which has a plurality of inputs and one logic element. And each of the logic array blocks further includes a first plurality of local interconnect lines extending substantially over a length defined by the plurality of logic elements; Each of the connection lines is coupled to a selected plurality of outputs of the plurality of logic elements, and each of the logic array blocks further includes a second plurality of local interconnect lines further divided into a plurality of independent segments; Each segment extends substantially over a length defined by a corresponding subset of the plurality of logic elements Each output of each of the plurality of logic elements, a dedicated one of said second plurality of local interconnect lines 1
And the programmable logic device further includes a global interconnect array coupled to the plurality of logic array blocks and input / output terminals of the device. 16. A plurality of inputs coupled to the first and second plurality of local interconnect lines, and a respective one of the plurality of inputs of each of the plurality of logic elements. The programmable logic device of claim 15, further comprising a plurality of multiplexers, each having one output. 17. In a programmable logic device having a plurality of logic array blocks (LABs) each including a row of logic elements, a method of arranging local interconnect lines in a LAB includes the steps of: , Substantially parallel to the row of logic elements, wherein the first plurality of local interconnect lines have a length substantially equal to the length of the row of logic elements, and the method further comprises: Coupling each of the first plurality of local interconnect lines to an output of two or more logic elements; and arranging the second plurality of local interconnect lines substantially parallel to a row of logic elements. Wherein the second plurality of local interconnect lines are divided into a plurality of independent segments, and the method further comprises the second plurality of local interconnect lines. Each of the lines comprising the step of coupling the output of a single logic element method. 18. The LAB includes sixteen logic elements, the first plurality of interconnect lines includes four wires each coupled to an output of four logic elements, and the second plurality of interconnect lines includes: 18. The interconnect line comprises eight wires.
The method described in. 19. A processing device including the programmable logic circuit according to claim 1, a memory unit storing data, an interface, and a bus network providing a communication link between the processing device, the memory unit and the interface. Including
Electronic system. 20. The electronic system according to claim 19, wherein said processing unit constitutes said programmable logic circuit.