JPH10177560A - Storage device - Google Patents

Abstract

(57) [Summary] To achieve an atomic operation required for a synchronous operation between a plurality of processors without bus locking. An address space that is connected to a multiprocessor system via a split-type bus and that performs an atomic operation indispensable for a synchronous operation using a semaphore / lock variable is premised on an address space that does not overlap with a real memory space. Generates a pseudo memory space that appears to overlap with the real memory space. If the memory access request of the bus master fetched via the bus is for the pseudo memory space, the request is recognized as an atomic operation start access request (S1), and the identifier of the bus master is stored and held (S7). Subsequently, if the identifier of the bus master making the memory access request matches the stored identifier (S1).
5, 16), this is recognized as an atomic operation end access request (S17, 18), and if they do not match, the memory access request is not accepted and a re-execution is requested (S14).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device which is connected to a combined type multiprocessor system via a split type bus and performs an atomic operation essential for a synchronous operation using a semaphore / lock variable.

[0002]

2. Description of the Related Art In recent years, a multiprocessor system in which a plurality of processors are prepared in a system and each processor is combined has been generally used. Such a multiprocessor system is configured by tightly coupling a relatively small number of processors, reducing the load on each processor by allocating a plurality of functions to each processor, and reducing the processing capacity by the simultaneous parallel operation of each processor. We are improving.

[0003] Here, there are various methods for connecting the processors, and one of them is a bus connection method in which the processors are connected by a bus. In such a bus connection system, a main memory that can be arbitrarily accessed by each processor is prepared on a bus, and each processor accesses the main memory. However, in a bus-coupled multiprocessor system, since a plurality of independently operating processors access a shared system bus, an arbitration function (arbitration function) is used to prevent trouble from occurring due to bus access contention.
Is generally provided.

On the other hand, a tightly-coupled multiprocessor system sharing a main memory requires a synchronous operation between the processors. Thus, in such a multiprocessor system, a variable called a semaphore / lock variable is placed on the main memory to perform a synchronization operation between the processors. For example, if several bytes in a certain area of the main memory are used as a series of meaningful data, the data will not be meaningful if a part of it is rewritten, and if the data is used elsewhere, Is bad. Therefore, a variable called a semaphore / lock variable is placed in the main memory, and a processor that intends to rewrite a series of data accesses this variable and confirms that the series of data is not being rewritten. / Rewrite lock variable and declare that data is being rewritten. Therefore, when performing a synchronization operation between the processors, a series of operations of confirming and rewriting the semaphore / lock variable stored in the main memory are required. Such a series of operations is called an atomic operation (indivisible operation).

However, in an atomic operation required for a synchronous operation between processors using a semaphore / lock variable, two operations are required for a main memory for confirmation and rewrite.
If an operation is performed on the same semaphore / lock variable between operations, there is a risk that data consistency may be lost.
For this reason, conventionally, a contrivance has been made so that two operations on the main memory are inseparable operations, so that operations of other processors do not intervene between the two operations. For example, Japanese Patent Laying-Open No. 3-74759 discloses an invention in which the bus is locked between two operations on the main memory so that another processor does not operate on the main memory during that time.

[0006]

In recent years, in a tightly-coupled multiprocessor system, a split-type bus in which addresses and data are separated from each other is often used in order to reduce the occupancy of the bus by the processor. Is coming. However, in atomic operations used for synchronous operations,
For example, as disclosed in Japanese Patent Application Laid-Open No. 3-74759, it is necessary to prevent another processor's operation from intervening between two operations on the main memory by a technique such as a bus lock. Therefore, during the atomic operation, the bus is occupied by one processor, and the use of the bus by other processors is prohibited. Therefore, there is a problem that the advantage of the split-type bus cannot be utilized in a system in which synchronous operations are frequently used.

[0007]

According to the first aspect of the present invention,
In a storage device connected to a multiprocessor system via a split-type bus and performing an atomic operation indispensable for a synchronous operation using a semaphore / lock variable,
Decoding means for generating a pseudo memory space so that the real memory appears to overlap in the address space which does not overlap with the real memory space; and a pseudo memory access request from the bus master fetched via the bus to the real memory space. Identification means for identifying whether the request is for the memory space, and in the normal mode, when the memory access request is identified as for the pseudo memory space, the memory access request is recognized as an atomic operation start access request, and the operation is performed in the atomic operation mode. A first recognition unit for changing the mode, a holding unit for storing and holding an identifier of a bus master that has made an atomic operation start access request, and an holding unit for storing an identifier of a bus master making a memory access request in the atomic operation mode. If it matches the identifier, the memory access request A second recognizing means for recognizing an atomic operation end access request and returning the operation mode to the normal mode, and a memory access request in the atomic operation mode when the memory access request does not meet the recognition condition of the second recognizing means. Prohibiting means for requesting re-execution of the access request without receiving the request. Therefore, during the atomic operation mode in which the atomic operation start access request is recognized and executed, a memory access request of a processor or a device other than the processor that made the atomic operation start access request is rejected, and the atomic operation is performed correctly. In this case, since the bus is not locked, the use of the bus of another processor or a bus master other than the processor is not impaired, and the advantage of the split-type bus is fully utilized.

According to a second aspect of the present invention, in the first aspect of the invention, the prohibiting means determines whether the bus master requesting the memory access is a processor, and if it is determined that the bus master is not a processor, permits the memory access. .
Therefore, even in the atomic operation mode, the memory access of the bus master other than the processor becomes possible, and the memory is used efficiently.

According to a third aspect of the present invention, in the first aspect of the present invention, the prohibiting means does not accept the memory access request only when the memory access request is for a pseudo memory space. Unless the memory access request is for the pseudo memory space, the data stored and held in the pseudo memory space is not rewritten, so that there is no need to reject the memory access request. Therefore, even in the atomic operation mode, memory access to the real memory space becomes possible, and the memory is used efficiently.

According to a fourth aspect of the present invention, in the first aspect of the present invention, the holding means stores and holds a real memory address corresponding to the access address of the atomic operation start access request, and the prohibiting means stores the real memory address corresponding to the access request. The memory access request is not accepted only for the real memory address corresponding to the access address of the atomic operation start access request. Unless the memory access request is for the pseudo memory space, the data stored and held in the pseudo memory space is not rewritten, so that there is no need to reject the memory access request. Therefore, in the invention according to claim 4, in the atomic operation mode, a memory access request that becomes a memory access request to the pseudo memory space, that is, a memory access request of a real memory address corresponding to the access address of the atomic operation start access request Other memory access requests are allowed. Thereby, the memory is used efficiently.

According to a fifth aspect of the present invention, in the first aspect of the invention, a timer means for counting a timeout period from when an atomic operation start access request is made to when an atomic operation end access request is made, and After that, there is provided forcible termination means for forcibly terminating the atomic operation mode. This prevents the system from going down which can be caused by the unnecessary operation of the atomic operation being performed unnecessarily for a long time due to an inappropriate memory access request.

According to a sixth aspect of the present invention, there is provided a storage device which is connected to a multiprocessor system via a split-type bus and performs an atomic operation indispensable for a synchronous operation using a semaphore / lock variable. Decoding means for generating a pseudo memory space so that real memories appear to overlap in non-overlapping address spaces, and identifying an access address space of a memory access request fetched via a bus to perform memory read access to the pseudo memory space An atomic operation identifying means for identifying the request as a read-modify-write access request;
Reads the real memory address corresponding to the access address of the memory read access request identified as the read-modify-write access request, writes a non-zero value to the real memory address, and sends the value to the bus master that issued the memory read access request. Return means for returning the read data. Therefore, the test and set for the memory is executed by a simple process.

[0013]

FIG. 1 shows a first embodiment of the present invention.
A description will be given based on FIG.

FIG. 1 is a block diagram of the electrical connection of each part. The storage device 1 of the present embodiment is connected to a multiprocessor system (not shown) via a split-type system bus 2 as a bus. Specifically, it is connected to the system bus 2 so as to communicate information mutually via the system bus I / F 3 and to communicate information one-way via the response control unit 4 having a processor configuration. The system bus I / F 3 receives an access request from the system bus 2 and transmits data, control information, an access address, and a master ID to each unit in the storage device 1. here,
“Data” refers to RA which is a main part of the storage device 1.
The "control information" is information to be stored and held in the M5. The "control information" is information for specifying the control content for the RAM 5, the "access address" is the address information for specifying the access area for the RAM 5, and the "master". “ID” is an identifier of the bus master, that is, the identity information. The RAM 5 is a DRAM or an SDRA
M.

A memory control unit 6 having a processor configuration is provided in the storage device 1. This memory control unit 6 stores
A memory control signal is transmitted to the AM 5 to control the RAM 5. That is, the memory control unit 6 receives a control signal and an access address from the system bus I / F 3, generates a memory control signal based on these signals, and transmits this to the RAM 5. At this time, the access address from the system bus I / F 3 is temporarily taken into the decoder 7 as decoding means. This decoder 7
R whether access address signal is for real memory space
An address space that does not overlap with the real memory space in the AM 5 is transmitted to the memory control unit 6 while distinguishing whether the real memory is for a pseudo memory space generated so as to appear to overlap (see FIG. 2). That is, the decoder 7 is connected to the system bus 2
And outputs a decoded signal corresponding to the access space information assigned to the upper bit of the memory access signal from the bus master taken in from the system bus I / F3 through the interface as a real memory signal or a pseudo memory signal. Then, the memory control unit 6 receiving this discriminates whether the memory access signal is a signal for the real memory space or a signal for the pseudo memory space (identification means), and specifies an access address of the RAM 5 according to each access address signal. Here, the “pseudo memory space” is an address space for realizing an atomic operation.

The storage device 1 also has a system bus I / F
A holding unit 8 for temporarily storing the master ID output from the storage unit 3, a comparator 9 for comparing the master ID output from the system bus IF3 with the master ID temporarily stored in the holding unit 8, and a processor. And a master ID table 10 for identifying whether or not the bus master is a processor based on the master ID output from the system bus IF3. The master ID table 10 includes a table for storing the ID code of each processor, and a master ID output from the system bus IF3.
And a circuit for determining whether the ID code stored in the table matches or not.

The operation of each unit in the storage device 1 is as follows. The storage device 1 takes the logical product of an output signal from the master ID table 10 indicating that the processor is a processor and an output signal from the decoder 7 indicating that an access request to the real memory space has been made, by an AND gate A, The result access request signal 1 is transmitted to the response control unit 4. That is, the access request signal 1 is a reaccess request signal output when an access request to a real memory address is made by the processor.

The storage device 1 transmits an atomic operation start signal to the response control unit 4 when an atomic operation start access request is made and an access address signal for a pseudo memory space is output from the decoder 7. In response, the response control unit 4 of the processor configuration shifts the operation mode of the storage device 1 from the normal mode to the atomic operation mode. Thereby, the function of the first recognition unit is executed.

In the atomic operation mode, the master ID of the bus master making the atomic operation start access request is temporarily stored in the holding unit 8, and the master ID of the bus master making the memory access request later is the master ID temporarily stored in the holding unit 8. The comparator 9 compares the bus master requesting the memory access with the bus master requesting the atomic operation start request and the output from the decoder 7 indicating the request for access to the pseudo memory space. The logical product with the signal is taken by the AND gate B, and the resulting atomic operation end signal is sent to the response control unit 4.
Sent to. In response, the response control unit 4 returns the operation mode of the storage device 1 from the atomic operation mode to the normal mode. Thereby, the function of the second recognition unit is executed.

Further, when a comparison result is output from the comparator 9 indicating that the bus master is not the same as the bus master having issued the atomic operation start access request, the decoder 7 indicating the output signal and the access request to the pseudo memory space.
Is ANDed with the output signal from the AND gate C, and
The resulting access request signal 2 is transmitted to the response control unit 4. That is, the access request signal 2 is a re-access request signal output when the bus master requesting access to the pseudo memory space is different from the bus master requesting the atomic operation start access request. Thereby, the function of the prohibition means is executed.

As described above, in the storage device 1 according to the present embodiment, the response control unit 4 performs various processes in response to various signals, and thereby, the first recognition unit, the second recognition unit, and the prohibition. Each function of the means is performed. The response control unit 4
Further, it has a function of outputting response signals corresponding to various signals to the system bus 2.

FIG. 3 is a flowchart showing the flow of operation in the storage device 1. First, when there is a memory access request from the bus master via the system bus 2, the type of the access space is determined by the memory control unit 6 based on the output of the decoder 7 (step 1). That is, it is determined whether the access space is the real memory space, the pseudo memory space, or the other. The input information to the decoder 7 that is the basis for this determination is access space information assigned to the upper bits of the access address signal included in the memory access signal from the bus master.

If the access space is neither the real memory space nor the pseudo memory space, the memory access request is ignored (step 2). If the access space is the real memory space, an access address signal for the real memory space is output to the memory control unit 6, and the memory control is performed by the control operation of the memory control unit 6 (step 3). At this time,
If it is the processor that makes the memory access request, A
The access request signal 1 from the ND gate A is
However, if the operation mode at this time is the normal mode, the response control unit 4 does not output the re-access request and sends a response signal indicating that the memory control has been performed to the system bus 2 (step 4).

When the access space is the pseudo memory space, the same memory control and response operations as those in steps 3 and 4 when the access space is the real memory space are performed (steps 5 and 6). The master ID output from the system bus I / F3 is temporarily stored in the holding unit 8 (step 7). This master ID is the ID of the processor that is the bus master that has issued the atomic operation start access request. At the same time as these processes, the atomic operation start signal output from the decoder 7 is input to the response control unit 4, and the entire operation mode shifts to the atomic operation mode. Here, the fact that the memory access signal from the bus master is for the pseudo memory space means that an atomic operation required for a synchronous operation of a plurality of processors will be performed.

In the atomic operation mode, first, when there is a memory access request from the bus master via the system bus 2 (step 8), the type of the access space is determined by the memory control unit 6 based on the output of the decoder 7 (step 8). 9). That is, it is determined whether the access space is the real memory space, the pseudo memory space, or the other. The input information to the decoder 7 that is the basis for this determination is access space information assigned to the upper bits of the access address signal included in the memory access signal from the bus master.

If the access space is neither the real memory space nor the pseudo memory space, the memory access request is ignored (step 10). If the access space is a real memory space, the bus master requesting the memory access is not a processor (step 1).
1) The access address signal for the real memory space is output to the memory control unit 6, and the memory control is performed by the control operation of the memory control unit 6 (step 12), and the response control unit 4
Is sent to the system bus 2 (step 4). On the other hand, if it is determined in step 11 that the processor makes a memory access request, the response control unit 4 outputs a re-access request signal,
That is, a retry response is sent to the system bus 2 (step 14). Here, whether or not the processor issues a memory access request is recognized based on whether or not the access request signal 1 from the AND gate A is output to the response control unit 4. That is, the AND gate A outputs the access request signal 1 only when the processor makes a memory access request.
When the response control unit 4 receives the access request signal 1, the bus master is a processor,
Otherwise, the bus master is not a processor.

If the access space is a pseudo memory space, the master ID is compared (step 15). That is, it is determined whether the bus master requesting access to the pseudo memory space is the same as the bus master requesting the atomic operation start access request. More specifically,
Since the master ID of the bus master that has made the atomic operation start access request is temporarily stored in the holding unit 8, the comparator 9 compares this with the master ID of the bus master that makes an access request to the pseudo memory space. The result is A
It is transmitted to the response control unit 4 as an output of the ND gate B or C, and the response control unit 4 determines the identity of the bus master. That is, if the master IDs match, an atomic operation end signal is output from the AND gate B to the response control unit 4, and if the master IDs do not match, the AND gate C
The access request signal 2 is output to the response control unit 4.

If the result of the comparison of the master IDs in step 15 is that the master IDs are not the same in step 16, the response control unit 4 responds to the access request signal 2 from the AND gate C in step 14. Performs a retry response process. On the other hand, if it is determined in step 16 that the master IDs are the same, memory control is performed by the memory control unit 6 (step 17), and the response control unit 4
A response to that effect is sent to the system bus 2 (step 18). Then, the operation mode returns to the normal operation mode.

As described above, according to the storage device 1 of the present embodiment, during the atomic operation mode in which the atomic operation start access request is recognized and executed, the processor or the device other than the processor or the device that made the atomic operation start access request is used. Is rejected, and the atomic operation is performed correctly (see step 16). In this case, since the system bus 2 is not locked,
The use of the system bus 2 of another processor or a bus master other than the processor is not prohibited, and therefore, the advantages of the split type bus are fully utilized. Further, even in the atomic operation mode, the memory access of the bus master other than the processor becomes possible, and the memory 5 is used efficiently (see step 11).

FIGS. 4 and 5 show a second embodiment of the present invention.
It will be described based on. The same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted (the same applies hereinafter).

As shown in the block diagram of FIG. 4, in the present embodiment, the response control unit 4 has a timer 2 as timer means.
1 is provided. This timer 21 is used by the response control unit 4
And controls the response control unit 4 to measure a timeout period from when the atomic operation start signal is input to when the atomic operation end signal is input. When the timer 21 times out, the response control unit 4 forcibly terminates the atomic operation mode, and the function of the forcibly terminating unit is executed here.

Also, the decoder 7 is connected to the system bus IF3.
Is provided for temporarily storing an access address transmitted and output to the system bus.
A comparator 23 is provided for comparing the access address transmitted from F3 to the decoder 7 and the access address temporarily stored in the holding unit 22. Then, the AND of the output of the comparator 23 and the access address of the real memory space output from the decoder 7 is transmitted to the response control unit 4 as the access request signal 1 from the AND gate A. Therefore, in the present embodiment, the master ID table 10 is not provided.

FIG. 5 is a flowchart showing the flow of the processing. The same steps as those in the flowchart shown in FIG. First, after it is determined that the access space in the memory access request of the bus master is access to the pseudo space, in step 7 performed following the memory control (step 5) and the response (step 6), the master ID is held. In addition, the corresponding real memory address is held. That is, even if the access address is interpreted as a pseudo memory address, the decoder 7
Is an actual memory address, and this address is temporarily stored and held in the holding unit 22.

Subsequently, when the operation mode shifts to the atomic operation mode, the timer 21 measures a timeout period, and when the timeout occurs, the atomic operation mode is forcibly terminated and returns to the normal mode (step 21). This prevents the system from going down which can be caused by the unnecessary operation of the atomic operation being performed unnecessarily for a long time due to an inappropriate memory access request.

Subsequently, as a result of the determination of the access space in step 9, the processing when the memory access request is made for a space other than the real memory space and the pseudo memory space (step 10) and the processing for the pseudo memory space The processing (steps 15 to 18) when the processing is performed is not different from that of the first embodiment, and the description thereof is omitted.
On the other hand, when a memory access request is made to the real memory space, a comparison process is performed between the access address at that time and the access address temporarily stored in the holding unit 22 in step 7 (step 22). That is, an AND gate which is a logical product of a comparison result by the comparator 23 between the access address at that time and the access address temporarily stored in the holding unit 22 in step 7 and a memory access request to the real memory space output from the decoder 7 By transmitting and outputting the access request signal 1 from A to the response control unit 4, the response control unit 4 makes the same / non-identical determination (step 23). Here, the fact that the two access addresses are the same means that the memory access request for the real memory address space transmitted during the atomic operation mode is an access to the currently used pseudo memory space. Therefore, if the two access addresses match, a retry response (step 1)
4) If they do not match, memory control (step 12) is performed. As a result, memory access requests other than the memory access request of the real memory address corresponding to the access address of the atomic operation start access request are allowed, and thereby the memory is used efficiently.

FIGS. 6 and 7 show a third embodiment of the present invention.
It will be described based on. In the present embodiment, as shown in the block diagram of FIG. 6, the system bus 3, the response control unit 4, the RA
An M5, a memory control unit 6, and a decoder 7 are provided, and the contents and connection state of these units are the same as in the first embodiment. The configuration includes a system bus I / F3 to RAM
5 is different from the first embodiment in that a holding unit 31 is interposed between the data line of the data transmitted to 5 and the memory control unit 6, and a value other than zero is written in the holding unit 31. In the storage device 1 of the present embodiment, as a function executed by the memory control unit 6, when a read access request is made to the pseudo memory space, a read operation is performed on a real memory address corresponding to the access address. Subsequently, a write operation is performed on the same address with write data having a non-zero numerical value temporarily stored in the holding unit 31, for example, “−1”.

FIG. 7 is a flowchart showing the flow of the processing. In the present embodiment, after receiving the memory access, steps 1 to 4 are not different from those of the first embodiment, and are characterized in that the write and set for the RAM 5 is executed. That is, if it is determined in step 1 that the access space of the memory access request is a pseudo space, and if it is determined in step 31 that the memory access request is a read-modify-write access request (atomic operation identification means), Memory control for realizing a normal read operation to the real memory address corresponding to the access address is performed (step 3).
2). Then, a response is returned to the bus master requesting the access, and the function of the return means is executed (step 33).
Subsequently, memory control for realizing a write operation of specific write data to the same address, for example, "-1" is performed (step 34). On the other hand, if it is determined in step 31 that the memory access request is a write access request to the pseudo memory space, error processing is performed (step 5). As described above, according to the present embodiment, the write and set for the RAM 5 is executed by a simple process.

[0038]

According to the first aspect of the present invention, a memory access request from a bus master fetched via a bus is identified for a real memory space or a pseudo memory space. When the memory access request is identified as a pseudo memory space, the memory access request is recognized as an atomic operation start access request, the identifier of the bus master that has made the atomic operation start access request is stored and stored. If the identifier of the bus master performing the operation matches the stored identifier, the memory access request is recognized as an atomic operation end access request; otherwise, the access request is re-executed without accepting the memory access request. During the atomic operation mode, Atomic operation can be performed correctly by rejecting a memory access request from a processor or device other than the processor that issued the access operation start access request, and in this case, the bus is not locked, so other processors and other processors The use of the bus master can be ensured and the advantages of the split type bus can be fully utilized.

According to the second aspect of the present invention, it is determined whether or not the bus master requesting the memory access is a processor, and if it is determined that the bus master is not the processor, the memory access is permitted. The memory access of the bus master becomes possible, and the memory can be used efficiently.

The third aspect of the present invention focuses on the fact that the data stored in the pseudo memory space cannot be rewritten unless the memory access request is for the pseudo memory space. , The memory access request is not accepted only during the atomic operation mode, so that the memory can be accessed in the real memory space even in the atomic operation mode, and the memory can be used efficiently.

The fourth aspect of the present invention focuses on the fact that data stored and held in the pseudo memory space cannot be rewritten unless the memory access request is for the pseudo memory space, and the access address of the atomic operation start access request is specified as the access address. Since the corresponding real memory address is stored and held, and the memory access request is not accepted only when the memory access request corresponds to the real memory address corresponding to the access address of the atomic operation start access request, the pseudo memory is used in the atomic operation mode. A memory access request other than a memory access request that is a memory access request for a space is permitted, and thereby the memory can be used efficiently.

According to a fifth aspect of the present invention, there is provided a timer means for counting a time-out period from when an atomic operation start access request is made to when an atomic operation end access request is made, and after the time-out time has elapsed, the atomic operation mode is forcibly set. And a forced termination unit for terminating the operation. Therefore, it is possible to prevent the system from being shut down which can be caused by the unnecessary operation being performed unnecessarily for a long time due to an inappropriate memory access request.

According to a sixth aspect of the present invention, a pseudo memory space is generated so that a real memory appears to overlap in an address space which does not overlap with a real memory space, and an access address of a memory access request fetched via a bus is generated. Real memory corresponding to the access address of the memory read access request identified as a read-modify-write-access request by identifying a memory read access request to the pseudo memory space as a read-modify-write-access request Read the address, write a non-zero value to the real memory address,
Since the read data is returned to the bus master that has made the memory read access request, the test and set for the memory can be executed by simple processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a schematic diagram conceptually showing a memory space.

FIG. 3 is a flowchart showing a flow of operation.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a flowchart showing a flow of operation.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is a flowchart showing a flow of operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Storage device 2 Bus (system bus) 7 Decoding means, identification means 8 Holding means (holding part) 21 Timer means (timer)

Claims (6)

[Claims] 1. A storage device which is connected to a multiprocessor system via a split-type bus and performs an atomic operation indispensable for a synchronous operation using a semaphore / lock variable. Decoding means for generating a pseudo memory space so that memories appear to be duplicated, and identification means for identifying whether a memory access request from a bus master fetched via a bus is for a real memory space or a pseudo memory space First normal recognition means for, in the normal mode, recognizing the memory access request as an atomic operation start access request when the memory access request is identified as a request for the pseudo memory space, and shifting the operation mode to the atomic operation mode; The bus master that has issued the atomic operation start access request Holding means for storing and holding the identifier; and in the atomic operation mode, when the identifier of the bus master making the memory access request matches the identifier held in the holding means, the memory access request is recognized as an atomic operation end access request, and the operation is performed. A second recognition unit for returning the mode to the normal mode; and a request for re-executing the access request when the memory access request does not meet the recognition condition of the second recognition unit in the atomic operation mode. And a prohibition unit for performing the operation. 2. The storage device according to claim 1, wherein said prohibiting means determines whether or not the bus master requesting the memory access is a processor, and permits the memory access when it is determined that the bus master is not a processor. 3. The storage device according to claim 1, wherein the prohibition unit does not accept the memory access request only when the memory access request is for a pseudo memory space. 4. The holding means stores and holds a real memory address corresponding to an access address of an atomic operation start access request, and the prohibiting means stores a real memory address corresponding to an access address of the atomic operation start access request. 2. The storage device according to claim 1, wherein the memory access request is not accepted only when the memory access request is received. 5. A timer means for counting a timeout period from when an atomic operation start access request is made to when an atomic operation end access request is made, and a forced termination means for forcibly terminating the atomic operation mode after the timeout time has elapsed. The storage device according to claim 1, comprising: 6. A storage device connected to a multiprocessor system via a split-type bus and performing an atomic operation indispensable for a synchronous operation using a semaphore / lock variable. Decoding means for generating a pseudo memory space so that memories appear to be duplicated; and an access address space of a memory access request taken in via a bus, and a read-modify / read-modify request for a memory read access to the pseudo memory space. Atomic operation identification means for identifying a write access request, and a real memory address corresponding to the access address of a memory read access request identified as a read-modify-write access request, and a non-zero value as a real memory address. When you write A storage device, comprising: return means for returning read data to a bus master that has made a memory read access request.