JPH10161600A - Liquid crystal display controller - Google Patents

Abstract

(57) [Summary] To provide a liquid crystal display control device capable of responding to various specifications of an input interface and an output interface with a liquid crystal display panel. A digital control unit (122) for processing display data obtained by converting an input video signal into a digital value, the digital control unit is capable of serial / parallel conversion of an internal input / output display data bus in dot units. Interface control means 12
3, 130 are provided. The digital control unit 122 internally performs processing in 2-dot parallel. On the input side, the interface control means converts dot serial display data into 2-dot parallel display data or converts 2-dot parallel display data into 2 dot parallel display data. There is a means for switching between dot parallel input and output. On the output side, it is switched between 2-dot parallel display data as it is or 2-dot parallel output according to the specifications of the liquid crystal panel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display control device.

[0002]

2. Description of the Related Art Conventionally, as a liquid crystal display control device having an inexpensive controller, for example, Japanese Patent Application Laid-Open No. 6-186935 has been proposed.
As disclosed in Japanese Unexamined Patent Application Publication No. H10-204, an analog C of a computer is added to a controller of a flat panel display.
Using only the signal input from the RT terminal,
RT can be easily replaced and used, and a clock generating means and a means for latching a display signal with this clock signal are used to obtain a display signal and a clock signal synchronized with each other with an easy configuration. 2. Description of the Related Art There is known a liquid crystal display system technology in which the frequency of a clock signal is specified so that it can be easily replaced with a CRT and used.

FIG. 20 and FIG.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration example of a liquid crystal display system disclosed in Japanese Patent No. 6935 and a schematic configuration diagram of a liquid crystal display control circuit.

In FIGS. 20 and 21, 1601 is a computer main body, 1602 is analog R, G, B terminals, 1603 is a flat panel display, 1604 is a control circuit, 1701 is an A / D converter, 1702 is a latch, 1703 denotes a flat panel display control unit, 1704 denotes an oscillation unit, and 1705 denotes a frequency dividing unit.

FIG. 22 is a timing chart for explaining the operation of the prior art liquid crystal display system.

In FIGS. 20, 21, and 22, a terminal for an analog CRT is provided as a terminal for a display terminal of a computer. When connecting a flat panel display, it is easiest to use this analog CRT terminal, and the user can use it simply by replacing the CRT and connecting.

In the timing chart of FIG. 22, image signals of R, G, and B are input from an analog R, G, and B terminal 1602 to an A / D converter 1701 (FIG. 22).
(A)), the signal is converted into a digital signal corresponding to the display color by the A / D converter 1701 (FIG. 22 (b)). A clock (f: as an example, f = 2fc) having a higher frequency than the dot clock (fc) of this signal is used (FIG. 22).
(C)), latch is performed by the latch unit 1702. Here, the image signal is synchronized with the clock signal (f) (FIG. 22).
(D)). The clock signal (f) synchronized with the image data is frequency-divided by the frequency dividing unit 1705, so that a clock signal synchronized with the image data can be obtained. (FIG. 22 (e)). These image data and clock signals, and analog R, G, B terminals
Using the horizontal / vertical synchronization signals input from 1602, a flat panel display control unit 1703 creates a control signal for displaying a flat panel.

By using a comparator as the A / D converter 1701 and a D / A converter as a reference voltage, analog image data for gradation display can be digitally set at an arbitrary voltage level. become. Further, a commonly used A / D converter can be used. As the latch unit 1702, an I
C can be used (for example, 74AC74,
General-purpose logic elements such as 74AC112 can be used.) The oscillating frequency (f) of the oscillating unit 1704 is not particularly limited as long as it is higher than the frequency of an image signal from a computer or the like, but is preferably in a range of 2fc ≦ f ≦ 4fc. The frequency divider 1705 includes a flip-flop (74AC161, 74AC1 as an example) for performing a counter or toggle operation.
General-purpose logic IC 63 or the like can be used.

[0009]

However, in the prior art described in the above-mentioned publication, a liquid crystal display system that can be easily replaced with a CRT and used can be realized, but the digital input display data after A / D conversion has been realized. However, there is no function of holding the image data, and it is difficult to perform the scaling process according to the size of the liquid crystal panel depending on the resolution (display size) of the video signal.

[0010] Further, in the above-mentioned prior art, since various adjustment functions for enabling the display of the image displayed on the liquid crystal panel with the best image quality are not provided, the data conversion accuracy of the A / D converter is reduced. There is a problem that an image with poor image quality is displayed due to factors such as constant variation of each part, and an image with image quality corresponding to the user's preference cannot be displayed.

Further, the above-mentioned prior art states that the interface with the CRT is compatible. However, the interface between the analog control unit and the digital control unit in the liquid crystal display control device to which the present invention is applied is described. However, when parallel processing is not possible, such as when the input video signal has a high resolution, high-speed operation is required, and there are problems such as increased power consumption and increased heat generation.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display control device capable of complying with various specifications of an input interface and an output interface with a liquid crystal display panel.

[0013] Another object of the present invention is to provide an apparatus for controlling the offset, amplitude level, phase difference with the horizontal synchronizing signal, and the like of display data on the liquid crystal panel so that video data displayed on the liquid crystal display panel has the best image quality. To provide a liquid crystal display control device capable of displaying an adjustment menu at the same time and making it easy to make adjustments and automatically adjusting these various adjustments by detecting the current state of the display data. It is in.

Still another object of the present invention is to realize by hardware the cycle measurement of horizontal and vertical synchronizing signals for determining the resolution of display data given from a computer, thereby realizing a microcomputer. It is an object of the present invention to provide a liquid crystal display control device which can reduce the burden on the resolution determination processing by the microcomputer (the cycle time of the synchronization signal by the microcomputer becomes unnecessary) and can adopt a low-function and inexpensive microcomputer.

Still another object of the present invention is to provide a liquid crystal display control device capable of implementing high-density mounting, reducing power consumption, reducing heat generation, and reducing costs by implementing the above-mentioned various functions in an LSI.

Still another object of the present invention is to provide a memory for temporarily storing digital display data converted by the A / D converter, and to store the digital display data stored in the memory in accordance with the resolution of the input display data. The present invention is to provide a liquid crystal display control device which carries out arithmetic processing on the data of (1) and (2) to display and output an image having a screen size matching the screen size of the liquid crystal panel.

[0017]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the present invention relates to a liquid crystal display control device used in a liquid crystal display device for displaying a video signal from a personal computer or the like, wherein the digital control device processes display data obtained by converting an input video signal into a digital value. And a digital control unit including an interface control means capable of serial / parallel conversion of an internal input / output display data bus in dot units. This makes it possible to support various specifications of the input interface and the output interface with the liquid crystal display panel.

In this device, preferably, the digital control unit internally performs processing in two-dot parallel, and the interface control means converts the dot serial display data into two-dot parallel display data on the input side. Or a means for switching between input of two-dot parallel display data and two-dot parallel display data. On the output side, two-dot parallel display data is directly output in two-dot parallel according to the specification of the liquid crystal panel. There is means for switching whether to output in dot serial.

When the display data is handled in units of two dots, there is a problem in that a shift of one dot in the horizontal direction occurs, as will be described later. This problem can be solved by providing the following means. .

That is, the digital control section has an even / odd conversion control means for exchanging display data of even-numbered dots and display data of odd-numbered dots and delaying display data of odd-numbered dots by one dot.

According to the present invention, in a display device for displaying a video signal from a personal computer or the like on a liquid crystal panel, various display sizes (resolutions) of the input video signal are scaled so as to match the display size of the liquid crystal panel. In addition to performing the processing, an adjustment for displaying the display data with the image quality desired by the user, and an on-screen display display for displaying an adjustment menu on the screen for easily performing the adjustment, It is designed to detect various states and perform automatic adjustment for automatically setting the best image quality. By making these liquid crystal display control functions LSI, high-density mounting, space saving, low power consumption It is possible to reduce power consumption and cost.

As scaling control means for matching the various display sizes (resolutions) of the video signal with the display size of the liquid crystal panel, the digital video data converted by the A / D converter is temporarily converted into a unit of horizontal cycle. The data is stored in the memory and read out in the next horizontal cycle.
The arithmetic processing is performed on the digital video data from the conversion unit, and the number of display data is increased in both the horizontal and vertical directions, so that the display is performed in accordance with the display size of the liquid crystal panel (here, the display of the liquid crystal panel is performed). Various display sizes (resolutions) of the input video data are smaller than the sizes, and therefore, scaling is performed by enlarging processing).

As an adjustment control means for obtaining the best image quality of display data, an on-screen display for displaying an adjustment menu on a liquid crystal panel screen is used, and various characters (fonts) for displaying the adjustment menu are used.
And a code memory for storing an address for the character memory and color information of the character. In the adjustment menu display area, the adjustment menu data read out of these memories is used to display the image from a personal computer or the like. The data is superimposed and displayed on the data. Also,
Regarding the various adjustments, there is an automatic adjustment function that detects various states of the current video data and automatically sets the state to a default value, in addition to a method that is individually performed by a user according to the adjustment menu. For the automatic adjustment, a maximum value / minimum value of data and a position where the maximum value / minimum value is detected with respect to the digital video data input from the A / D conversion unit.
Furthermore, by detecting the start / end position of the video data, transferring the detected data to the microcomputer, the microcomputer calculates a difference from a default state, and performs resetting to correct the difference data. It is possible to automatically adjust offset / gain adjustment, phase adjustment, horizontal / vertical position adjustment and the like for display data.

[0025]

An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an overall configuration diagram showing an example of a display system using the technology of the present invention, in which the technology of the present invention is located in a digital display control unit 122.

In FIG. 1, reference numeral 101 denotes a vertical synchronizing signal output from a personal computer, a work station, or the like; 102, a horizontal synchronizing signal; 103, analog R, G, B display data; 104, an analog display control unit;
, A vertical synchronizing signal (VSYNC) after polarity control; 107, a horizontal synchronizing signal (HSYNC); 108, a phase adjusting circuit for performing the same based on the horizontal synchronizing signal 107; Is the phase adjustment clock, 110
Is a PLL circuit based on the phase adjustment clock, 111
Is a dot clock whose phase has been adjusted with the phase adjustment clock 109 by the PLL circuit 110, 112 is an offset adjustment circuit, 113 is offset adjustment data, 114 is a gain adjustment circuit, 115 is gain adjustment data, 116 is analog R, G , B
A pedestal adjustment circuit for adjusting the display data 103 by using the offset adjustment data 113, 117 is pedestal-adjusted R, G, B analog display data, 118 is a video amplifier circuit, and 119 is an amplified R, G, B analog display. Data, 1
Reference numeral 20 denotes an A / D converter circuit; 121, digital R, G, B digital display data; and 122, a digital display control unit according to the present invention. Digital display control unit 122
Inside, 123 is a display input control circuit, 124 is a multi-scan control circuit for enlarging / reducing digital R, G, B display data, 125 is R, G, B digital display data that has been enlarged or reduced, Reference numeral 126 denotes a multi-color control circuit for multi-color display of R, G, B digital display data, 127, R, G, B digital display data subjected to multi-color processing, and 128, display on the screen. An adjustment menu display control circuit for controlling the adjustment menu; 129, adjustment menu display data output from the adjustment menu display control circuit; 130, R / G / B digital display data in parallel /
A display output control circuit for serial conversion and output; 131, an automatic adjustment control circuit for automatically setting output display data to a prescribed image quality and display position based on R, G, B digital display data; 132, display Digital R output to panel
G and B output display data 133 are an output synchronization signal for controlling the timing of the display panel, a dot clock, and a blanking signal. 134 is a microcomputer for performing various settings of the entire display system, 135 is a data bus connecting between the microcomputer 134 and the digital display control unit 122, 136 is display control unit setting data output from the microcomputer, 137 is an external system A serial communication control bus for performing various controls, 138 is adjustment key input data for inputting various adjustment instructions by a user, and 139 corresponds to input display data of various resolutions from the personal computer or a workstation or the like. Parameter storage memory for storing control data, 140 is a memory bus, 141 is a crystal oscillator serving as an operation reference of the digital display control unit 122, 142 is an oscillation clock, 143 is the microcomputer clock, 144 is a cycle measurement control unit, 145 Denotes a microcomputer clock control unit.

The outline of the operation of the display system using the present invention will be described below with reference to FIG.

First, a vertical synchronizing signal 101, a horizontal synchronizing signal 102 and analog R, G, B display data 103 are inputted from a personal computer, a work station or the like. The input synchronization signals 101 and 102 are input to the polarity reversal and synchronization separation circuit 105, converted into a polarity according to the display control setting data 136 from the microcomputer 134, and output. Also,
When the input display data is in the composite format, the synchronization separation control is performed using the G color display data 103. The polarity-controlled synchronization signal is output to the microcomputer 134 and the digital display control unit 122, and the horizontal synchronization signal 107 is also output to the phase adjustment circuit 108. In the phase adjustment circuit 108, the horizontal synchronizing signal
The phase adjustment clock 109 synchronized with 107 is output to the PLL circuit 110 to reproduce the dot clock 111. Analog R,
The G and B display data 103 is input to a pedestal adjustment circuit 116 and becomes pedestal clamp and offset adjusted display data 117 in accordance with the offset adjustment data 113 output from the offset adjustment circuit 112. Amplified display data 119 amplified according to gain adjustment data 115 output from 114
Is input to the A / D converter circuit 120. The A / D converter circuit 120 converts the input analog R, G, B display data 119 into digital data at the timing of the dot clock 111, and outputs the digital R, G, B display data 121 to the digital display control unit 122. In the present embodiment, the digital R, G, B display data 121 has a width of 16 bits for each of R, G, B, and a total of 48 bits.
Each 16-bit data is an even-numbered data (ID [7:
0]) and odd data (ID [15: 8]). Each of the even data (ID [7: 0]) and the odd data (ID [15: 8]) forms one dot.

The adjustment values in the various adjustment circuits in the analog display control unit 104 are output from the microcomputer 134 to adjustment data 136.
Output as

In the digital display control unit 122, the synchronization signals 106 and 107 from the analog display control unit 104, the dot clock 11
1. Digital R, G, B display data 121 and microcomputer 13
The control is performed by the adjustment data 136 from 4 and the oscillation clock 142 which is the operation reference of the crystal oscillator 141. The digital R, G, and B display data 121 is input to the digital display control unit 122, input to the display input control circuit 123, and provided to the automatic adjustment control circuit 131. Digital R, G, B
There are two types of display data 121, depending on the high resolution specifications of the input display data that can be supported, when the A / D converter circuit 120 is a serial output and when the A / D converter circuit 120 is a two-parallel output. The inside of the digital display control unit 122 according to the present invention is 2
When the digital R, G, and B display data 121 is a serial input, the display input control circuit 123 performs serial / parallel conversion and outputs the data to the multi-scan control circuit 124 because of parallel control. Conversely, in the case of parallel input, the input digital R, G, B display data 121 is output to the multi-scan control circuit 124 without conversion. The automatic adjustment control circuit 131 includes digital R, G, and B display data 121.
In addition, vertical and horizontal synchronizing signals 106 and 107 are also provided. Based on the input display information, the start and end positions of the display data, the maximum and minimum values of the display data during one frame period, and the display of those values are displayed. The position and the like are detected, and all the detected values are assigned to the LSI internal register and output to the microcomputer 134 through the microcomputer bus 135. Microcomputer 134
Calculates a difference value from a predetermined value based on these values and resets the value to a specified value, thereby realizing automatic adjustment of output display data. On the other hand, the digital R, G, B input to the multi-scan control circuit 124
The display data 121 is composed of digital R, G,
A memory for storing the B display data 121 is provided, and it is possible to digitally perform enlargement processing on a dot-by-dot basis and output it. The digital display data 125 output from the multi-scan control circuit 124 is input to the multi-color control circuit 126, where the display colors are pseudo-increased in frame units (FRC processing) and output to the display output control circuit 130. The multi-colored digital display data 127 input to the display output control circuit 130 is video data from a personal computer, a workstation, or the like displayed on the display panel. The display output control circuit 1 adds the adjustment menu display data 129 generated inside the adjustment menu display control circuit 128 to the digital display data 127.
An overlay process is performed at 30 and finally output as digital R, G, B display data 132 to be displayed on the display panel. The adjustment menu display data 129 is realized by reading out character memory data inside the adjustment menu display control circuit 128 using a code / attribute memory. Note that the microcomputer 134 recognizes the adjustment key input 138 by the user and issues an adjustment menu display instruction to the data bus 135.
To the digital display control unit 122 through. The display output control circuit 130 outputs a synchronizing signal for controlling the timing of the display panel, a dot clock, and a blank signal 133 together with the output of the digital R, G, and B display data 132.

Further, a counter that sets each of the vertical synchronization signal 106 and the horizontal synchronization signal 107 as a clear condition is provided in the digital display control unit 122, and the horizontal synchronization signal 107 is provided in the vertical direction, and the oscillation clock is provided in the horizontal direction. Using the clocks 142 as clocks, both the vertical and horizontal periods are measured. The measured cycle is stored in the microcomputer 13 as part of the register.
4 can be read through the microcomputer data bus 135.

The microcomputer 134 determines the resolution of the read value by a resolution determination algorithm, reads various setting parameters corresponding to the determination result from the parameter storage memory 139 through the memory bus 140, and sets the parameters in each register. As a result, the microcomputer can omit the interrupt processing for the resolution determination and the like, so that the load can be reduced and a low-function microcomputer can be used.

FIG. 23 shows an internal configuration of the cycle measurement control unit 144 for realizing such a function. In the figure, 2
001 is a horizontal cycle measurement counter, 2002 is a vertical cycle measurement counter, and 2003 is a register read control circuit. The horizontal period measurement uses the oscillation clock 142 having a fixed frequency as a counter clock, and the horizontal synchronization signal 107 is used to clear the counter. The period measurement in the vertical direction is based on the horizontal synchronization signal 1
07 is used as a counter clock, and the vertical synchronization signal 108 is used to clear the counter. Each counter outputs the value immediately before being cleared to the register read control circuit unit 2003, and the microcomputer recognizes the frequency in each of the horizontal and vertical directions via the data bus 135 by the register read access by the microcomputer 134. It is possible to do. At this time,
When each frequency is lower than the normal frequency, the microcomputer 134 determines that the periodic signal has not been input, and shifts the entire system to the power saving mode (the shift to the power saving mode is performed by the display control unit setting data 136).

Further, the microcomputer clock 143 used by the microcomputer 134 uses the oscillation clock 142 from the crystal oscillator 141 as the microcomputer clock controller 1 inside the digital display controller 122.
Use the clock divided by 45. Therefore, synchronization between the digital display control unit 122 and the microcomputer 134 is facilitated. In addition, the frequency division value inside the digital display control unit 122 can be changed, so that the clock specifications of the crystal oscillator 141 and the microcomputer 134 can be easily changed. Can have versatility.

In the present invention, the serial communication bus 137 is provided so that it can be directly controlled by an external system, and the function of each unit can be easily verified.

FIG. 2 shows an internal configuration diagram of the display input control unit 123 in the digital display control unit 122.

The control unit controls the display data output format of the A / D converter circuit 120 (dot serial output when the high-resolution upper limit frequency is low, (Parallel output), and performs serial / parallel conversion of digital display data and even / odd conversion of digital display data.
In FIG. 2, reference numeral 201 denotes a serial number of digital display data.
Parallel conversion control unit, 202 is an even / odd conversion control unit, 203 to 208, 211, 216, and 217 are latch circuits in the serial / parallel conversion control unit 201, 209 is a clock frequency dividing circuit, 210, 213, 214 is an inverter circuit, 212 and 215 are selector circuits, 218 is a latch circuit in the even / odd conversion control unit 202, and 219 and 220 are selector circuits. Also, DSH
The IFTP signal and the ISDIEN signal are connected to a power supply or a ground outside the digital
gh ”or“ Low ”level signal.

ID [7: 0] and terminal ID [15:
8] terminal is provided for each of R, G, and B, and has a width of 8 bits. The ID [7: 0] terminal receives half (even number data) of each of the R, G, and B of the digital R, G, and B data 121 described above. The ID [15: 8] terminals are R, G, and B of the digital R, G, and B data 121 described above.
B receives the other half (odd data) of each. These R, G, B 8 bits each (total 24 bits) constitute one dot. Thus, in the present embodiment, one dot corresponds to 2 to the 24th power (16 million colors = full-color display).

In FIG. 2, in the case of the dot serial input operation, data is input from the ID [15: 8] terminals. At the same time, the serial / parallel mode setting terminal I
The SDIEN terminal becomes “L”, and the selectors 212 and 215 select the “b” side. Therefore, of the serial data input from the ID [15: 8] terminal, even data (0,
, 2,...) Are latched by the LDCLKs in the latch circuits 204 to 206, the output data is latched in the latch circuit 216, and output from the OD [7: 0] terminal to the next multi-scan control circuit 224. I do. Here, as the clock of the latch circuit 216, a clock generated by the divide-by-2 circuit 209, the inverter 210, the latch circuit 211, and the selector 212 using LDCLK as an input is used. Odd data (1, 3, 5,
...) Output from the latch circuit 204 to the latch circuits 208 and 217.
And outputs the signal to the multi-scan control circuit 124 at the next stage from the OD [15: 8] terminal. Here, the clock of the latch circuit 217 is the same as that of the latch circuit 216, and the clock of the latch circuit 208 is
Use the inverted clock. Thus, the ID
The serial data input from [15: 8] is parallel-converted and output from OD [7: 0] and OD [15: 8].

In the case of the dot parallel input operation, even-numbered data (0, 2, 4,...) Is supplied from the ID [7: 0] terminal, and odd-numbered data (1, 3, 5,. :
8] Input from terminal. At the same time, the ISDIEN terminal becomes "H", and the selectors 212 and 215 select the "a" side. Thus, the even-numbered and odd-numbered data latch circuits are the same, and output from the OD [7: 0] and OD [15: 8] terminals, respectively.

Further, the digital display control unit 12 according to the present invention
2 processes the inside with two dots in parallel (hereinafter simply referred to as parallel), so the minimum adjustment amount of the horizontal display position is two dots. Therefore, even when the horizontal display position is adjusted to the best state, the left or right end row may be blank display with respect to the display range of the display panel, and the other side may not be displayed in a single row. In order to avoid this problem, the even / odd data is converted by the digital display data even / odd conversion control unit 202. DSHIF to instruct data conversion
When the TP signal is set to “H” level, the selector circuit 21
9 and 220 select the "b" side. As a result, the even-numbered data (ID [7: 0]) output from the serial / parallel conversion control unit 201 of the digital display data is transferred to the selector circuit.
Odd data selected by 220 (OD [15: 8])
And the odd data (ID [15: 8]) is delayed by one clock by the latch circuit 218, and the selector circuit 219
And output as even-numbered data (OD [7: 0]). For the input digital display data, the digital display control unit 122 according to the present invention shifts (delays) the data by one clock (one dot) and processes it. Can be completely matched. FIG. 3 shows a timing chart of horizontal display position adjustment by data shift (delay).

FIG. 4 is a diagram showing the internal configuration of the multi-scan control circuit unit 124 in the digital display control unit 122.

The present control circuit section performs a scaling (enlargement) process on the 2-parallel digital display data output from the display input control circuit 123 in accordance with the display size of the display panel using a line memory for four lines. is there. 4, reference numeral 401 denotes a line memory control unit for scaling; 402, a display data scaling (calculation) unit;
0 is a line memory of line 0 / bank 0 to line 3 / bank 7, 411 is an input digital display data selector circuit, 412 is a write / read address selector for line memories 403 to 409, 413 is a latch circuit, and 414 is frame data. Selector, 415 is a line data selector, 416 is a write address counter for line memories 403 to 409, 417 is a read address counter, 418 is a frame data horizontal operation control unit, 419 is a line data horizontal operation control unit, and 420 is an even number A vertical operation control unit for pixels, 421 indicates a vertical operation control unit for odd pixels, 422 indicates a horizontal operation select signal generation unit, and 423 indicates a vertical operation select signal generation unit. In this embodiment, a VGA (640 × 640 dots) display panel is used for a display panel of XGA size (1024 × 768 dots).
(480 × 600 dots) and SVGA (800 × 600 dots) display mode are scaled (enlarged), and through display is performed for the XGA (1024 × 768 dots) display mode. Each of the R, G, and B display data has an 8-bit / pixel configuration, and performs 2-parallel processing on each, so that 48-bit data is processed by one load clock LDCLK. First, the operation of the scaling line memory control unit 401 is as follows. Each of the line memories 403 to 410 has a 200 × 48 bit configuration, stores input display data for four lines in the VGA and SVGA modes, and stores two lines of display data in the XGA mode. Stores the display data of. For the line memories 403 to 410, a single-port static random access memory (hereinafter referred to as SRAM) or the like is used, and each line is composed of two banks and interleaved. As a result, the operating speed per bank can be half the speed of the load clock. The digital display data from the display input control circuit 123 is selected by the selector circuit 411, and is stored in the line 0 in the line memories 403 to 410.
To line 3 are output to any of the line memories. At the same time, the selector circuits 412 and 413 use the digital display data (OD [7: 0],
OD [15: 8]) is also output to the display data scaling (calculation) unit 402. For the digital display data given to the line memories 403 to 409, the selector circuit 412 selects the write address counter 416 and stores the count value as an address. Where the write address counter
A latch circuit 416 uses an input horizontal address counter that increments every load clock (LDCLK).
At step 3, the write address counter 416 is latched and set as an address for the bank memory to be written in the latter half. To read the display data from the line memories 403 to 409, the value of the read address counter 417 is given as an address to all the memories by the selector circuit 412, and the bank selected by the output enable signal (OE [7: 0]). Read data only from memory. Also, the control of the read cycle differs depending on either the simple enlargement method or the gradation integration method as a scaling (enlargement) processing method described later. In the simple enlargement method, the read for the write data of each line is performed at the end. Is read once and only the last line is read twice. However, in the case of the gradation integration method, the read data for each line is all read twice, and the data of two lines is read at the same time. I do. FIG. 5 and FIG. 6 are line memory write / read timing charts when scaling processing (1.5 times (960 × 720 dots)) display data in the VGA mode by the simple enlargement method and the gradation integration method, respectively. Is shown.
In the figure, "second read" indicates the second read of the same line data.

It should be noted that WE [7: 0] -N, OE in FIG.
[7: 0} -P, FLMOE [3: 0], LINOE
[3: 0], RDN / WRN are signals generated by a memory control circuit unit (not shown) in the multi-scan control circuit 124.

Next, a display data scaling (calculation) section 40
In the second operation, the display data from the display input control circuit 123 or the read data from the line memories 403 to 410 is input to the horizontal operation circuit for frame data 418 or the horizontal operation circuit for line data 419. The first data of each line read is input to the horizontal operation circuit unit 418 for frame data, and the second data of each line read is input to the horizontal operation circuit unit 419 for line data. Using the select signal from the horizontal operation control circuit 422, the frame and the display data that has been subjected to the horizontal operation by the line operation horizontal operation circuits 418 and 419 are the even pixel vertical operation circuit 420 and the odd pixel vertical operation circuit. The signals are input to both of the arithmetic circuits 421, and the arithmetic operation in the vertical direction is performed using the select signal from the vertical arithmetic control circuit 423.
EV [7: 0]), odd-numbered pixels (SDATOD [7:
0]). In the present invention, as a scaling mode, a through mode in which the line memories 403 to 409 are not used, a “1 to 1 mode (1 × mode)” using the line memories 403 to 409, and “2t” for expanding the VGA input mode
o3 mode (1.5 × mode) and “4 to 5 mode (1.25 × mode)” for expanding the SVGA input mode.
It corresponds to the gradation integration method. Table 1 shows a list of scaling modes corresponding to Table 1.

[0047]

[Table 1]

In the present embodiment, a simple enlargement method and a gradation integration method for the "2 to 3 mode (1.5 times mode)" in which the VGA input mode is enlarged in accordance with the operation of the scaling line memory control unit 401. The operation of FIG. FIG.
In (a) to (d), the horizontal operation converts two dots into three dots, that is, 1.5 times. First, in the memory read operation, the number of pixels is increased by reading the second dot twice, and in the case of the simple enlargement method, the pixels are rearranged as shown in FIG. In the case of the gradation integration method, a halftone is calculated from two adjacent pixels as shown in FIG. The formula for calculating the halftone is: Xm '= Xm Xm + 1' = 0.5Xm + 1 + 0.5Xm Xm + 2 '= Xm + 1

The calculation in the vertical direction (vertical direction) enables the simple enlargement method and the gradation integration method as in the horizontal direction (horizontal direction). In the simple enlargement method, as shown in FIG. 7C, by reading the display data of the second line of the line memory twice, the number of lines is increased by 1.5 times from the second line to the third line as in the horizontal operation. The line data is not rearranged as in the direction. In the case of the gradation integration method, as shown in FIG.
In each of the upper and lower lines, a halftone is calculated from two corresponding pixels of an adjacent line, and the value is output to the Yn + 1 'line, which is the same as in the case of the horizontal operation. The formula for calculating the halftone is: X'.Yn '= X'.Yn X'.Yn + 1' = 0.5X'.Yn + 1 + 0.5X'.Y
n X ′ · Yn + 2 ′ = X ′ · Yn + 1

FIG. 8 shows the internal configuration of the multi-color control circuit 126 in the digital display control unit 122.

The control circuit unit 126 generates three potentials between each gradation by using the number of gradations that can be displayed on the display panel (for example, 64 gradations in this embodiment). Simultaneously multiple gradations (for example, 2
53 gradations). This allows
A total of 16.19 million colors can be displayed for R, G, and B.

In FIG. 8, reference numeral 701 denotes a 2/4 spatial modulation pattern generation unit, 702 denotes a 1/3, 2/3 spatial modulation pattern generation unit, and 703.
Is a selector circuit 1, 704 is an addition circuit, 705 is a selector circuit 2, 706 is a latch circuit, 707 is an EOR circuit, and 708 is AND.
Each circuit is shown. In FIG. 8, the 2/4 pattern generation unit 701
Further, the 1/3, 2/3 pattern generation unit 702 generates a gray scale of 1/3, 2/4, 2/3 between two adjacent gray scales (α, β). According to the system clock (CLKIN), the horizontal synchronization signal (HSYNC-N), and the vertical synchronization signal (VSYNC-N), as shown in FIG. The four patterns are repeated in the first to fourth frames. The generated spatial modulation pattern is output to the selector circuit 703, and the pattern selected by the pattern selection signal (RFRCPTN) set by the register setting is further selected from the lower two bits of the display data, and output to the EOR circuit 707. Here, the pattern selection based on the register setting includes, as shown in FIG. 10, a pattern for emphasizing a black level (pattern 1),
This is a pattern (pattern 2) that emphasizes the white level. The output data of the EOR circuit 707 is ANDed with the register setting (RFRCEN) indicating the validity / invalidity of the multi-color display, and becomes the select signal of the selector circuit 2705. The selector circuit 2705 includes the upper 6 bits of the display data 125 from the multi-scan control circuit 124 and the upper 6 bits of data −1 or +
Select one of the displayed data. Therefore, when the register setting (RFRCEN) indicating the valid / invalid of the multi-color display is invalid, the upper 6 bits of the display data 125 from the multi-scan control circuit unit 124 are selected, and the multi-color display is not performed. Conversely, register setting indicating valid / invalid of the multi-color display
When (RFRCEN) is valid, it depends on the output result of the EOR circuit 707. When the pattern selection signal (RFRCPTN) is set to “L”, the addition circuit is used when the spatial modulation pattern is “H”.
The 704 side is selected, and the display data of the upper 6 bits-1 of the display data 125 from the multi-scan control circuit section 124 is output to the latch circuit 706. Conversely, the pattern selection signal (RFRC
When the PTN) is set to “H”, the addition circuit 704 is selected when the spatial modulation pattern is “L”, and the upper 6 bits of the display data 125 from the multi-scan control circuit unit +1
Is output to the latch circuit 706. In this way, by setting the gradation level of the display data to −1 or +1 according to the voltage level of the spatially deviated pattern generated internally between two adjacent gradations, multicolor display can be realized.

The signals RFRCEN and RFR shown in FIG.
The CPTN is generated by a register control unit (not shown) in the digital control unit 122 of FIG.

FIG. 19 shows the adjustment menu display control circuit 12
8 shows a specific display example of the adjustment menu according to FIG. This adjustment menu is a menu for adjusting the screen of the liquid crystal display monitor. As an example of an operation method based on this adjustment menu, for example, when performing horizontal position adjustment, by selecting an item “HORIZONTAL” from the top menu 1900 from an input unit such as a key or a touch panel (not shown), A lower layer menu 1901 indicating the adjustment amount is displayed. When an item “<LEFT” indicating the left direction is designated in the menu 1901 of this hierarchy, the screen moves to the left, and the item “RIG” indicating the right is moved.
When "HT>" is specified, the screen moves rightward.

FIG. 11 shows an internal configuration diagram of the display output control circuit unit 130 in the digital display control unit 122.

The control circuit unit 130, contrary to the display input control circuit unit 123, outputs two parallel digital display output data 1 from the multicoloring control circuit unit 126 depending on the setting state of the external terminal.
27 is parallel / serial converted and corresponds to a high-speed clock operation at the time of serial output. Furthermore, when the digital display control unit 122 according to the present invention is implemented as an LSI, the digital display control unit 122 has a switching function for monitoring the operation of each internal function (test mode output). In FIG. 11, 1001
Is the display output data 132 is the test block 1 with the monitor assigned to the odd upper, 1002 is the test block 2 with the monitor assigned to the odd lower, 1003 is the test block 3 with the monitor assigned to the even upper, and 1004 is the even lower Test blocks 4 and 10 with assigned monitors
05, 1006 are latch circuits with preset function 1, 2, 1007
Is an OR circuit 1, 1008 is a selector circuit 1, 1009 is an OR circuit 2, 1010 is an inverter circuit 1, 1011 is NOR circuits 1, 10
12 is a NOR circuit 2, 1013 is an inverter circuit 2, 1014 is a selector circuit 2, 1015 is a latch circuit 3 with a reset function,
1016 is a selector circuit 3, 1017 and 1018 are NOR circuits 3,
Reference numerals 4 and 1019 denote NOR circuits 5 and 1020, respectively, a latch circuit 4 with a reset function.

In FIG. 11, the digital display data 129 from the adjustment menu display control circuit 128 is a latch circuit 1005 and a latch circuit 1002 in an even / odd 2-dot parallel state.
Import to 1006. When video data is displayed by parallel output, the 2 parallel output mode setting terminal (ISDOEN) is at “H” level, the output of the OR circuit 1007 is fixed at “H”, and the output of the NOR circuit 1017 is fixed at “L”. . As a result, the selector circuit 1014 selects the (b) side. In addition, since the mode is the normal mode for displaying a video signal, the signals TEST1 and TEST2 indicating the test mode become “L” level. As a result, the outputs of the NOR circuits 1011, 1009, 1017, and 1018 are at the "L" level, and the output of the inverter circuit 1010 is at the "H" level. Therefore, the data latched by the latch circuit 1015 is inverted data of the output of the latch circuit 1005, that is, odd data of the two parallel display data 129 output from the adjustment menu display control circuit 128. Also,
The data latched by the latch circuit 1020 is
Since the outputs of 7 and 1018 are at the “L” level, the output of the latch circuit 1006 is reflected. That is, the output becomes the even number data of the two parallel display data 129 output from the adjustment menu display control circuit 128.

Next, display data is processed in two parallel processes up to the adjustment menu display control circuit 128, and this display output control circuit section
When parallel / serial conversion is performed at 130 and finally serial output is performed, the 2 parallel output mode setting terminal (ISDOEN) sets the “L” level. Also in this case, the signals TEST1 and TEST2 indicating the test mode become “L” level,
The output of the OR circuit 1019 is always at the “L” level (the output (OODATA) of the latch circuit 1020 which becomes the display output data on the even side).
Is always "L" level). Conversely, the output (OEDATA) of the latch circuit 1015, which becomes the display output data on the odd side, is
14 output data is reflected. The (a) input of the selector circuit 1014 is the even number data of the two parallel display data 129 output from the adjustment menu display control circuit 128, and the (b) input is that the output of the NOR circuit 1011 is at the “L” level. Thus, the odd-numbered data of the two parallel display data 129 output from the adjustment menu display control circuit 128 is obtained. Switching between even / odd display in the selector circuit 1014 is controlled by the output level of the OR circuit 1007.
The output level of the OR circuit 1007 is set to two parallel output mode setting terminals (ISDOEN) and signals TEST1 and TEST indicating the test mode.
Since all of EST2 are at the “L” level, the normal phase and the negative phase of the reference clock (CLKIN) of the two parallel control are directly reflected.
That is, since the two parallel display data is converted directly to the serial display data by directly using the level of the two parallel clocks (CLKIN), the delay due to the logic circuit is suppressed and the high frequency operation can be supported.

In FIG. 11, ISDOEN, TEST
1, TEST2, are input signals connected to a power supply or GND outside the digital control unit 122 in FIG. RESETN is a reset signal for the entire apparatus, and is a signal supplied from a higher hierarchy of the apparatus of FIG.

FIG. 12 shows an operation timing chart when the above-described two-parallel display data is converted into serial display data. Further, the display output control circuit section 130
Is provided with a switching control for monitoring internal functions by setting a test mode when the digital display control unit 122 according to the present invention is implemented as an LSI. When the LSI internal operation is set to output to the even display output data terminal (OODATA) and the odd display output data terminal (OEDATA), first, the signals TEST1 and TEST2 indicating the test mode are set to “H” level. As a result, the latch circuits 1005 and 1006 enter the preset state, and their output data is fixed at the “L” level. Therefore, the data input to the latch circuit 1015 is either the test block 1001 or the test block 1002.
The internal monitor signal assigned to the latch circuit 1020
Is an internal monitor signal assigned to the test block 1003 or the test block 1004. Which of the test blocks 1001 and 1002 and the test block 1003 and the test block 1004 is monitored is switched by the selector circuit 1008 and the selector circuit 1016 depending on the setting level of the TEST2 terminal.

As described above, in the present invention, when the internal operation is monitored by setting the test mode, the output data of the latch circuit 1005 and the output data of the latch circuit 1006, which are the display data when performing the display output in the normal operation, are used as the test block. By using the signal as a selection signal, it is possible to eliminate a selector circuit which causes an increase in delay, and it is possible to cope with a high frequency of serial display output by the 2-parallel / serial conversion.

FIG. 13 shows an internal configuration diagram of the adjustment menu display control circuit unit 128 in the digital display control unit 122.

The control circuit section has a character memory for generating an adjustment menu display character, and a code / attribute memory for specifying the address and color information of the character memory. The adjustment menu display data is output, and in the display output control circuit unit 130, the menu display is realized on the display panel by overlaying the output display data 127 from the multicoloring control circuit 126.

In FIG. 13, reference numeral 1201 denotes an adjustment menu display period pulse generation unit; 1202, a state machine generation unit indicating a display / non-display state of the adjustment menu; 1203, a memory control signal generation unit by microcomputer access; and 1204, an adjustment menu display. Control signal generator 1205, a selector circuit 1205, a memory address generator 1206 for accessing the microcomputer, 1207 a memory address generator for displaying an adjustment menu, 1208 a selector circuit 2, 1209 a code / attribute Memory, 1210 is an addition circuit 1, 1211 is a character memory, 1212 is a parallel / serial conversion circuit for character data, 1213 is a color palette register section, 1214
Indicates an adder circuit 2 and 1215 indicates a selector circuit 3, respectively.

FIG. 14 shows a specific configuration example of the menu display period pulse generator 1201. The menu display period pulse generation unit 1201 displays
It has a function of setting a position at which a menu screen is displayed, and has a horizontal display period pulse generator 1201a and a vertical display period pulse generator 1201b for separately setting the vertical direction and the horizontal direction. Specifically, a counter 1201 for counting a dot clock to measure a horizontal position
1 are compared with the set values of the horizontal start position setting register 12013 and the horizontal end position setting register 12014 by comparators 12017 and 12018, respectively, and the outputs of both comparators are input to the JK flip-flop 12021. A pulse having a width from the signal display start position to the end position indicating the horizontal menu display period is output. Similarly, the output of the counter 12012 for counting the horizontal synchronization signal to measure the vertical position is compared with the output of the comparator 1202.
19, 12020, a vertical start position setting register 12015 and a vertical end position setting register 1201
6 and inputs the outputs of both comparators to the JK flip-flop 12022 to output a pulse having a width between the display start position and the end position as a signal indicating the vertical menu display period. .

FIG. 15 shows a state machine generator 1202.
FIG. State machine generator 1202
Is a means for distinguishing between a menu display period and a non-display period, and sequentially changes states according to a reference clock. Normally, the state stays in the state indicating the menu non-display period (S0 state in the figure) and recognizes the menu display period pulse (the signal OLHEN- indicating the horizontal and vertical menu display periods output from the circuit of FIG. 4).
P.OLVEN-P) and a state (S1, S2,..., S8 state) indicating a menu display period. Therefore, the entire circuit performs control based on this state.

Returning to FIG. 13, when the system is started, the microcomputer sets a character memory address and character color information in the code / attribute memory 1209, and sets character data (font data) in the character memory 1211. These settings are made by the microcomputer 1034 shown in FIG. 1 from the data (MD [7: 0]), write (WRN) / read (RD
N) A command and an address (MA [15: 0]) are input, a microcomputer access / memory control signal generator 1203 generates a memory write / read pulse, and a microcomputer access / memory address generator 1206 generates a memory address. I do. The generated write / read pulse and address are input to the selector circuit 1205 and the selector circuit 1208, respectively. The input on the opposite side of each selector circuit is a memory read pulse generated by the menu display memory control signal generation unit 1204 and a menu display memory address generated by the menu display memory address generation unit 1207, respectively. Switching of these selector circuits is performed by the menu display period pulse generator 12.
This is performed using a state signal output from the state machine generation unit 1202 that transitions based on 01. Therefore, when the system is started, the state signal indicating the adjustment menu non-display period is output from the state machine generation unit 1202, and both the selector circuit 1205 and the selector circuit 1208 select the (a) side, and the microcomputer 1034 shown in FIG. The memory access from is enabled. The state signal indicating the menu non-display period selects the (a) side of the selector circuit 1215, and selects the display output data 1027 from the multicolor control circuit 1026.

Next, when the menu display period pulse is output from the menu display period pulse generation unit 1201, the state machine generation unit 1202 outputs a state signal indicating that the adjustment menu display is valid. With this state signal, the selector circuits 1205, 1208, and 1215 all select the menu display memory control signal generation unit 1204, the menu display memory address generation unit 1207, and the addition circuit 1214 that outputs adjustment menu display data to select the (b) side. Output data is selected. Accordingly, a memory read pulse and an address for displaying an adjustment menu are output to the code / attribute memory 1209 irrespective of the access instruction of the microcomputer 134.
The code / attribute memory 1209 outputs, from the area corresponding to this address, an address for indicating the position where the head data of the character to be displayed is stored and the color information data of the character to be displayed. The read address data is added to the raster address output from the menu display memory address generation unit 1207 by the addition circuit 1210, and is provided to the character memory 1211 as an address. The color information data is output to the color pallet register unit 1207, and performs valid / invalid control of the pallet data. The character memory unit 1211 includes a memory read pulse from the menu display memory control signal generation unit 1204 and an addition circuit 1210.
The corresponding character data is read out in parallel by the character address from. The parallel-state character data is converted into serial data, which is a display output timing, by a parallel / serial conversion circuit 1212, and color information from the color pallet unit is added by an addition circuit 1214 and output to a selector circuit 1215. In the selector circuit 1215, since the state signal from the state machine generating unit 1202 indicates the adjustment menu display, the selector circuit 1215 selects the (b) side and outputs adjustment menu data serialized and added with color information. Therefore, since the adjustment menu is displayed in the order of the addresses of the code / attribute memory 1209, the upper limit of the adjustment menu display range is determined by the memory capacity. Therefore, in the present invention, when the menu display range larger than the capacity of the code / attribute memory 1209 is set by the menu display period pulse generation unit 1201, the address from the menu display memory address generation unit 1207 overflows, and the adjustment menu 2 To avoid double display,
When the maximum address of the code / attribute memory 1209 is accessed, the display range thereafter repeats access to this maximum address, and an address for blank data is set in this maximum address.

FIG. 16 shows a configuration diagram of the control circuit. In FIG. 16, reference numerals 1202 and 1207 denote a state machine generator 1 and a menu display memory address generator 1 in the adjustment menu display control circuit 128. 1301 is a code / attribute memory address counter, 1302 is an address decoder, 1303 is a counter stop circuit, 1304 is a code / attribute memory / maximum address generator, and 1305 is a selector circuit. In FIG. 16, the state machine
When the state signal output from 1202 indicates the adjustment menu display period, the code / attribute memory address counter 1301 starts counting and the selector circuit 1305
(A) Output the counter value as an address to the input.
The address decoder 1302 receives this counter output,
This is compared with the maximum address value of the maximum address generation unit 1304. A signal becomes valid when the counter value of the memory address counter 1301 reaches the maximum address value of the code / attribute memory. The decoded output controls the select signal of the selector circuit 1305 and the activation of the counter stop circuit 1303. When the counter output is smaller than the maximum address value, the selector circuit 1305 (a)
When the counter is selected, the counter stop circuit 1303 is disabled, and the code / attribute memory address counter 1301 continues counting. When the count operation continues and the counter value reaches the maximum address value of the code / attribute memory 1209, the address
When the output of the decoder 1302 is inverted and the selector circuit 1305 selects the side (b), the counter stop circuit 13
03 is activated, and the code / attribute memory address counter 1301 is held. Therefore, the output of the address decoder 1302 is also in the hold state. In this state, the output of the selector circuit 1305 becomes the maximum address from the code / attribute memory maximum address generation unit 1304, and the character display indicated by the character address stored in the maximum address of the code / attribute memory 1209 is continued. If blank data is set in this area, double display of the adjustment menu does not occur. Further, this function can be used not as an adjustment menu but as mask data of video display data.

As shown in FIG. 17, when the number of lines of a certain type of resolution display data cannot satisfy the number of lines required by the display panel, double display of display data occurs. Therefore, by using the present invention, the adjustment menu display range is set to the double display portion of the display data, and the menu display data is entirely blank data. Becomes maskable. In FIG. 17, for convenience, the description is made using a picture of a person, but the actual displayed content is different from this.

FIG. 18 is a diagram showing the internal configuration of the automatic adjustment control circuit 131 in the digital display control unit 122.

The control circuit detects a blank level, a start / end position of the input display data, a maximum / minimum value of the input display data, and a change point of the input display data from the input display data of various resolutions, and detects the change level in a register format. By outputting these values to the microcomputer, offset, gain, display position,
The microcomputer realizes automatic adjustment by calculating and resetting optimal setting values such as a clock phase and a clock dividing value. In FIG. 18, reference numeral 1501 denotes a blank level hold control unit, 1502 denotes a display data start / end position detection control unit, 1503 denotes a display data maximum / minimum value detection control unit, 1504 denotes a display data change point detection control unit, and 1505-1508. Reference numerals 1 to 4 denote synchronization circuits for synchronizing detection data from the control units with the operation of the microcomputer, and reference numeral 1509 denotes a register read control circuit. In FIG. 18, a blank level hold control unit 1501 detects the input start / end position of the display data and detects the black level. The blank level hold control unit 1501 uses a reference value for comparing the data level with the A / D converter circuit 120. From the input display data 121, the dot clock 110, the input vertical synchronization signal 106, and the horizontal synchronization signal 107. The generated reference data is synchronized with the operation timing of the microcomputer 134 by the synchronization circuit 1505 so that the microcomputer 134 reads the register. Display data start / end position detection control unit 15
02 determines the display start position and the end position of the input display data 121 from the value of the input display data 121, and holds the values of the horizontal / vertical positions. Like the blank level hold control unit 1501, the held horizontal / vertical position data is used by the synchronization circuit 1 to read the register by the microcomputer 134.
At 506, the operation timing is synchronized with the operation timing of the microcomputer 134. The display data maximum / minimum detection control unit 1503 compares the values of adjacent dot data during one frame period, and detects the maximum value and the minimum value. The microcomputer 134 adjusts the offset / gain to an optimum value with reference to the maximum value / minimum value. The detected maximum value and minimum value are synchronized with the operation timing of the microcomputer 134 by the synchronization circuit 1507 in order to perform the register read by the microcomputer 134, similarly to the blank level / hold control unit 1501. Display data change point detection controller 15
04 is the input display data 121 during one frame period,
The position where the change of the display data value between dots is large and the display data before and after the position are detected, and the correlation with the clock phase adjustment value is obtained to adjust the clock phase to the optimum value. The detected position and the display data are synchronized with the operation timing of the microcomputer 134 by the synchronization circuit 1508 so that the microcomputer 134 reads the register similarly to the blank level / hold control unit 1501. As described above, each of the synchronized detection data is decoded by the register read circuit control unit 1509 so that the microcomputer 134 can read the data as a register, and sequentially read in a register read cycle.
The microcomputer 134 analyzes the read data and automatically sets each adjustment value to an optimum value.

As described above, in the liquid crystal display control device according to the present invention, the digital display control unit 122 (display input control circuit unit 12
3, multi-scan control circuit section 124, multi-color control circuit section 12
6. The display output control circuit unit 130, the adjustment menu display control circuit unit 128, and the automatic adjustment control circuit unit 131) are implemented as LSIs, thereby enabling high density, low power consumption, and low cost. .

When executing the automatic adjustment, it is possible to entrust all adjustments to the automatic adjustment control means, and during this time, the adjustment menu can be kept in a non-display state. Therefore, the operation of the automatic adjustment control means and the operation of the adjustment menu display control means do not have to be performed at the same time, so that power can be saved.

[0075]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

That is, according to the liquid crystal display control device of the present invention, a memory required for scaling input display data of various resolutions according to the display size of the display panel, and an adjustment menu by the on-screen display An effect is obtained that a memory required for display can be built in the LSI.

Further, the digital display control unit in the form of an LSI performs parallel / serial conversion of input / output display data and
It is possible to obtain an effect that high-speed operation, pseudo multi-color display by FRC, and display data mask control using an adjustment menu can be realized.

Further, by detecting various states of the input display data and outputting the detected data to the microcomputer, it is possible to achieve an effect that automation of various adjustments can be realized.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram showing an example of a display system using the technology of the present invention.

FIG. 2 is an internal configuration diagram of a display input control unit in a digital display control unit in the display system according to the present invention.

FIG. 3 is a timing chart of horizontal display position adjustment by data shift (delay) relating to input display data of a display input control unit according to the present invention.

FIG. 4 is an internal configuration diagram of a multi-scan control circuit unit in a digital display control unit in the display system according to the present invention.

FIG. 5 is a line memory write / read timing chart in a simple enlargement method in a multi-scan control circuit unit according to the present invention.

FIG. 6 is a line memory write / read timing chart in the gray scale integration method in the multi-scan control circuit unit according to the present invention.

FIG. 7 is a conceptual diagram of a simple enlargement method and a gradation integration method of a multi-scan control circuit unit according to the present invention.

FIG. 8 is an internal configuration diagram of a multi-color control circuit in a digital display control unit in the display system according to the present invention.

FIG. 9 is a conceptual diagram of generating a spatial modulation pattern in a multicolor control circuit according to the present invention.

FIG. 10 is a graph showing a relationship between input display data and display luminance of the multi-color control circuit according to the present invention.

FIG. 11 is an internal configuration diagram of a display output control circuit unit in a digital display control unit in the display system according to the present invention.

FIG. 12 is a display data parallel / serial conversion timing chart of the display output control circuit unit according to the present invention.

FIG. 13 is an internal configuration diagram of an adjustment menu display control circuit unit in the digital display control unit in the display system according to the present invention.

FIG. 14 is an internal configuration diagram of a menu display period pulse generator shown in FIG. 13;

15 is a state transition diagram of the state machine generator shown in FIG.

FIG. 16 is a schematic diagram of a menu display memory address generation of the adjustment menu display control circuit unit according to the present invention.

FIG. 17 is a conceptual diagram of a video display data mask function by the adjustment menu display control circuit unit according to the present invention.

FIG. 18 is an internal configuration diagram of an automatic adjustment control circuit unit in a digital display control unit in the display system according to the present invention.

FIG. 19 is an explanatory diagram showing a specific display example of an adjustment menu by the adjustment menu display control unit according to the present invention.

FIG. 20 is a configuration diagram illustrating an example of a conventional liquid crystal display system.

FIG. 21 is a schematic configuration diagram of a liquid crystal display control circuit of a conventional liquid crystal display system.

FIG. 22 is a timing chart showing an operation of a conventional liquid crystal display system.

FIG. 23 is an internal configuration diagram of a cycle measurement control unit in the digital control unit according to the present invention.

[Explanation of symbols]

101: vertical synchronization signal, 102: horizontal synchronization signal, 103: analog R, G, B synchronization signal, 104: analog display control unit, 105
... Input synchronization signal polarity reversal and synchronization separation circuit, 106: Vertical synchronization signal after polarity control, 107: Horizontal synchronization signal after polarity control, 108: Phase adjustment circuit, 109: Phase adjustment clock, 110
... PLL circuit, 111 dot clock, 112 offset adjustment circuit, 113 offset adjustment data, 114 gain adjustment circuit, 115 gain adjustment data, 116 pedestal adjustment circuit, 117 pedestal-adjusted R, G, B Analog display data, 118: video amplifier circuit, 119: amplified R, G, B analog display data, 120: A / D converter circuit, 121: digitized R, G, B digital display data, 122: digital Display control unit, 123: display input control circuit, 124: multi-scan control circuit, 125: scaled R, G, B digital display data, 126 ...
Multi-color display circuit, 127: R, G, B digital display data subjected to multi-color processing, 128: Adjustment menu display control circuit, 1
29: Adjustment menu display data, 130: Display output control circuit, 131: Automatic adjustment control circuit, 132: R, G, B output display data, 133: Output synchronization signal, dot clock, blank signal, 134: microcomputer, 135 … Data bus, 136… Display control section setting data, 137… Serial communication control bus, 138…
Adjustment key input data, 139… Parameter storage memory, 140
... memory bus, 141 ... crystal oscillator, 142 ... oscillation clock,
201: serial / parallel conversion control unit, 202: even / odd conversion control unit, 203 to 208, 211, 216, 217: latch circuit, 209
... 2 frequency divider circuits, 210,213,214 ... Inverter circuits, 212,215
... Selector circuit, 218 ... Latch circuit, 219,220 ... Selector circuit, 401 ... Scaling line memory control unit, 402 ...
Display data scaling unit, 403 to 410 ... line memory,
411 input digital display data selector circuit, 412 write / read address selector for line memory, 413 latch circuit, 414 frame data selector, 415 line data selector, 416 write address counter, 4
17 ... Read address counter, 418 ... Frame data horizontal calculation control unit, 419 ... Line data horizontal calculation control unit, 420 ... Vertical calculation control unit for even pixels, 421 ... Vertical calculation control unit for odd pixels, 422 ... Horizontal calculation select signal Generation unit, 423: vertical operation select signal generation unit, 701: 2/4 spatial modulation pattern generation unit, 70
2 1/3, 2/3 spatial modulation pattern generation unit, 703 selector circuit 1, 704 addition circuit, 705 selector circuit 2, 706 latch circuit, 707 EOR circuit, 708 AND circuit, 1001
Test block 1, 1002 ... Test block 2, 1003 ... Test block 3, 1004 ... Test block 4, 1005, 1006
... Latch circuits 1, 2, 1007 ... OR circuits 1, 1008 ... Selector circuits 1, 1009 ... OR circuits 2, 1010 ... Inverter circuits 1, 1011 ... NOR circuits 1, 1012 ... NOR circuits 2, 1013 ...
Inverter circuit 2, 1014 ... Selector circuit 2, 1015 ... Latch circuit 3, 1016 ... Selector circuit 3, 1017, 1018 ... NOR
Circuits 3, 4, 1019 NOR circuit 5, 1020 Latch circuit 4, 1201 Adjustment menu display period pulse generator 1202
State machine generation unit, 1203 ... Memory control signal generation unit by microcomputer access, 1204 ... Memory control signal generation unit for adjustment menu display, 1205 ... Selector circuit 1, 1206
... Memory address generation unit by microcomputer access, 1207
... Memory address generator for displaying adjustment menu, 12
08 ... Selector circuit 2, 1209 ... Code / attribute
Memory, 1210 addition circuit 1, 1211 character memory, 1212 parallel / serial conversion circuit, 1213 color palette register, 1214 addition circuit 2, 1215 selector circuit 3, 1301 code / attribute memory address counter , 1302 ... Address decoder, 1303 ... Counter stop circuit, 1304 ... Code / attribute memory / maximum address generation unit, 1305 ... Selector circuit, 1501 ... Blank level hold control unit, 1502 ... Display data start / end position detection control unit 1503: Display data maximum / minimum value detection control unit, 1504 ... Display data change point detection control unit, 1505 to 15
08 ... Synchronization circuits 1-4, 1509 ... Register read control circuit, 1601 ... Computer body, 1602 ... Analog R, G,
B terminal, 1603 ... Flat panel display, 1604 ...
Control circuit, 1701 A / D converter, 1702 Latch, 1703 Flat panel display controller, 1704 Oscillator, 1705 Frequency divider

Continued on the front page (72) Inventor Yukio Hiruta 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Image Information System Co., Ltd. In the image information system (72) Inventor Hiroshi Kurihara 3300 Hayano, Mobara City, Chiba Pref.Electronic Device Division, Hitachi, Ltd. Inside

Claims (13)

[Claims] 1. A liquid crystal display control device used for a liquid crystal display device for displaying a video signal from a personal computer or the like, comprising a digital control unit for processing display data in which an input video signal is a digital value. A liquid crystal display control device, wherein the digital control unit includes interface control means capable of serial / parallel conversion of an internal input / output display data bus in dot units. 2. The digital control section internally performs processing in 2-dot parallel, and on the input side, the interface control means converts dot serial display data into 2-dot parallel display data or 2-dot parallel display data. Means for switching whether or not to input the display data of 2 dots in parallel. On the output side, the display data of 2 dots in parallel is output as it is in accordance with the specification of the liquid crystal panel.
2. The liquid crystal display control device according to claim 1, further comprising means for switching between dot parallel output and dot serial output. 3. The digital control section according to claim 2, further comprising: an even / odd conversion control means for exchanging display data of even-numbered dots and display data of odd-numbered dots and delaying display data of odd-numbered dots by one dot. The liquid crystal display control device according to claim 2. 4. The interface control means,
In addition to the function of handling display data input to the digital control unit as the original display output data, by having a function as a data selection signal, it is possible to perform high-resolution display data transfer processing at the time of serial interface. 2. The liquid crystal display control device according to claim 1, wherein: 5. A liquid crystal display control device used in a liquid crystal display device for displaying a video signal from a personal computer or the like, wherein an adjustment menu for performing various adjustments to enable the video signal to be displayed in a good state. A liquid crystal display comprising: an adjustment menu display control means for displaying on a display screen, and an automatic adjustment control means for detecting a state of a video signal input for automatically adjusting the adjustment. Control device. 6. The adjustment menu display control means displays an adjustment menu such as an offset of display data, an amplitude level, and a phase difference with a horizontal synchronizing signal on a liquid crystal panel. 6. The liquid crystal display control device according to claim 5, wherein various adjustments are automatically corrected by detecting a current state of the display data. 7. An operation sequence in which the adjustment menu display control means and the automatic adjustment control means activated by an operation on the adjustment menu are not operated at the same time. 7. The liquid crystal display control device according to item 6. 8. The liquid crystal display control device according to claim 1, further comprising control means for enlarging or reducing an input video signal according to the screen size of the liquid crystal panel. 9. A system according to claim 1, further comprising a frame rate control control means for enabling multi-gradation display even when a driver in the liquid crystal panel supports only a small number of gradations. 9. The liquid crystal display control device according to any one of 1 to 8. 10. A control means for enlarging or reducing the input video signal in accordance with the screen size of a liquid crystal panel, wherein a buffer memory required for performing frequency conversion of an input / output video signal is incorporated in an LSI. The liquid crystal display control device according to claim 8, wherein: 11. The adjustment menu display control means includes a memory necessary for storing various font data for the adjustment menu, a font data read address, and color information in an LSI. Item 7. The liquid crystal display control device according to item 5 or 6. 12. A microcomputer for controlling at least the digital control unit, wherein the digital control unit has a counter for counting the period of input horizontal and vertical synchronization signals,
When the period of each synchronization signal becomes longer than the specified period,
The digital control unit outputs a signal indicating that a synchronization signal has not been input to the microcomputer, and the microcomputer issues an instruction to shift to a power saving mode for the entire device by this signal from the digital control unit. 2. The liquid crystal display control device according to claim 1, wherein: 13. A system clock used by the microcomputer is generated inside the digital control unit, thereby enabling both to be synchronized and allowing the frequency of the system clock used by the microcomputer to be arbitrarily set. 13. The liquid crystal display control device according to claim 12, wherein an interface with any microcomputer is made possible, and the selection of the microcomputer has versatility.