JPH039861A - Low noise circuit in impact dot matrix printer - Google Patents

Abstract

PURPOSE:To reduce the noise of an impact dot matrix printer during printing by controlling a discrepancy in a printing head configuration when the number of printing wires to be simultaneously driven for printing is reduced from 12 in a prior art to an arbitrary integer less than 12. CONSTITUTION:A CGPLS generator 104 is a circuit consisting of a shift register of a flip flop assembly, which inputs the data of pulse signals from an impact dot matrix printer drive circuit 101 and inputs a clock PLSCLKd. Twelve flip flops are connected to every printing wire. Twelve data outputs from each flip flop become CGPLSA to CGPLSL. A CGPLS selector 105 selects an arbitrary shifted data CGPLS out of data CGPLSA to CGPLSL per printing wire shifted by the CGPLS generator 104 in accordance with an input of data (g) outputted from a switch 106. The printing data CGPLS shifted in this manner allows an arbitrary timing selection, while 12 wires of odd-number alignment and 12 wires of even number alignment are conventionally driven for printing at the same timing.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to the output and timing of printing wires (printing timing) in impact dot matrix printers.
The present invention relates to arbitrarily shifting , and particularly to reducing noise during printing.

BACKGROUND OF THE INVENTION Conventionally, it has been known that this type of impact dot matrix printer reduces noise during printing by using a housing for the purpose of soundproofing.

Problems to be Solved by the Invention However, the above-mentioned conventional techniques are mechanical treatments and have currently reached a certain limit. Another disadvantage is that it costs a considerable amount of money to create an effective low-noise housing (noise-preventing housing) using this method.

Furthermore, no noise reduction circuit has ever been available which generates print dot timing without changing the basic output impact pulse even when the print head arrangement is different by shifting and selecting the print timing as in the present invention. It wasn't known.

The present invention has been made in view of the above-mentioned conventional situation,
Therefore, an object of the present invention is to provide a novel means that eliminates the above-mentioned drawbacks inherent in the conventional technology and makes it possible to reduce noise during printing.

Means for Solving the Problems In order to achieve the above object, the noise reduction circuit in the impact dot matrix printer according to the present invention inputs a basic output impact pulse corresponding to the vertical dot array of print data of the impact dot matrix printer. A circuit that shifts the timing of Toshiko's pulse by any time,
The printer is equipped with a selector that can arbitrarily select this printing timing, and changes the dot arrangement of the print head according to the timing at which the impact pulse is shifted, so that even if the arrangement of the print heads is different, the basic impact pulse described above can be The feature is that printing dot timing can be generated without changing it.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a circuit block diagram showing an embodiment of the present invention.

Before explaining the present invention in detail, the printing timing of the printing wire of the impact dot matrix printer will be explained.

FIG. 4 is a timing diagram of the impact dot matrix printer during printing wire drive (printing).
CGDAT is a basic output impact pulse signal that sends to the print head that the print wire outputs, ie, prints, when set to "old gh", and that the print wire does not output, ie, prints when set to "Low". The printing wires according to this printing method are arranged in odd number columns (501 in Fig. 5) as shown in Fig. 5.
, are arranged in a staggered manner in two vertical columns of even-numbered columns (502 in Figure 5), and the printing timing is determined by C on the odd-numbered column side as shown in Figure 4.
GDAT and CGDAT on the even-numbered column side maintain a delay of half a printing stroke cycle (T/2 shown in FIG. 4), and each of the 12 lines prints simultaneously.

Next, one embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing an embodiment of a drive circuit for an impact dot matrix printer according to the present invention.

Referring to FIG. 1, reference numeral 101 indicates an impact dot matrix printer drive circuit, and the circuit of the present invention receives a clock signal a and a reset signal from a CLK terminal and a RESET terminal of the impact dot matrix printer drive circuit 101, respectively. It also inputs pulse signals CGDATI to CGDAT24. 1
02 is a clock generator (CLOCK DIVIDER).
) Generates the basic clock for shifting the pulse signal CGDAT. The number of clocks generated here is n of CLKI to CLKn (n is any integer greater than or equal to 1).
Individual. The conditions for this clock cycle are set below.

The pulse signal CGDAT is shifted by a CGPLS generator (CGPLS GENERATOR) 104 (CG
(PLS is CGDAT after shifting), and the inside of this CGPLS generator 104 is a shift register in which flip-flops are assembled. At this time, the pulse width ()lig of the pulse signal CGDAT shown in FIG.
h″x″, Low″y′), it is necessary to make the period of the basic clock of this shift register a common divisor of °X° and °y°.

This is because if the period of the basic clock is not a common divisor of °X° and °y0, the pulse width of the pulse signal CGDAT will not be latched accurately.

Reference numeral 103 denotes a switch, which selects an arbitrary clock PLSCL ((
The basic clock (base clock) that becomes the input to the CGPLS generator 104 is selected.

A specific example of the circuit configuration of the clock generator 102 and the switch 103 is shown in FIG.

The CGPLS generator 104 receives the pulse signal CGDATI of the impact dot matrix printer drive circuit 101.
This is a circuit composed of a shift register made up of a set of flip-flops with ~CGDAT24 as a data input and (clock) d as a clock input in PLSCL.

Connect 12 flip-flops per printing wire per bin, and the 12 data outputs from each flip-flop are:
As shown in FIG. 6, CGPLSA to CGPLSc.

105 is a CGPLS selector which selects the data CGP of each print wire shifted by the CGPLS generator 104;
Select arbitrary shifted data CGPLS from LSA=CGPLSt by inputting data g output from switch 106.

CGPLS generator 104, CGPLS selector 105
A specific example of the circuit configuration of the switch 106 is shown in FIG.

By using the printing cavity data CGPLS shifted in this way, it becomes possible to select an arbitrary timing from the conventional timing in which 122 wires in odd-numbered columns and 122 even-numbered column wires were printed at the same time.

Here, some printing timings from the printing timing matrix shown in FIG. 7 will be explained as examples.

FIG. 8 is a diagram showing the first timing according to the present invention in which six printing wires are printed at the same time, and the wire arrangement of the print head is a staggered arrangement in four vertical columns shown in FIG. is an example where the odd and even columns are parallel).

FIG. 9 is a diagram showing the second timing according to the present invention in which four printing wires print simultaneously, and the wire arrangement of the print head is a staggered arrangement in six vertical columns shown in FIG.
Figure 4 is an example where odd and even numbered columns are parallel).

Fig. 10 is a diagram showing the third timing according to the present invention in which three printing wires print simultaneously, and the wire arrangement of the print head is a staggered arrangement of eight vertical columns shown in Fig. 15. This is an example in which the odd and even numbered columns are parallel, and this printing wire arrangement is called an "S-shaped arrangement").

FIG. 11 is a diagram showing the fourth timing according to the present invention in which two printing wires print simultaneously, and the wire arrangement of the print head is a staggered arrangement in 12 vertical columns as shown in FIG.
FIG. 16 shows an example in which the odd and even columns are symmetrical, and this printing wire arrangement is called a "diamond arrangement").

FIG. 12 is a diagram showing the fifth timing according to the present invention in which each of the 24 printing wires prints independently, and the wire arrangement of the print head is a staggered arrangement of 24 vertical columns shown in FIG. (The figure shows an example where odd and even numbered columns are parallel).

As explained above, the low-noise circuit in the impact dot matrix printer of the present invention uses a difference in the print head arrangement that reduces the number of printing wires that print simultaneously from the conventional 12 in order to reduce noise during printing. Print dot timing can be generated without changing the basic output impact pulse.

As described in detail, according to the present invention, differences in print head arrangement are controlled when the number of print wires that print simultaneously is reduced from the conventional 12 to an arbitrary integer less than 12. As a result, the effect of reducing noise during printing by the impact dot matrix printer can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention, and FIG. 3 shows the CGPLS generator 104 of FIG.
A circuit diagram showing a specific configuration example of the PLS generator 105 and the switch 106, FIG. 2 is the clock generator 102 in FIG.
, a circuit diagram showing a specific configuration example of the switch 103, the fourth
The figure is a print data timing diagram when the print wire is driven by an impact dot matrix printer, Figure 5 is a print head arrangement diagram (viewed from the front of the head) of an impact dot matrix printer, and Figure 6 is a diagram of the print data shifted by the circuit of the present invention. FIG. 7 is a print timing matrix diagram; FIG. 8 is a diagram showing a first print timing example according to the present invention; FIG. 9 is a diagram showing a second print timing example according to the present invention; FIG. 1θ is a diagram showing a third example of printing timing according to the present invention, FIG. 11 is a diagram showing a fourth example of printing timing according to the invention, and FIG. 12 is a diagram showing a fifth example of printing timing according to the invention. , FIG. 13 is a diagram showing a first printing wire arrangement example according to the present invention, FIG. 14 is a diagram showing a second printing wire arrangement example according to the invention, and FIG. 15 is a diagram showing a third printing wire arrangement example according to the invention. FIG. 16 is a diagram showing an example of a wire arrangement, FIG. 16 is a diagram showing a fourth example of a printing wire arrangement according to the present invention, and FIG. 17 is a diagram showing a fifth example of a printing wire arrangement according to the invention. 101... Impact dot matrix printer drive circuit, 102... Clock generator (CLOCKD)
IVIDER), 103 ・X switch, 104 ・C
GPLS GENERATOR
, 105...CGPLS selector (CGPLS 5E
LECTOR) (shift register), 106...
- Switch, a... Internal clock possessed by the drive circuit 101, b... Reset signal possessed by the drive circuit 101, C... Clock selection data, d... PLSCL
, e...Print data (C) held by the drive circuit 101
GDATI~CGDAT24), g...Shift data selection data, h...Selected shift data, x...Print data CGDAT@lli
gh" pulse width, y...Print data CGDAT"L
ow' pulse width, T...cycle of print data CGDAT

Claims (1)

[Claims] The impact dot matrix printer has a circuit that inputs the basic output impact pulse corresponding to the vertical dot array of the print data and shifts this timing by an arbitrary time, and a selector that can arbitrarily select this printing timing, and the print head arrangement. 1. A noise reduction circuit for an impact dot matrix printer, characterized in that the printing dot timing is generated without changing the basic output impact pulse even when the basic output impact pulses are different.