JPH0387061A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form an element having rectifying property by forming a semiconductor device composed of a semiconductor layer which is laminated on a first conductivity type semiconductor layer and contains, in lattice, impurity of second conductivity type different from the first conductivity type, and an upper part layer. CONSTITUTION:The title device is constituted of the following; a P-type semiconductor substrate 101 composed of Si and the like, a field insulating film 102, an N<+> type diffusion layer 103, an interlayer insulating film 104 composed of an Si oxide film and the like, an amorphous Si film 105 containing P-type impurity, and a metal wiring film 106 composed of a single layer or a laminated layer of high melting point metal silicide such as Al, Mo, Ti and W. The amorphous Si film 105 containing P-type impurity and the metal wiring film 106 of an upper electrode are laminated on the N<+> type diffusion layer 103 as a lower electrode. By such a structure, a program element which has been a high resistive element before programming is turned into a rectifying element as the result of programming.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device whose resistance value changes irreversibly from a high resistance to a low resistance due to an applied electric field, and particularly to an electrically programmable read-only memory. The present invention relates to a semiconductor device having an element.

[Prior Art] Conventionally, a so-called uncuff use element, in which an amorphous silicon layer is inserted between electrodes, has been used as a semiconductor device whose resistance value irreversibly changes from high resistance to low resistance due to an applied electric field. .

In particular, when an untied fuse element is used in an electrically programmable read-only memory element, a method of adding a diode to each memory element has been used in order to easily configure a read-only memory element circuit. . The method for forming the diode was to form a Schottky junction layer using platinum on an N-type semiconductor layer with a low impurity concentration.

As a first conventional example, a case where a diffusion layer provided in a silicon substrate is used as one electrode of a memory element will be described with reference to FIG. FIG. 2 shows a main cross-sectional view of a conventional semiconductor device. In the figure, 201 is a P-type semiconductor substrate made of silicon or the like, 202 is a selective oxide film that becomes a field insulating film, 203 is an N-type diffusion layer, 20
4 is an interlayer insulating film made of a Zinocon oxide film, etc., 205 is N
206 is a platinum silicide layer, 207 is an amorphous silicon film, and 208 is a metal wiring film.

In this element, a platinum silicide layer 206, an amorphous silicon film 207, and a metal wiring layer 208 as an upper electrode are stacked on an N-type diffusion layer 205, which serves as a lower electrode and is in contact with an N-type diffusion layer 203. It is something that With this configuration, an electric field greater than that which causes avalanche breakdown of the amorphous silicon film is applied between the electrodes, and a part of the amorphous silicon film changes due to the Joule heat generated at that time. As a result, a conventional electrically programmable read-only memory element was created due to the low resistance region formed and the rectifying properties of the Schottky diode between the platinum silicide layer and the N-type diffusion layer. .

As a second conventional example, U, S, PAT'ENTNo,
A case will be described in which a polycrystalline silicon layer provided on a silicon substrate is used as one electrode of a memory element, as in No. 4442507. In this device, an N-type doped polycrystalline silicon layer with a low impurity concentration is provided on an N-type doped polycrystalline silicon layer with a high impurity concentration, and a platinum silicide layer, an amorphous silicon film, It is a stack of metal interconnects serving as the upper electrode, and uses a Schottky diode between a platinum silicide layer and an N-type doped polycrystalline silicon layer with a low impurity concentration.

[Problems to be Solved by the Invention] However, the above-mentioned conventional technology has the following problems due to the provision of an N-type diffusion layer with a low impurity concentration in order to create a Schottky junction.

■ The resistance value after programming increases by the resistance of the N-type diffusion layer with a low impurity concentration. (Examples 1 and 2) ■ When programming elements are formed in series on the same lower electrode, the lower electrode resistance becomes higher by the amount of the N-type expansion layer with a lower impurity concentration. (Example 1) ■ The resistance value of the thin N-type diffusion layer is easily subject to voltage modulation, so the resistance value after programming tends to fluctuate in the operating state. (Example 1) ■ To create a Schottky junction When providing a thin N-type diffusion layer, it is necessary to take into account the overlapping valley, which increases the pattern area (Example 1).
) Therefore, the present invention aims to solve these problems, and its purpose is to make the resistance value after programming low and stable, the pattern area is narrow, and the resistance value is low and stable in the applied electric field. The object of the present invention is to provide a semiconductor device which irreversibly changes from high resistance to low resistance and has rectifying properties after the change.

[Means for Solving the Problems] A semiconductor device of the present invention includes: a semiconductor layer laminated on a semiconductor layer having a first conductivity type and containing an impurity of a second conductivity type different from the first conductivity type in the lattice; It is characterized by consisting of an upper electrode layer.

[Function 1 According to the above structure of the present invention 1 For example, an amorphous semiconductor film or a polycrystalline semiconductor film or a polycrystalline semiconductor film containing a P-type impurity with a low impurity concentration, laminated on an N-type semiconductor,
Semiconductor films whose crystals have been destroyed by ion implantation, etc.
Before programming, P-type impurities exist between the lattices of the amorphous or polycrystalline semiconductor film, and it is electrically inactive. For this reason, it exhibits high resistance regardless of the direction of voltage application. As the crystal structure of a part of the program film containing a low concentration of P-type impurities changes, the P-type impurities become activated, and the above-mentioned laminated film, which was a high resistance element, becomes a diode with a low resistance value of forward characteristics. It is something that changes.

〔Example〕

FIG. 1 shows a main cross-sectional view of a semiconductor device according to a first embodiment of the present invention, in which 101 is a P-type semiconductor substrate made of silicon or the like, 102 is a field insulating film, and selective oxidation film made of silicon oxide film or the like is shown. membrane, 103 is a No type diffusion layer,
104 is an interlayer insulating film made of silicon oxide film or the like; 105
is an amorphous silicon film containing P-type impurities, 106
is a metal wiring film made of a single layer or a laminated layer of a high melting point metal such as aluminum, Mo, Ti, W, etc. or a silicide of the high melting point metal. In this way, the lower electrode N″
”-shaped diffusion layer 103, an amorphous silicon film 105 containing impurities, and a metal wiring film 106 serving as an upper electrode.
By adopting a laminated structure, as explained in the action,
A program element that has a high resistance before programming becomes an element with rectifying properties by programming.6 Next, a detailed explanation will be given of the manufacturing method of this embodiment.

First, after forming a selective oxide film 102 on a P-type semiconductor substrate 101, an N3-type diffusion layer 103, which will become the lower electrode of the program element, is formed by ion implantation using 60 keys of phosphorus to form a 4×10 cm-” Next, a silicon oxide film is deposited by the CVD method to form an interlayer insulation II! 104, and an N0 type diffusion layer 1 is formed by implanting into a P type semiconductor substrate 101 made of Zinocon and performing thermal annealing.
03 and the amorphous silicon It! containing P-type impurities, which is the main part of the program element. After forming the openings necessary to make the connection through the
An amorphous silicon film was deposited by decomposing SiH+ at a low temperature of 1,500 mL, and then enriched boron was added at 60 keV by ion implantation to obtain the desired diode characteristics. 101″c
m-", an amorphous silicon film l○5 containing P-type impurities is formed.Finally, after processing the amorphous silicon film into a desired pattern, a laminated film of barrier metal and aluminum is sputtered. The metal wiring film 106 is formed by filling the metal wiring film 106 using a method and processing it into a desired pattern.

Through the above steps, an element of the present invention whose resistance value irreversibly changes from high resistance to low resistance due to an applied electric field and has rectifying properties is formed.

Here, the selective oxide film 102 is formed not only by the so-called LOCO3 method, but also by forming a groove in a semiconductor substrate and filling the groove with an insulator, which is a structure used in a so-called grooved element isolation region. Furthermore, the barrier metal is one using a high melting point metal such as Mo, Ti, or W, a silicide of the high melting point metal, or a nitride of the high melting point metal. This barrier metal is usually located below the aluminum.

Next, the electrical characteristics of the above element will be explained.

As a prototype example, concentrated boron is 1×10110 with 60 keys.
A case will be described in which an amorphous silicon film containing P-type impurities implanted with 1fi" is used, and the diameter of the through hole at the location covered with the amorphous silicon film is 1.2 μm1. Figure 3 (a) shows the program Figure 3(b) shows the electrical characteristics after programming by applying an electric field to cause avalanche breakdown and flowing a current of 2 to 3 mA.The electrical characteristics before programming are as follows: Almost symmetrical with respect to the direction of application, at 5V,
It is a high resistance material that allows a current of 1 OnA to flow through it. However, when programmed by applying a negative voltage, it exhibits forward characteristics when a positive voltage is applied to the upper electrode, which is an aluminum film on an amorphous silicon film, and reverse characteristics when a negative voltage is applied. , Incidentally, in the case of an amorphous silicon film that does not contain impurities, after programming, a change in electrical properties of 0 or more that becomes a low resistance object that is almost symmetrical with respect to the direction of voltage application is due to the amorphous silicon film, as explained in the operation. A part of the silicon film undergoes a structural change due to the Joule heat generated by the current, and the P-type impurity is activated, forming a P-N diode between it and the N''' diffusion layer that is the lower electrode. This is thought to be due to

A second embodiment of the present invention uses an N0 type polycrystalline silicon film on an oxide film as the lower electrode instead of the N0 type diffusion layer. FIG. 4 shows a main cross-sectional view of a semiconductor device according to a second embodiment of the present invention, in which 401 is a P-type semiconductor substrate, 402 is a selective oxide film, 403 is an N3-type polycrystalline silicon film, and 404 is an interlayer insulating film. , 405 is an amorphous silicon film containing P-type impurities, and 406 is a metal interconnection film having a two-layer structure in which, for example, aluminum is provided on a pariah layer, as in the previous embodiment. In this way, by using an N'' type crystalline silicon film on an oxide film, not only does the degree of freedom in pattern layout increase, but also the N''' type polycrystalline silicon as the lower electrode can be used as an insulator such as a silicon oxide film. Since it is surrounded by a membrane, the Joule heat generated during programming is less likely to be dissipated, so it can be programmed with a lower current.

In the third embodiment of the present invention, the lower electrode is made of a low-resistance metal such as Mo, Ti, or 'W, or a silicide of these metals, such as Mo5ia, through a through hole, and an N0 type polyamide It is provided with crystalline silicon and P-type amorphous silicon films. FIG. 5 shows a main cross-sectional view of the third embodiment of the present invention, in which 501 is a P-type semiconductor substrate, 502 is an insulating film made of a selective oxide film, 503 is a MoSix film, 504 is an interlayer insulating film, 505 506 is an amorphous silicon film containing P-type impurities, and 507 is a metal wiring film.

Next, the manufacturing method will be explained. First, an insulating film 502 made of a silicon oxide film is formed on a semiconductor substrate 501 made of silicon or the like, and then a metal film 503, for example, MoS, which will become the lower electrode of the program element is formed. Form i z with a thickness of 0.2 μm by sputtering and process into the desired pattern. 0th order. Deposit a silicon oxide film by CVD method to create an insulating film 504 between the eyebrows, and deposit an amorphous silicon film 506 containing P-type impurities. After forming a 0.2 μm thick layer of polycrystalline silicon to form a through hole at the location where it will be formed, phosphorus is ion-implanted to a depth of 4 x 10 cm with a 60 key, annealed and activated in an electric furnace, and N
Forming a crystalline silicon film 505 Next, an amorphous silicon layer of 1,500 layers is formed by decomposing S I H4 at a low temperature of 560° C. using the CVD method, and a desired diode is formed using an ion implantation method. In order to obtain the characteristics, digested boron is 80 keys x 10”
cm-" to 1 x 10"cm-", amorphous silicon l containing P-type impurities is implanted.
Form l@506. After that, by simultaneously etching the N-type crystalline silicon 1!505' and the amorphous silicon film 506 containing P-type impurities,
Process into desired pattern. Finally, a through hole is formed at a location where a direct connection is made to the metal film 503 of the lower electrode, and a barrier metal film and an aluminum film are sequentially deposited by the sppack method to form a metal wiring film 507.
Process into desired pattern.

Through the above steps, the dielectric breakdown programmable read-only storage element of the present invention is formed.

In this example, the CVD method and the ion implantation method were used as the method for manufacturing the P-type semiconductor film, but the sputtering method may also be used, or impurities may be added during the CVD method or sputtering. .

Also, P-type polycrystalline silicon, polycrystalline silicon whose crystals have been destroyed by ion implantation, etc., or crystalline silicon may be used.Furthermore, although a P-type semiconductor film is used, if the lower electrode is a P'' diffused layer may be an N-type semiconductor film.

Mo5it was used as the metal film of the lower electrode, but T
It doesn't matter if it's i S i z or W S i g, or P
Any alycide tank structure may be used, and in this embodiment, the semiconductor substrate may be either P-type silicon or N-type silicon.

In a fourth embodiment of the present invention, the lower electrode is made of a low resistance metal or a metal silicide, such as M.

The N9 polycrystalline silicon film is laminated on Si2, and an amorphous silicon film is provided through a through hole. FIG. 6 shows a main sectional view in the fourth embodiment of the present invention, in which 601 is a P-type semiconductor substrate, 602 is an insulating film made of a selective oxide film, etc., 603 is a MoSix film, 6
04 is an N4 type polycrystalline silicon film, 605 is an interlayer insulating film,
606 is an amorphous silicon film containing P-type impurities;
607 is a metal wiring film.

Next, the manufacturing method will be explained. First, an insulating film 602 made of a silicon oxide film or the like is formed on a semiconductor substrate 601 made of silicon or the like, and then a metal film such as Mo5iz 603, which will become the lower electrode of the program element, is formed. Form 0.2 m by sputtering. After forming polycrystalline silicon to a thickness of 0.2 μm on top of that, 4×10 phosphorus was applied with 60 keys.
'cm-' ion implantation is performed and annealing is performed in an electric furnace to form an N-type crystalline silicon film 604. next,
Metal 111603 and N type crystal silicon ll! 60
4 is processed into a desired shape by photo-etching technology. Thereafter, a silicon oxide film is deposited by the CVD method to form an interlayer insulating film 605, and a through hole is formed at the location where the amorphous silicon film 606 containing P-type impurities is to be deposited. By decomposing S i H4 at a low temperature of 1500 °C, an amorphous silicon layer is formed. After that, by ion implantation method, digested boron was added with 80 keys to obtain the desired diode characteristics.
By typing in the range of ~I Xl○"cm-",
An amorphous silicon film 606 containing P-type impurities is formed and processed into a desired pattern. Finally, N-type crystalline silicon II, which is part of the lower electrode! A through hole is formed at a location to be directly connected to 604, and a barrier metal film and an aluminum film are sequentially deposited by sputtering to form a metal wiring film 607, which is then processed into a desired pattern.

Through the above steps, the dielectric breakdown programmable read-only storage element of the present invention is formed.

In this example, the CVD method and the ion implantation method were used as the manufacturing method of the P-type semiconductor film, but this was replaced by the sputtering method.
I do not care. Further, impurities may be added during the CVD method or sputtering.

Also, P-type polycrystalline silicon, polycrystalline silicon whose crystals have been destroyed by ion implantation, etc. or crystalline silicon may be used.Furthermore, although a P-type semiconductor film is used, the lower electrode may be a P'''' type diffusion layer. In that case, an N-type semiconductor film may be used.

Although M o S i 2 was used as the metal film of the lower electrode, TiS i a or W S i x may also be used.
In addition, a polycrystalline silicon tank structure may also be used. In this embodiment, the semiconductor substrate may be either P-type silicon or N-type silicon.
It doesn't matter if it's silicone or not.

As in the third and fourth embodiments, Mo and Ti are used in the lower electrode.
By using metals such as , W, or silicides of these metals, the resistance value of the lower electrode is lowered, and when programming areas are arranged in series, programming can be performed with a small programming current.

As described above, in the first to fourth embodiments, films formed by the CVD method and the ion implantation method were used as the semiconductor films containing P-type impurities between the lattices, but this film was formed by the sputtering method. It does not matter, or it may be a polycrystalline silicon film into which P-type impurities are ion-implanted, or polycrystalline silicon or crystalline silicon whose crystals have been destroyed by ion implantation, or even a semiconductor film containing P-type impurities between the lattices. However, if the lower electrode is a P4 type diffusion layer, a semiconductor film containing an N type impurity between the lattices may be used. Further, in the third and fourth embodiments, Mo5ia was used as the metal film of the lower electrode, but TiSi2 or WSi2
, W, Mo, etc. may be used.Furthermore, the first
Metal wiring Ml 106 which becomes the upper electrode in the fourth to fourth
．． 406.507 and 607 are aluminum, W, Ti
It goes without saying that single or multilayer films of high melting point metals such as Mo, silicides of these high melting point metals, and nitrides of these high melting point metals can be used.
It goes without saying that the present invention is not limited to the first to fourth embodiments described above, and can be modified in various ways without departing from the gist thereof.

[Effects of the Invention] As described above, according to the present invention, a semiconductor layer laminated on a semiconductor layer having a first conductivity type and containing an impurity of a second conductivity type different from the first conductivity type in the lattice; Due to the structure consisting of an upper electrode layer.

The semiconductor film of the first conductivity type directly under the programming film has a low resistance value, is not subject to voltage modulation, and has a simple structure, so the pattern area is small and the process is simple. have

Furthermore, if the lower electrode is a wiring provided on the substrate, Joule heat is used effectively, so programming can be performed with a lower current. Furthermore, Mo, Ti,
High melting point metals such as W and silicides of these high melting point metals, such as M
If o5iz, Ti5ia, or WSii is used, the wiring resistance of the lower electrode is reduced, so there is an effect that a read-only memory element capable of high-speed operation can be obtained.

[Brief explanation of drawings]

FIG. 1 is a main cross-sectional view showing a first embodiment of a semiconductor device of the present invention. FIG. 2 is a main cross-sectional view showing a conventional semiconductor device. 3(a) and 3(b) are graphs showing the electrical characteristics of the semiconductor device of the present invention, FIG. 3(a) is a graph showing the electrical characteristics before programming, and FIG. 3(b) is a graph showing the electrical characteristics before programming. ) is a graph showing the electrical characteristics after programming. FIG. 4 is a main sectional view showing a second embodiment of the semiconductor device of the present invention. FIG. 5 is a main cross-sectional view showing a third embodiment of the semiconductor device of the present invention. FIG. 6 is a main cross-sectional view showing a fourth embodiment of the semiconductor device of the present invention. 101, 401°102, 402. 103 ・ ・ ・ ・ 501 , 601 ・・P-type semiconductor substrate 502, 602 ・・・Selective oxide film ・・N′″ type diffusion layer 4, 404, 504, 605 ・・・・・Interlayer insulating film 105 , 405, 506, 606 ...... Amorphous silicon containing P-type impurities 106.406.507.607 ...... Metal wiring film 403.505, 604 ...... N0 Type polycrystalline silicon film 503.603
...Mo51□ film 201...P-type semiconductor substrate 202...Selective oxide film 203...N''' type diffusion layer 204... Interlayer insulating film 205...N-diffusion layer 206...Platinum silicide layer 207...
...Amorphous silicon film 208...
・Metal wiring layer and above 106th shame (α) (b) Budget 4 Nagi procedure amendment (voluntary)

Claims (5)

[Claims] (1) A semiconductor device comprising a semiconductor layer laminated on a semiconductor layer having a first conductivity type and containing an impurity of a second conductivity type different from the first conductivity type in its lattice, and an upper electrode layer. (2) The semiconductor layer having the first conductivity type is a diffusion layer, and the semiconductor layer containing impurities of the second conductivity type in the lattice is made of polycrystalline silicon, amorphous silicon, or crystal-destructed silicon. The semiconductor device according to claim 1, characterized in that: (3) The semiconductor layer having the first conductivity type is a polycrystalline silicon layer doped with an impurity, and the semiconductor layer containing the impurity of the second conductivity type is polycrystalline silicon, amorphous silicon, or crystalline silicon. 2. The semiconductor device according to claim 1, wherein the semiconductor device is made of destroyed silicon. (4) The semiconductor layer having the first conductivity type is a polycrystalline silicon layer doped with impurities, and is connected to the underlying metal layer or metal compound layer via a through hole, and the semiconductor layer has the first conductivity type. Claim 1, wherein the semiconductor layer laminated on the semiconductor layer having a conductivity type and containing an impurity of the second conductivity type in the lattice is made of polycrystalline silicon, amorphous silicon, or crystal-destructed silicon.
The semiconductor device described. (5) The semiconductor layer having the first conductivity type is an impurity-doped polycrystalline silicon layer, and the polycrystalline silicon layer is formed on a metal or metal silicide layer, and has through holes. 2. The semiconductor device according to claim 1, wherein the semiconductor layer including the impurity of the second conductivity type connected therebetween is made of polycrystalline silicon, amorphous silicon, or crystal-destructed silicon.