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JPH0380358B2 - - Google Patents

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Publication number
JPH0380358B2
JPH0380358B2 JP57070861A JP7086182A JPH0380358B2 JP H0380358 B2 JPH0380358 B2 JP H0380358B2 JP 57070861 A JP57070861 A JP 57070861A JP 7086182 A JP7086182 A JP 7086182A JP H0380358 B2 JPH0380358 B2 JP H0380358B2
Authority
JP
Japan
Prior art keywords
insulating
insulating layer
melting point
forming
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57070861A
Other languages
Japanese (ja)
Other versions
JPS58186996A (en
Inventor
Katsuhiko Yabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP7086182A priority Critical patent/JPS58186996A/en
Publication of JPS58186996A publication Critical patent/JPS58186996A/en
Publication of JPH0380358B2 publication Critical patent/JPH0380358B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)

Description

【発明の詳細な説明】 本発明はIC、コンデンサー、抵抗等の能動素
子並びに受動素子を多数個実装するための多層回
路基板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer circuit board on which a large number of active elements and passive elements such as ICs, capacitors, and resistors are mounted.

従来、この種の多層回路基板の多層の導体回路
間を絶縁するための絶縁層をスクリーン印刷によ
つて形成する際、下地として存在する回路用導体
の影響を受け、バイアホール形状をスクリーン上
に形成したパターン通りに印刷形成する事が困難
であつた。また、絶縁層材料としては、近年の高
速演算用高密度多層回路基板の必要性から低い比
誘電率、高い熱伝導性、大きい機械的強度等の物
理的特性が要求される為、ガラス粉末と、アルミ
ナ等の無機酸化物粉末の混合物が使用されてい
る。故に形成後の絶縁層は気孔を多く含んでい
る。気孔が多いとメツキ工程などでメツキ液が滲
みこみ、金属が析出して上下の導体層間を短絡さ
せ、絶縁性を劣化させるというような欠点があ
る。
Conventionally, when forming an insulating layer to insulate between the multilayer conductor circuits of this type of multilayer circuit board by screen printing, the shape of the via hole was not printed on the screen due to the influence of the underlying circuit conductor. It was difficult to print according to the formed pattern. In addition, the recent need for high-density multilayer circuit boards for high-speed calculations requires physical properties such as low dielectric constant, high thermal conductivity, and high mechanical strength as materials for insulating layers, so glass powder and A mixture of inorganic oxide powders such as , alumina, etc. has been used. Therefore, the insulating layer after formation contains many pores. If there are many pores, the plating solution will seep in during the plating process and metal will precipitate, causing a short circuit between the upper and lower conductor layers and degrading the insulation.

本発明は上記欠点を除き、気孔を低減すること
により絶縁性の劣化を防ぐと共に機械的強度を大
きくし、しかもバイアホールを確保して上下層導
体との接続を確実に行うことができる多層回路基
板の製造方法を提供するものである。
The present invention eliminates the above-mentioned drawbacks, prevents deterioration of insulation properties by reducing pores, increases mechanical strength, and provides a multilayer circuit that secures via holes to ensure reliable connection with upper and lower layer conductors. A method for manufacturing a substrate is provided.

本発明の多層回路基板の製造方法は、セラミツ
ク基板上に第1導体パターンを形成する工程と、
前記第1導体パターンを含むセラミツク基板の表
面にバイアホール形成用パターンを有するスクリ
ーンを用い高融点のガラス粉末と無機酸化物粉末
とを含む第1の絶縁ペーストをスクリーン印刷し
前記高融点ガラスの軟化点と融点との間の温度で
焼成して前記第1導体パターン上にバイアホール
を有する第1絶縁層を形成する工程と、前記バイ
アホール内に露出する第1導体パターンを含む第
1絶縁層の上に低融点ガラス粉末を含む第2の絶
縁ペーストを塗布し前記低融点ガラスの軟化点よ
り少し高い温度で焼成し第2絶縁層を形成する工
程と、前記第2絶縁膜上に前記スクリーンを用い
て前記第1の絶縁ペーストをスクリーン印刷して
前記第1絶縁層のパターンと整合したパターンを
有する塗布膜を形成し前記第1の絶縁ペーストの
高融点ガラスの軟化点と融点との間の温度で焼成
して第3絶縁層を形成すると同時に第2絶縁層を
溶融させ前記バイアホール内の第1導体パターン
上の第2絶縁層を前記第1及び第3絶縁層に生じ
た気泡内に吸収させて前記バイアホール内の第1
導体パターンの表面を露出させる工程と、前記バ
イアホールを含む表面に前記第1導体パターンと
接続する第2導体パターンを形成する工程とを含
んで構成される。
The method for manufacturing a multilayer circuit board of the present invention includes the steps of forming a first conductor pattern on a ceramic substrate;
A first insulating paste containing high melting point glass powder and inorganic oxide powder is screen printed on the surface of the ceramic substrate including the first conductor pattern using a screen having a pattern for forming via holes, and the high melting point glass is softened. forming a first insulating layer having a via hole on the first conductive pattern by firing at a temperature between a melting point and a melting point; and a first insulating layer including a first conductive pattern exposed in the via hole. forming a second insulating layer by applying a second insulating paste containing a low melting point glass powder thereon and firing it at a temperature slightly higher than the softening point of the low melting point glass; and applying the screen on the second insulating film. screen printing the first insulating paste to form a coating film having a pattern that matches the pattern of the first insulating layer, and forming a coating film having a pattern between the softening point and the melting point of the high melting point glass of the first insulating paste. At the same time, the second insulating layer is melted to form a third insulating layer at a temperature of the first in the via hole.
The method includes the steps of exposing the surface of the conductive pattern, and forming a second conductive pattern connected to the first conductive pattern on the surface including the via hole.

次に、本発明の実施例について図面を用いて説
明する。
Next, embodiments of the present invention will be described using the drawings.

第1図乃至第6図は本発明の一実施例を説明す
るための主な製造工程における断面図である。
1 to 6 are cross-sectional views showing main manufacturing steps for explaining an embodiment of the present invention.

まず、原材料として、アルミナ等で作られるセ
ラミツク基板、Au、Ag/Pd等の貴金属を含む厚
膜導体形成用ペースト、800℃の軟化点と1000℃
の融点を有する第1のガラス粉末とアルミナ粉末
とを含む第1絶縁ペースト、500℃の軟化点と850
℃の融点を有する第2のガラス粉末を含む第2絶
縁ペーストを用意する。
First, as raw materials, a ceramic substrate made of alumina etc., a thick film conductor forming paste containing noble metals such as Au and Ag/Pd, a softening point of 800℃ and a softening point of 1000℃.
a first insulating paste comprising a first glass powder and an alumina powder having a melting point of 500°C and a softening point of 850°C;
A second insulating paste is provided that includes a second glass powder having a melting point of °C.

次に、第1図に示すように、セラミツク基板1
の上に厚膜形成用ペーストを使用しスクリー印刷
法により第1導体パターン2を形成する。この上
に第1の絶縁ペーストをスクリーン印刷法で印刷
し、乾燥し、第1絶縁ペースト塗布層3を形成す
る。このとき、スクリーンには後の工程で形成さ
れる第2導体パターンを第1導体パターン2に接
続させるためのバイアホール7を有しているもの
を用いる。
Next, as shown in FIG.
A first conductor pattern 2 is formed thereon by a screen printing method using a paste for forming a thick film. A first insulating paste is printed on this by a screen printing method and dried to form a first insulating paste coating layer 3. At this time, a screen having via holes 7 for connecting the second conductor pattern formed in a later step to the first conductor pattern 2 is used.

次に、第2図に示すように、第1絶縁ペースト
塗布層3を基板1と共に850℃で焼成して第1絶
縁層4を形成する。この焼成で第1絶縁層4には
気孔5が多数発生する。
Next, as shown in FIG. 2, the first insulating paste coating layer 3 is fired together with the substrate 1 at 850° C. to form a first insulating layer 4. A large number of pores 5 are generated in the first insulating layer 4 by this firing.

次に、第3図に示すように、第2絶縁ペースト
を全表面に塗布し、530℃で焼成してバイアホー
ル7を埋めた第2絶縁層6を形成する。
Next, as shown in FIG. 3, a second insulating paste is applied to the entire surface and fired at 530° C. to form a second insulating layer 6 filling the via holes 7.

次に、第4図に示すように、第1図に示した第
1絶縁ペースト塗布層3を形成したときのスクリ
ーンと第1絶縁ペーストとを用い、第1絶縁ペー
スト塗布層3と同じパターンを有する第3絶縁ペ
ースト塗布層3′とバイアホール7とを形成する。
Next, as shown in FIG. 4, the same pattern as the first insulating paste coating layer 3 is formed using the screen and the first insulating paste used when forming the first insulating paste coating layer 3 shown in FIG. A third insulating paste coating layer 3' and a via hole 7 are formed.

次に、第5図に示すように、第3絶縁ペースト
塗布層3′を基板1と共に850℃で焼成し、第3絶
縁層9を形成する。このとき、第2絶縁層6は融
点が850℃であるから、この焼成時に溶融し、第
1及び第3絶縁層4,9の気孔5,10内に入り
込む形で吸収されるので、バイアホール7中の第
1導体パターン2上の第2絶縁層6の大部分はな
くなり、導体表面が露出する。
Next, as shown in FIG. 5, the third insulating paste coating layer 3' is fired together with the substrate 1 at 850° C. to form a third insulating layer 9. At this time, since the second insulating layer 6 has a melting point of 850°C, it melts during firing and is absorbed into the pores 5 and 10 of the first and third insulating layers 4 and 9, so that the via hole Most of the second insulating layer 6 on the first conductor pattern 2 in 7 is removed, and the conductor surface is exposed.

次に、第6図に示すように、厚膜導体形成用ペ
ーストを用いてスクリーン印刷、乾燥、焼成して
第2導体パターン11を形成する。
Next, as shown in FIG. 6, a second conductor pattern 11 is formed by screen printing, drying, and baking using a paste for forming a thick film conductor.

以上の工程を必要回数繰返えせば多層回路基板
を得ることができる。この実施例で示したよう
に、軟化点と融点の異なる2種の絶縁ペーストを
用いることにより、バイアホールがつまることな
くパターン通りに印刷形成でき、かつ気孔をも塞
ぎ、水分等の吸収による絶縁劣化を防いだ多層回
路基板が得られる。
A multilayer circuit board can be obtained by repeating the above steps a necessary number of times. As shown in this example, by using two types of insulating pastes with different softening and melting points, via holes can be printed according to the pattern without clogging, and the pores can be closed to provide insulation by absorbing moisture, etc. A multilayer circuit board that prevents deterioration can be obtained.

本発明は、以上説明したように2種の絶縁ペー
スト2種の焼成温度を用いて緻密な絶縁層を形成
する事により、上下層導体の接続を微細なバイア
ホールを介して確保し、しかも絶縁特性の優れた
多層回路基板を得るという効果がある。
As explained above, by forming a dense insulating layer using two types of insulating paste and two different firing temperatures, the present invention secures the connection between the upper and lower layer conductors through fine via holes, and also provides insulation. This has the effect of obtaining a multilayer circuit board with excellent characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第6図は本発明の一実施例を説明す
るための断面図である。 1…セラミツク基板、2…第1導体パターン、
3…第1絶縁ペースト塗布層、3′…第3絶縁ペ
ースト塗布層、4…第1絶縁層、5…気孔、6…
第2絶縁層、7…バイアホール、8…第2絶縁
層、9…第3絶縁層、10…気孔、11…第2導
体パターン。
1 to 6 are cross-sectional views for explaining one embodiment of the present invention. 1... Ceramic substrate, 2... First conductor pattern,
3... First insulating paste coating layer, 3'... Third insulating paste coating layer, 4... First insulating layer, 5... Pore, 6...
2nd insulating layer, 7... via hole, 8... second insulating layer, 9... third insulating layer, 10... pore, 11... second conductor pattern.

Claims (1)

【特許請求の範囲】[Claims] 1 セラミツク基板上に第1導体パターンを形成
する工程と、前記第1導体パターンを含むセラミ
ツク基板の表面にバイアホール形成用パターンを
有するスクリーンを用い高融点のガラス粉末と無
機酸化物粉末とを含む第1の絶縁ペーストをスク
リーン印刷し前記高融点ガラスの軟化点と融点と
の間の温度で焼成して前記第1導体パターン上に
バイアホールを有する第1絶縁層を形成する工程
と、前記バイアホール内に露出する第1導体パタ
ーンを含む第1絶縁層の上に低融点ガラス粉末を
含む第2の絶縁ペーストを塗布し前記低融点ガラ
スの軟化点より少し高い温度で焼成し第2絶縁層
を形成する工程と、前記第2絶縁膜上に前記スク
リーンを用いて前記第1の絶縁ペーストをスクリ
ーン印刷して前記第1絶縁層のパターンと整合し
たパターンを有する塗布膜を形成し前記第1の絶
縁ペーストの高融点ガラスの軟化点と融点との間
の温度で焼成して第3絶縁層を形成すると同時に
前記第2絶縁層を溶融させ前記バイアホール内の
第1導体パターン上の第2絶縁層を前記第1及び
第3絶縁層に生じた気泡内に吸収させて前記バイ
アホール内の第1導体パターンの表面を露出させ
る工程と、前記バイアホールを含む表面に前記第
1導体パターンと接続する第2導体パターンを形
成する工程とを含むことを特徴とする多層回路基
板の製造方法。
1. Forming a first conductor pattern on a ceramic substrate, and using a screen having a pattern for forming via holes on the surface of the ceramic substrate including the first conductor pattern, using a high melting point glass powder and an inorganic oxide powder. forming a first insulating layer having via holes on the first conductor pattern by screen printing a first insulating paste and baking at a temperature between the softening point and melting point of the high melting point glass; A second insulating paste containing low melting point glass powder is applied on the first insulating layer including the first conductor pattern exposed in the hole, and is fired at a temperature slightly higher than the softening point of the low melting point glass to form a second insulating layer. forming a coating film having a pattern matching the pattern of the first insulating layer by screen printing the first insulating paste on the second insulating film using the screen; The insulating paste is fired at a temperature between the softening point and the melting point of the high melting point glass to form a third insulating layer, and at the same time, the second insulating layer is melted to form a second insulating paste on the first conductor pattern in the via hole. a step of absorbing an insulating layer into bubbles generated in the first and third insulating layers to expose the surface of the first conductive pattern in the via hole, and forming the first conductive pattern on the surface including the via hole. A method for manufacturing a multilayer circuit board, comprising the step of forming a second conductor pattern to be connected.
JP7086182A 1982-04-27 1982-04-27 Method of producing multilayer circuit board Granted JPS58186996A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7086182A JPS58186996A (en) 1982-04-27 1982-04-27 Method of producing multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7086182A JPS58186996A (en) 1982-04-27 1982-04-27 Method of producing multilayer circuit board

Publications (2)

Publication Number Publication Date
JPS58186996A JPS58186996A (en) 1983-11-01
JPH0380358B2 true JPH0380358B2 (en) 1991-12-24

Family

ID=13443760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7086182A Granted JPS58186996A (en) 1982-04-27 1982-04-27 Method of producing multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS58186996A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3940881A1 (en) * 1989-07-04 1991-01-17 Conver Osr Ozean Service Repar COUPLING PIECE FOR DETACHABLE CONNECTION OF CONTAINERS
DE4042710C2 (en) * 1990-09-25 2002-11-28 Macgregor Conver Gmbh Coupling piece for connecting containers

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59142B2 (en) * 1977-12-23 1984-01-05 株式会社東芝 Multilayer thick film circuit board

Also Published As

Publication number Publication date
JPS58186996A (en) 1983-11-01

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