JPH0345545B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an integrated circuit constituting a reference level supply circuit of a master slice LSI that outputs a reference level of an emitter pull logic.

(2) Technical background With the advancement of digital circuit technology, high-speed processing is required. Emitsutakatsu pull logic (hereinafter referred to as ECL) is commonly used for these high-speed processes. Meanwhile, with advances in semiconductor integrated circuit technology, ECL's master slice LSI
has also been put into practical use. This ECL master slice
LSIs are capable of high-speed processing depending on the purpose and are also compact.

(3) Conventional technology and problems In the ECL circuit, the input signal becomes high (H) depending on the voltage value.
A reference voltage is required to determine the level and low (L) level. Some also require a current source to drive the ECL circuit. Therefore, ECL
The circuit requires a bias circuit that generates a reference voltage and also has a current source for driving.

Conventionally, the bias circuit of the ECL circuit in a master slice LSI was placed within each cell, and supplied a reference voltage and drive bias current to the gate circuit within the cell. FIGS. 1a and 1b show the cell configuration of the master slice LSI and the layout inside the cell. For example, a 5×5 cell C is placed on the CHP of an LSI chip,
Bonding pad BP is placed around its outer periphery. Each cell C consists of four gate circuits G sandwiching a bias circuit BC, as shown in FIG. 1b. For example, one cell can perform OR,
NOR gate works.

In other conventional configurations, the LSI is divided into external cells that connect to circuits outside the LSI and internal cells that perform logic processing within the LSI, and each of these cells has the aforementioned bias circuit. External cells had a bias circuit that outputs a reference voltage level value in order to maintain a constant logic level with the external circuit, while internal cells had a simple bias circuit because they were not connected to the external circuit. .

FIG. 2 shows the cell configuration. External cell EXC is arranged around the outer periphery of internal cell INC, and bonding pad BP is further arranged outside of it.

FIG. 3 shows the circuit configuration of the bias circuit BC that generates the reference voltage value required by each gate circuit G of the external cell EXC and the internal cell INC. The output V _BB of the bias circuit BC is input to the reference input terminal of each gate circuit.

FIG. 4a shows the bias circuit BC, b and c the gate circuit G, and d the structure of the bias circuit and gate circuit on the cell, respectively. The bias circuit BC consists of transistors Tr ₁ ′ and Tr ₂ ′ and resistors r ₁ , r ₂ , and r ₃ , and a constant voltage is maintained by a negative feedback circuit using transistors.
V _BB is generated and placed between the gate circuits G on the cell as shown in FIG. 4d. The gate circuit in FIG. 4b includes transistors TrG ₁ and TrG ₅ and resistors RG ₁ to _{RG 3.}
The bases of transistors TrG ₃ and TrG ₄ are the input G _iM in FIG. 4d, and the transistors
The emitter of TG ₁ ' is the positive output G+ in Fig. 4d,
The emitter of transistor _TrG2 is the negative output G-. Further, the output V _BB of the bias circuit BC is input to the base of the transistor TrG ₅ . The gate circuit in Fig. 4c is the transistor of the gate circuit shown in b.
A transistor TrG ₆ is inserted between the emitters of TrG ₃ , TrG ₄ , and TrG ₅ and a resistor RG ₃ , and its gate serves as a bias input V _CS for driving.

In the conventional method described above, a reference voltage is supplied to a plurality of gates, for example, four gates, from one bias circuit. This supply method has a problem in that it requires a large amount of power because it includes a plurality of reference voltage generation circuits.

Ideally, a system is desired in which one bias circuit supplies voltage to all gates on the chip. However, from one bias circuit directly many
In the method of supplying the reference voltage to the ECL, noise is added to the reference voltage due to the switching operation of the ECL, and this noise is transmitted to other sources via the bias circuit.
As described above, a plurality of bias circuits, for example, about four, are supplied from one bias circuit in order to influence the ECL, slow down the operating speed, and the driving ability of the bias circuit.

(4) Purpose of the Invention The present invention is intended to solve the above-mentioned problems.The purpose of the present invention is to reduce power consumption, prevent malfunctions due to fluctuations in power supply voltage, and enable the switching operation of an ECL to match the operating speed of other ECLs. It is an object of the present invention to provide an integrated circuit that constitutes a reference level supply circuit for an ECL master slice LSI that does not affect the ECL master slice LSI.

(5) Structure of the Invention The present invention is characterized by a plurality of internal cells including emitter-coupled logic gates, a bias cell that is provided in common to the plurality of internal cells and generates a predetermined voltage, and a bias cell that generates a predetermined voltage. and a bias buffer circuit that supplies the predetermined voltage generated in the bias cell to the internal cell, and the predetermined voltage is used as a reference voltage applied to the reference side transistor in the emitter-coupled logic gate. It is located in an integrated circuit.

(6) Examples of the invention The present invention will be explained in detail below using the drawings.

FIG. 5 shows the structure of a cell according to the first embodiment of the present invention. External cell EXC on chip CHP,
A bias cell SBC for generating a reference voltage and multiple internal cells INC are arranged in sequence. External cell EXC is a cell for coupling with an external circuit, and its bias voltage is input from bias cell SBC. The internal cell INC is a cell in the internal logic circuit and has an internal bias buffer INB. The internal bias buffer INB is a buffer circuit for inputting the reference voltage obtained from the bias cell SBC to the gate circuit in the internal cell. 1
The reference voltage generation bias cells SBC output a reference voltage to each bias buffer INB of a plurality of internal cells.

FIG. 6 shows a circuit diagram of a second embodiment of the present invention. The reference voltage generating bias cell SBC in the bias cell SBC generates a reference voltage V _BB ', and outputs the reference voltage V _BB to the gate circuit G in the internal cell INC via the internal buffer INB.

FIG. 7 shows a circuit diagram of a third embodiment of the invention. The bias cell SBC section constitutes a reference voltage generation bias circuit SBCC, and the first power supply V _CC and the second power supply V _EE are a series circuit of a resistor R ₁ and a transistor Tr ₂ ,
Series circuit of resistors R ₂ and R ₃ , transistor Tr ₁ , resistor R ₄ , transistor Tr ₃ , and resistor R ₆ , transistor
Tr ₄ , diodes D ₁ , D ₂ , resistor D ₉ , transistor Tr ₅ , resistor D ₈ , and diode D ₃ are connected by series circuits, and further connected by an internal bias buffer circuit group INBS. The transistor _Trn0 , the diode _Dn0 , _Dn1 , the resistor _Rn0 , the transistor _Trn1 , the resistor _Rn1 , and the diode _Dn2 are connected by a series circuit. Also, the connection point between resistor R ₂ and resistor R ₃ is transistor Tr ₄
At the base of transistors Tr ₁₀ ~ Trn ₀ , resistor R ₁
The connection point between the collector of the transistor Tr ₂ and the collector of the transistor Tr 2 is connected to the bases of the transistors Tr ₅ , Tr ₁ , Tr ₁₁ to Trn ₁ , respectively. Furthermore, the base of transistor Tr ₂ is connected to the collector of transistor Tr ₃ . The emitter of the transistor Tr ₃ is connected to the base of the transistor Tr ₂ via a resistor R ₄ , and its collector is connected to the collector of the transistor Tr ₁ . The base of the transistor Tr ₂ is connected to the power supply V _EE via a resistor R ₅ . Naturally, when the collector current of transistor _Tr1 increases, the emitter current also increases. As the emitter current increases, the base current of the transistor _Tr2 also increases. Furthermore, its collector current increases. As a result, the base voltage of transistor Tr ₁ decreases and transistor Tr ₁
The collector current of decreases. That is, the transistors Tr ₁ and Tr ₂ and the resistor R ₄ constitute a negative feedback circuit, and the current flowing to the collector of the transistor Tr ₁ is almost constant. In other words, with this circuit configuration, the current flowing through the resistors R ₂ and R ₃ is almost constant regardless of the power supply voltage, and the current flowing through the transistors Tr ₄ , Tr ₁₀ to Trn ₀
The base current of is constant. Transistor Tr ₄ ,
The emitters of Tr ₁₀ to Trn ₀ output the first bias voltage, and for the reason described above, this output is also approximately constant.

Diodes D ₁ , _{D 2} , D _{10 -Dn 0} , D ₁₁ -Dn ₁ are connected to the emitters of the transistors Tr ₄ , Tr 10 -Trn 0 and output as a second bias voltage, and this voltage is also naturally The result is almost constant. For example, the first
If the power supply voltage of the second power supply is approximately -1.3V, the second power supply voltage is approximately -2.8V.

The emitters of the transistors Tr ₅ , Tr ₁₁ to TRn ₁ output a third power supply voltage. This voltage is also approximately constant, and when the first power supply voltage is approximately -1.3V, approximately -3.7V is output.

Transistor TR ₃ is a temperature compensation transistor, and performs temperature compensation in conjunction with diode D ₃ . For example, compensation is achieved by changing the junction area of a diode on a chip and the junction area between the emitter and base of a transistor so that the current flowing there changes with temperature. The above-mentioned compensation utilizes the fact that the temperature characteristics change depending on the current density flowing through the junction of the diode and the junction between the emitter and base of the transistor. These operations are described in a paper published on pages 362 to 367 of the IEEE Journal of Solid State Circuits, published in October 1973, entitled "Complete Compensation System that Eliminates the Disadvantages of Conventional ECL".
ECL (authors Miller, Owens, and Verhofschütt).

In the circuit described above, the first bias voltage is
It is used as a reference voltage to determine the H level and L level of the ECL circuit. The second bias voltage is
This is the reference voltage when multiple ECL inputs are connected in series, that is, in the case of a series gate. Third
The bias voltage is used as a bias voltage for operating each gate circuit. Note that the second and third bias voltages may not be necessary depending on each gate circuit used.

The bias buffer circuit group INBS consists of multiple bias buffer INBs, and one bias circuit
INB is transistor Trn ₀ , Trn ₁ , diode
It consists of Dn ₀ , Dn ₁ , Dn ₂ and resistors Rn ₀ and Rn ₁ . The operation of this bias buffer circuit group INBS has been described above, but to explain in more detail, the transistors Tr ₁₀ to Trn ₀ constitute an emitter follower, and the emitter serves as an output terminal for the reference voltage of the internal cell. Since it is an emitter follower, this transistor performs current amplification operation and the voltage gain is approximately 1.
Outputs a voltage approximately equal to voltage _BB '. The transistors Tr ₁₁ to Trn ₁ also constitute emitter followers, and since the voltage V _CS ' is applied to them, their emitters output a voltage approximately equal to that voltage. That is, the external reference voltage output also has a similar circuit, and the internal cell reference voltage and bias voltage have approximately the same voltage value as the external reference voltage.

(7) Effects of the Invention As is clear from the above, the present invention has a bias cell SBC having a reference voltage generation function for a plurality of gate cells, and outputs the reference voltage of the bias circuit through a bias buffer circuit. A voltage is supplied to each gate circuit G, and the number of bias circuits is smaller than that of the conventional circuit, resulting in lower power consumption. It also prevents the switching operation of the ECL from affecting the operating speed of other ECLs. Furthermore, according to the present invention, the number of reference voltage generation circuits is reduced, so that it can withstand power fluctuations.
The reliability of the LSI also increases.

[Brief explanation of drawings]

Figures 1 and 2 are cell configuration diagrams of conventional chips, Figure 3 is a bias supply circuit configuration diagram, and Figure 4 is a circuit diagram of a bias supply circuit.
Figure a is a bias circuit, Figures 4 b and c are gate circuits, Figure 4 d is a bias circuit on a cell, and a configuration diagram of the layout of the gate circuit. Figure 5 is a cell layout configuration of the first embodiment of the present invention. 6 is a circuit configuration diagram of a bias supply according to a second embodiment of the present invention, and FIG. 7 is a bias circuit diagram of a third embodiment of the present invention. EXC...external cell, SBC...bias cell, bias circuit, INB...internal buffer, G...gate circuit, _R1 ~ _R8 , _R10 ~
_Rn0 , _R11 ~ _Rn1 ...Resistance, _D1 ~ _D3 , _D10 ~ _Dn0 ,
_D11 ~ _Dn1 , _D12 ~ _Dn2 ...Diode, _Tr1 ~
_Tr5 , _Tr10 ~ _Trn0 , _Tr11 ~ _Trn1 ...Transistors.

Claims (1)

[Claims] 1: a plurality of internal cells including emitter-coupled logic gates; a bias cell that is provided in common to the plurality of internal cells and generates a predetermined voltage; and the predetermined voltage generated by the bias cell. a bias buffer circuit for supplying a bias buffer circuit to the internal cell, wherein the predetermined voltage is used as a reference voltage applied to a reference transistor in the emitter-coupled logic gate. 2. The integrated circuit according to claim 1, wherein the predetermined voltage is configured to be used as a drive voltage for the emitter-coupled logic gate.