JPH034338A - Debug system for information processor - Google Patents

Abstract

PURPOSE:To omit an interface for debug by storing a program for debug from a debugging device through a general interface and executing the debug with the program for debug itself. CONSTITUTION:At a debugging device side, when a processor 21 is activated, a program D for debug is loaded from a file 30 to a RAM 23 by a loading program L for debug in a ROM 22. The processor 21 sends an interruption signal 54 for debug, and the program D for debug and data in the RAM 23 through a connection code 45 to an information processor. The program D and data are stored in a RAM 3 according to a program L stored in a ROM 2. At the time of debugging, an interruption signal generating circuit 24 of the debugging device outputs the signal 54. At the information processor side, an interruption level converting part 15 connects an interruption signal line 51 to an interruption signal line 52. Thus, an interruption controller 13 decides the interruption level with the highest priority, and a control part 1 execute a debug processing priorly to all processing.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to debugging of an information processing device, which allows debugging to be performed easily.

(Prior art) Conventionally, for debugging and fault diagnosis of information processing equipment,
The main control element within the information processing device is pulled out from the IC socket, and the connector of the debugging device is connected to this IC socket. Furthermore, some conventional information processing devices were equipped with a debugging interface.

FIG. 2 is a block diagram showing the configuration of a conventional information processing device.

The illustrated information processing device includes a control unit 1, a read-only
It consists of a memory (hereinafter referred to as ROM) 2, a random access memory (hereinafter referred to as RAM) 3, a regular interface controller 4, a debugging interface controller 5, and the like.

The control unit 1 includes a processor 11 and a register 12.

The processor 11 takes out the data stored in the RAM 3 into the register 12, performs arithmetic processing on the data, and stores the data in the RAM 3 again.

The register 12 consists of a high speed storage element like Ichi.

The ROM 2 stores a loading program for loading programs during normal processing and a basic control program.

The RAM 3 temporarily stores programs, data, arithmetic processing results, etc. for normal processing.

The interrupt controller 13 determines the interrupt level of the control section 1. This interrupt controller 13 is
When the interrupt signal line 52 connected to the debugging interface circuit 5 becomes high level, the highest priority interrupt level is determined.

The status register 14 is a register that stores status information of the control unit 1.

The data bus 8 connects the control unit 1, ROM 2, RAM 3, interrupt controller 13, and status register 14.
, a regular interface controller 4, and a debugging interface circuit 5.

The address bus 9 connects the control unit 1, ROM2, and RAM.
3 and the status register 14.

The regular interface controller 4 is, for example, for the well-known R3232C interface, and is used to transmit and receive interrupt signals and data using a predetermined communication method. An interrupt signal line 53 and a data bus 8 are connected to one end of this common interface controller 4. A common connector 6 is connected to the other end of the common interface controller 4 .

The debugging interface circuit 5 has an interrupt signal line 52
, the data bus 8 and the address bus 9 are directly connected to the debug connector 7. Therefore, the debugging connector 7 is a large connector with a capacity of, for example, 128 bins.

On the other hand, the debug device is configured as follows.

The debug device shown in FIG. 2 includes a processor 21, an RO
M22, RAM23, interrupt signal generation circuit 24,
Debug interface circuit 25 and display 2
7, a keyboard 28, a printer 29, etc.

The processor 21 debugs the information processing device via the connection code 35 according to the debugging program D stored in the RAM 23.

The ROM 22 stores a debug loading program L that loads a debug program D from the file 30 into the RAM 23 .

The RAM 23 stores the debugging program D and the processor 2.
Temporarily stores the calculation processing data and calculation results of 1.

The interrupt signal generation circuit 24 generates an interrupt signal 5 for debugging.
Generates 4.

The debugging interface circuit 25 and the debugging connector 26 are connected to the debugging interface circuit 5, respectively.
and the same as the debugging connector 7.

The display 27 displays the results of debugging to the operator.

The keyboard 28 is used by the operator to input parameters during debugging.

The printer 29 prints out the results of debugging.

The file 30 is made up of a magnetic disk or the like, and stores a debugging program D and the like.

The data bus 31 connects the processor 21, the ROM 22,
RAM 23, debugging interface circuit 25,
Display 27, keyboard 28, and printer 29
and the file 30.

The address bus 32 connects the processor 21, ROM 22, RAM 23, and debug interface circuit 25.

Next, the operations of the above-mentioned information processing device and debugging device will be explained.

The debug device and the information processing device are connected by a connection cord 35 through debug connectors 26 and 7. When the processor 21 of the debug device is started, the file 3
The debugging program D is loaded into the RAM 23 by the debugging loading program L in the ROM 22 from o.

The processor 21 has a data bus 31 and an address bus 3.
2, debugging interface circuit 25, debugging connector 26, connection cord 35, debugging connector 7,
The register 1 of the control unit 1 is transferred from the RAM 23 via the debugging interface 5, the data bus 8, and the address bus 9.
Writing data to 2 and writing data from register 12 to RAM 23
Perform debugging such as reading data to.

The debugging results of writing and reading of these data are displayed on the display 27 and printed out from the printer 29.

(Problems to be Solved by the Invention) However, the above debugging method for an information processing device has the following problems.

That is, in addition to the commonly used interface, there is a debugging interface, and since the debugging interface also includes address information, there is a problem in that the amount of hardware increases.

In addition, if a debugging interface is not provided, pull out the processor 11 from the IC socket and connect it to the IC.
You must connect a debug device directly to the socket. This requires disassembling the information processing device, which poses a problem in that debugging becomes extremely troublesome.

The present invention has been made in view of the above points, and it is an object of the present invention to provide an information processing device that has simplified hardware and facilitates debugging.

(Means for Solving the Problems) A debugging method for an information processing device according to the present invention includes a general-purpose interface for connecting the debugging device to the information processing device side;
When loading a debugging program from the debugging device, the debugging device includes a read-only memory storing a debugging loading program for performing loading processing, and a random access memory storing the debugging program; A device side is provided with a general-purpose interface that connects to the information processing device, and a processor that sends the debugging program to the information processing device, and the information processing device debugs according to the debugging program. It is something.

(Operation) In the above information processing device, a debugging program is sent from the debugging device via the general-purpose interface. In an information processing device, as shown in FIG.
A debugging program D is stored in the RAM 3 from the debugging device via the general-purpose interface using the debugging loading program L stored in the OM2. Then, the control unit 1 stores the RAM in accordance with the debugging program D.
3 to the register 12, and reading data from the register 12 to the RAM 3. Thereafter, the control unit 1 sends the results of debugging such as writing and reading data in the register 12 to the debugging device via the general-purpose interface.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a debugging method for an information processing apparatus according to the present invention.

The illustrated information processing device includes a control unit 1, a ROM 2, and an RA.
It consists of M3, general-purpose interface controller 4, etc.

The control unit 1 includes a processor 11 and a register 12 as in the conventional case. Duplicate explanations of the details will be omitted.

The ROM 2 stores a loading program for loading programs during normal processing and a basic control program. In addition to this, ROM2 is
A debug loading program L for loading a debug program D during debugging is stored.

The RAM 3 temporarily stores programs, data, arithmetic processing results, etc. for normal processing. In addition, the RAM 3 temporarily stores the debugging program D, debugging data, debugging results, and the like.

The general-purpose interface controller 41 is, for example, R5.
It is for the H.232C interface and transmits and receives interrupt signals and data using a predetermined communication method. This general-purpose interface controller 41 includes a general-purpose connector 4.
2 are connected.

The interrupt signal output from the general-purpose interface controller 41 is input to the interrupt controller 13 via the interrupt level converter 15.

FIG. 3 is a circuit diagram showing a detailed configuration of the interrupt level converter 15. As shown in FIG.

The interrupt level converter 15 includes a flip-flop 61 and
It consists of two AND gates 62 and 63.

A data line 64 and a trigger signal line 65 are connected to the input terminal of the flip-flop 15.

Further, the output terminal and the inverted output terminal of the flip-flop 15 are connected to one input terminal of each of the AND gates 62 and 63.

By inputting a trigger signal via the trigger signal line 65, the interrupt signal line 51 is connected to the interrupt signal line 52 during debugging, and to the interrupt signal line 53 during normal times. Such signal line switching is performed by a changeover switch (not shown) provided in the information processing device or by software.

FIG. 4 is a circuit diagram showing another example of the interrupt level converter.

The interrupt level converter shown in this figure is the short plug 6.
6. Short plug like this 6
According to No. 6, the hardware can be minimized.

Here, we return to the explanation of FIG.

The interrupt controller 13 determines the level of the interrupt signal according to the priority of the processing performed by the control unit 1. When the interrupt signal line 52 is at a high level, the highest priority interrupt level is determined to ensure accurate debugging.

Further, as in the prior art, the status register 14 is a register that stores status information of the control unit 1.

On the other hand, the debug device is configured as follows.

The debug device shown in FIG. 1 includes a processor 21, an RO
M22, RAM23, interrupt signal generation circuit 24,
It consists of a general-purpose interface controller 43, a display 27, a keyboard 28, a printer 29, and the like.

The processor 21 sends the debugging program D in the RAM 23 to the information processing device via the general-purpose interface 43, the general-purpose connector 44, the connection code 45, the general-purpose connector 42, and the general-purpose interface controller 41 in accordance with the debugging program stored in the RAM 23.

The ROM 22 stores a debug loading program L that loads a debug program D from the file 30 into the RAM 23 .

The RAM 23 stores the debugging program D and the processor 2.
Temporarily stores the calculation processing data and calculation results of 1.

The interrupt signal generation circuit 24 generates an interrupt signal for debugging.

The general-purpose interface controller 43 and the general-purpose connector 44 are connected to the general-purpose interface controller 41, respectively.
and the general-purpose connector 42.

The display 27, keyboard 28, printer 29, and file 30 are the same as those of the conventional ones, so a redundant explanation will be omitted.

The data bus 31 connects the processor 21, the ROM 22,
It connects the RAM 23, the general-purpose interface circuit 43, the display 27, the keyboard 28, the printer 29, and the file 3o.

The address bus 32 connects the processor 21, ROM 22, and RAM 23.

Next, the operations of the above-mentioned information processing device and debugging device will be explained.

The debug device and the information processing device are connected to the general-purpose connector 44.
42 and is connected by a connection cord 45. On the debugging device side, when the processor 21 is started, the file 3
0, a debugging program D is loaded into the RAM 23 by a debugging loading program L in the ROM 22.

The processor 21 of the debug device sends the debug interrupt signal 54, the debug program D in the RAM 23, and the debug data to the information processing device via the connection code 45. The debug program D and debug data transmitted from the debug device are stored in the RAM 3 by the information processing device according to the debug loading program L stored in the ROM 2.

When debugging, interrupt signal generation circuit 2 of the debug device
4 outputs a debugging interrupt signal 54. On the information processing device side, the interrupt level converter 15 connects the interrupt signal line 51 to the interrupt signal line 52 by an operator switching a changeover switch (not shown). As a result, the interrupt controller 13 determines the highest priority interrupt level, and the control unit 1 performs debugging processing with priority over all other processing.

The control unit 1 performs debugging according to the code of the data transmitted from the general-purpose interface according to the debugging program D.

That is, when the code of the transmission data of the general-purpose interface is a code indicating reading of a register in the information processing device, the control unit 1 recognizes that the data following this code is an identification code for identifying the register to be read. . Then, the data in the register specified by this identification code is read and sent back to the debug device via the general-purpose interface.

On the other hand, when the code of the transmission data of the general-purpose interface is a code indicating writing to a register within the information processing device, the control unit 1 receives the register identification code and write data following this code.

Then, data is written into the register specified by the identification code, and then a code indicating completion of writing is returned to the debug device.

Similarly, a storage device such as RAM 3 in the information processing device that can be read and written by the control unit 1 can perform reading and writing debugging.

The results of debugging data reading and writing as described above are displayed on the display 27 of the debugging device and printed out from the printer 29.

The information processing device of the present invention is not limited to the above embodiments.

That is, in the above-described embodiment, the debugging results are displayed on the display of the debugging device, but the present invention is not limited to this, and if the information processing device has a display, the debugging results can be displayed on the display. There is no problem.

(Effects of the Invention) According to the debugging method for an information processing device of the present invention configured as described above, the information processing device stores a debugging loading program, and the debugging program is stored from the debugging device via a general-purpose interface. , I decided to debug it myself using this debugging program, so
The debugging interface can be omitted and the amount of hardware can be reduced. Furthermore, for information processing devices that are not equipped with a debugging interface, it is possible to eliminate the complicated work of disassembling the device and connecting the debugging device to the IC socket of the control element.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the debugging method of the information processing device of the present invention, FIG. 2 is a block diagram explaining the debugging method of the conventional information processing device, and FIG. 3 is the details of the interrupt converter shown in FIG. 1. FIG. 4 is a circuit diagram showing another example of the interrupt converter shown in FIG. 1. 1...Control unit, 2...Read-only memory, 3
...Random access memory, 21...Processor, 41.43...General-purpose interface controller, 4
2.44...General-purpose connector, 45...Connection cord,
L...Loading program for debugging, D...
Program for debugging.

Claims (1)

[Claims] An information processing device includes: a general-purpose interface for connecting a debug device; and a read-only interface that stores a debug loading program for performing loading processing when loading a debug program from the debug device. a memory, and a random access memory for storing the debugging program, and the debugging device includes: a general-purpose interface for connecting to the information processing device; and a processor for transmitting the debugging program to the information processing device. An information processing device comprising: the information processing device debugging according to the debugging program.