JPH0338604B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a position detection device for a numerically controlled machine tool, and particularly to a position counter that counts pulses from the encoder in a system using an incremental shaft encoder for position detection, and a shaft of the encoder. The present invention relates to a device for detecting a discrepancy in the rotational angular position of a coupled drive motor shaft.

Conventionally, in numerical control devices that detect position by attaching an incremental shaft encoder to the rotating shaft of the drive motor, when detecting a discrepancy between the count value of a reversible counter that counts pulses from the encoder and the rotational angular position of the drive motor, , by using two shaft encoders, or by having one shaft encoder generate short interval pulses for position detection and long interval pulses for position error detection. This is done by storing a count value corresponding to the position where the pulse is generated in memory and comparing the count value of the reversible counter at the time when the pulse for position error detection occurs with the value stored in the memory. Ta.

In the conventional method, the pulse for position error detection is generated accurately, and it is effective when only the reversible counter has a counting error or only the pulse for position detection has a generation error. If there is an error, the pulse interval for position error detection is long, causing a delay in detection and causing a major accident.

The present invention has been made in order to solve the above-mentioned problem, and the present invention has a counter that counts the position detection pulses from the encoder. During rotation, while the position error detection command signal is input from the numerical control device, two signals are generated: the rotation signal and the count value zero signal that is generated when the content of the counter is zero. It checks whether the signals are generated at the same time and if only one of the two signals is generated, it is determined that the contents of the counter and the rotational position of the drive motor do not match, and a position error detection signal is output. It is intended to do so.

Examples will be described below with reference to the drawings. In FIG. 1, 11 is a drive motor, and 12 is an incremental shaft encoder connected to the output shaft of the motor 11, which generates a-phase, b-phase, and Z-phase channel signals CHA, CHB, and CHZ. Signal CHA,
CHB has a phase difference of 90° with respect to motor 11.
The direction of rotation can be determined. Signal CHZ
is a one-rotation signal generated every one rotation of the encoder 12.

Reference numeral 13 denotes a gate to which the clock signal CP is input, and the channel signals CHA, SY, CHB, and SY output from the gate 13 are signals synchronized with the clock CP.

14 is the channel signal CHA・SY, CHB・
Initialization signal inputted by SY, CHZ and given from the computer side of the numerical control device main body
A clear signal CL is issued in response to Sini.

15 is a counting section including an up-down counter, which receives channel signals CHA・SY, CHB・SY,
When the encoder 12 is rotated clockwise, the count value increases and when the encoder 12 is rotated counterclockwise, it decreases.
Further, the number of times counter 15 is set to zero by the clear signal CL. Motor 11 when this zero is cleared
The rotation angle position of is the origin of the position data.

16 is an n double precision counter, where n=4 in this embodiment, and channel signals CHA・SY,
CHB, SY, and CHZ are input, and in order to quadruple the accuracy, the counter 16 forms 2-bit data.

17 is an error detection section which receives a channel signal.
CHA・SY, CHB・SY, CHZ and counting section 15
When the count zero signal g is input and the channel signal CHZ is given, if the signal g is issued, there is no error signal ERROR, but if only one of CHZ and g is given, an error signal is generated.
Give ERROR to the counting machine side of the NC device. Signal Sch
is given by the computer to activate this check function.

FIG. 2 is a circuit diagram embodying the concept of FIG. 1 shown in a block diagram. In the figure, 21 indicates each channel signal CHA, CHB, CHZ (in the figure, CHA-H,
Compatible with CHB-H, CHZ-H) through photocouplers PC1, PC2, PC3 to provide noise resistance.
It is a conversion circuit for insulating the power supply, and the output of each photocoupler PC1, PC2, PC3 is inputted to inverters T1, T2, T3 with Schmitt triggers.

Reference numeral 13 denotes the gate shown in FIG. 1, which has flip-flops FFA and FFB1 and receives a clock signal CP. T4 and T5 are inverters. Clock CP of channel signals CHA, CHB
Signals CHA・SY, CHB・SY synchronized with FFA,
It is given from the Q terminal of FFB1.

Flip-flop FFB2, NAND gate 22,
23 and exclusive OR gate 24 constitute a circuit that generates a signal for controlling timing, and flip-flop FFB2
The Q output of FFB1 is input to the J terminal.
The output of FFB2 is input to its K terminal.
Gives an output value delayed by one clock from the output of FFB1. NAND gate 22 connects the output of FFA and FFB
The output signal a is input to the DN terminals of counters CNT1, CNT2, and CNT3 that constitute the up-down counter 15, and subtraction is possible when a=1. At 0, addition is possible.

Furthermore, the NAND gate 23 is inputted with the output of the FFA and the output of the exclusive OR gate 24, and its output signal b is sent to the counters CNT1 and CNT described above.
2. Channel signal CHA which is input connected to each terminal of CNT3 and makes each count ready for counting.
Alternatively, it is possible to count 1 for 1 pulse of CHB. The Q output of FFB1 and the output of FFB2 are respectively input to the exclusive OR gate 24, and its output signal C is also input to the exclusive OR gate 24.
NAND gate 25 and flip-flop FFZ
is input to an AND gate 29 forming the J input of.

The NAND gate 25 is a circuit that constitutes the zero loader shown in FIG. 1, and the signal C, the Q output of the FFA, the signal CHZ, and the output signal d of the exclusive OR gate 27 are input to the NAND gate 25, respectively. The output signal e is output from each counter mentioned above.
When the input is connected to the terminals of CNT1 to CNT3 and the same signal e=0 is given, the logical values given to the A, B, C, and D terminals of each counter are output to the output terminals QA, QB, QC, and QD. loaded.
In the figure, the A, B, C, and D terminals of each counter are LG
In other words, since it is set to 0, the output QA, QB,
QC and QD will all be set to 0.

The exclusive OR gate 26 is a circuit for configuring the n double precision counter shown in FIG.
The Q output of FFB2 is input, and its output signal f is transmitted to the register R that constitutes the buffer register 31.
It is input to the lowest bit terminal of 1, and is equivalent to the binary conversion of the channel signals CHA and CHB in which the lower bits of the up-down counter 15 are gray coded. Therefore, n = 4, that is, a quadruple precision counter. It has been realized.

Furthermore, the check signal Sch (see Figure 1) given from the computer of the NC device and P5 (+5 Volt) indicating a logical value of 1 are input to the exclusive OR gate 27, and its output signal d creates the initialization command signal e. In Fig. 1, the signal d is used for the signal d.
Although Sch and Sini are represented as separate signals, Sch=Sini and Sini=d in FIG. That is, when initialization is not performed in FIG. 2, position error detection is always performed.

The inverter T6 and the exclusive OR gate 28 are normal when the count value zero signal g and the rotation signal CHZ are generated simultaneously or when both are not generated.
The error detection unit 17 generates a signal h to indicate an abnormal state when only one of the above occurs.
This is a circuit for inputting.

A circuit 17 consisting of FFZ and an AND gate 29 corresponds to the error detection section shown in FIG. 1, and a check signal Sch is input to the clear terminal of FFZ.
When Q = 0, the output of the AND gate 29 becomes 1, and when Q = 1 by the next clock CP, an ERROR signal is given to the NC computer side.

The NAND gate 30 mentioned above has each counter.
Signal from output terminal MAX of CNT1 to CNT3
When MAX is input and each MAX output = 1
When NAND is established, the output signal g is applied to the gate 28. Note that the counter outputs QA, QB, QC, and QD are all 0 from this MAX terminal.
When , the signal MAX=1 has a logic value of 1; otherwise, the signal MAX=0 has a logic value of 0.
is output. Therefore, the NAND gate 30 provides a pulse signal g when each counter becomes 0.

Regarding the connections of the signal terminals of the up-down counter 15 that have not been mentioned so far, regarding the terminals CLK and RIPL, the counters CNT1, CNT2, and CNT3 shown here are the same, and these counters cannot be used alone. This is a 4-bit binary up-down counter that operates in synchronization with the clock pulse CP that is input to the clock terminal CLK terminal, but by using two or more of these counters, it is possible to use the ripple clock terminal RIPL of the lower setting counter. By connecting the clock terminals CLK of the uppermost counters (the ripple clock terminal RIPL of the uppermost counter CNT3 is connected to NC, that is, No.
−Connection (no connection). ) A bit binary count that is an integer multiple of 4. In the figure, three of these counters are used, so an up-down counter with a binary count of 4×3=12 bits is realized.

Regarding connecting the QD output terminal of counter CNT3 to LG, the incremental shaft encoder 12 in this embodiment has a pulse generation number of 2048 pulses/
Since the rotation is 2048 = 2 ¹¹ , the number of bits in the binary count up/down counter is 11.
It turns out that. Therefore, in order to output zero every 2048 counts, it is necessary to use an 11-bit binary count up-down counter, and the logical value will be 1 only when the logical values of the up-down output terminals of this 11-bit binary count are all 0. A function is required to output . In order to satisfy this function, as shown in the figure, the output terminal of the most significant bit, that is, the output terminal of the 12th bit, that is, the most significant bit output terminal QD of the counter CNT3, must be connected to LG (GND, where the logical value is 0) so that the logic value of the output terminal QD is always 0. ).

Regarding the connection with the buffer register 31, the lowest bit output terminal QA of the counter CNT1 is output as an input signal to the third bit terminal 1D of the register R1, and the counter
The second bit output terminal QB of CNT3 is the register R.
It is output as an input signal to the most significant bit terminal 2D of No.3. (The names of the data input terminals of each register in the buffer register 31 are as follows:
3D, the second bit terminal is 4D, the third bit terminal is 1D, and the most significant bit terminal is 2D. )
Reference numeral 31 denotes a buffer register required for inputting the count value counted by the up-down counter 15 into the computer of the NC device, and is composed of three registers R1, R2, and R3. A clock CP is input to the CLK terminal of each register R1 to R3. Also, from the computer side, the signal i is given to each R1 to R3, and each counter CNT1 to CNT
The output of FFB3, the signal f, and the Q output of FFB2 are taken into registers R1 to R3 by the signal i and latched.

Also, the signal j from the computer side is for each R1 to R3,
This signal j is input to the N terminal, and the register R
The terminal outputs 2Q, 1Q, 4Q, and 3Q of terminals 1 to R3 are taken into the computer side as position data. In the end, in addition to the 10 bit signals from the counters CNT1 to CNT3, the output f of the gate 26 and the Q output of the FFB2 are input as the lowest and next bit signals to the registers R1 to R3, making up a total of 12 bits. This forms position data.

The position data given to the computer side is indicated by out1, out2, ...out12 from the lowest level.

FIG. 3 is a timing chart showing the interrelationships of the main signals in FIG. In the figure, time t
1 is the first command signal (initialization command signal Sini = 1)
It represents the state of each signal at the time of initialization when zero is loaded from the zero loader 16 to each counter of the counting unit 15 based on the rotation signal CHZ (CHZ=1) in response to the rotation signal CHZ (CHZ=1), and it represents the state of each signal at time t2, t3, t4 represents the state of each signal when the ERROR state is detected in the position error detection state (Sch = 1), and times t2, t3, and t4 in the upper right corner of Fig. 3 represent each signal in the normal case. At time t2 at a in the lower right corner, the contents of the counter 15 are +1 higher than the normal count value, even though the counter 15 is generating a zero count signal (g=0). Rotation signal CHZ is not generated (CHZ=
This represents the state of each signal (CHZ, g, h, ERROR) when the ERROR state is detected.At time t3 at b, the contents of the counter 15 are higher than the normal count value. -1 state occurs, and even though the rotation signal CHZ (CHZ = 1) is generated, the count value zero signal is not generated from the counter 15 (g = 1), so an ERROR state is detected. It represents the state of each signal (CHZ, g, h, ERROR) at time t4 at c, the rotation signal CHZ is missing, and the count value zero signal (g
= 0) Rotation signal despite being generated
This represents the state of each signal when an ERROR state is detected because CHZ is not generated (CHZ remains at 0).

As explained above, in the present invention, the command signals Sini and
By using CHZ, the up-down counter 15 is cleared in advance so that the rotation angle position is set at any given rotational angle position of the drive motor. Using the signal g given when the contents of the counter becomes zero, the motor rotation and counter 15
By doing so, it is possible to detect any discrepancy in the contents of each rotation of the encoder. Therefore, it is possible to detect any error or mismatch between the feed motor used in the feed drive system of a numerically controlled machine tool and the driven body even during a very short movement distance during driving.

There are various ways to use the error detection signal ERROR, but a monitoring program must be prepared in advance on the computer side.
Check the degree of signal generation or
By monitoring the value of the buffer register when an ERROR signal is generated and checking the size of the error each time,
It is also possible to check for phenomena such as unnecessary or thinning due to vibrations associated with CHB or machine drive.

Considering that the channel CHZ is given more stably during driving than CHA and CHB, if an ERROR signal is given due to an increase or decrease in CHA or CHB due to mechanical vibration or electrical noise, the computer side from registers R1 to R3 or counter
It is practical to give a command to forcefully clear CNT1 to CNT3.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a detection device according to the present invention;
Figure 2 is a circuit diagram embodying the main parts of Figure 1;
The figure is a time chart showing the interrelationships of the main signals in the circuit of FIG. 2 in the count-up state. 11...Motor, 12...Encoder, 13...
...gate, 14...zero loader, 15...up-down counter, 16...n double precision counter, 17
...Error detection section.

Claims (1)

[Claims] A motor is used as a drive source for one-axis movement, and a motor is connected to the motor as a position detector for the rotational position of the motor, and N position detection pulses (CHA) per rotation and the position detection pulse are connected to the motor as a position detector for the rotational position of the motor. A numerically controlled machine tool that uses an incremental shaft encoder that outputs N position detection pulses (CHB) per revolution with a phase difference of 90° from (CHA) and one rotation signal pulse (CHZ) per revolution. In the position detection device, position detection pulses (CHA,
an N-ary up-down counter that counts the position detection pulses using a signal obtained from a CHB), initializes the count contents using an initialization signal, and generates a count value zero signal when the count contents are zero; In response to a first command signal (initialization command signal Sini) from the numerical control device for initialization, the N-ary up-down counter is operated based on a rotation signal (CHZ) given from the encoder every rotation. A zero loader that provides a signal to initialize the value, and a second command signal (error check command signal) for performing an error detection operation from the numerical control device.
While the rotation signal (CHZ) and the count value zero signal that occurs when the contents of the N-ary up-down counter are zero are being generated at the same time, it is checked whether or not the two signals are being generated. When only one of them occurs, it is assumed that a mismatch between the content of the N-ary up-down counter and the rotational position of the motor that rotates the encoder is detected, and a position error detection signal (mismatch signal) is detected.
A position error detection device for a numerically controlled machine tool, comprising: an error detection section that outputs an error (ERROR);