JPH0337200Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a sampler circuit for sampling and detecting high-speed input signals, and particularly relates to a sampler circuit for measuring input absolute value voltage with high speed and high accuracy.

[Prior art and its problems]

In sampler circuits that use switch elements such as diodes, the input voltage and hold voltage are not equal because the common mode impedance of the bias circuit is finite and the sampling period is too short. For this reason, it is common to provide feedback. Feedback methods include a pulse stretcher method (feeding back an output signal to a hold capacitor) and a feedback method to a bias circuit (hereinafter simply referred to as "feedback method"). FIG. 3 is a circuit diagram of a conventional feedback system, and FIG. 4 is an explanatory diagram of its operation. Diode bridge 2 is connected to variable power supplies 7 and 8 via bias resistor 5, and is maintained in an off state during hold. At the time of sampling, positive and negative sample pulses Sp are applied to the sample pulse terminals 3 and 5, respectively, the diode bridge 2 is turned on, and the input voltage Vi applied to the input terminal 1 is sampled and applied to the hold capacitor 9. , is held. sample voltage
V _cH is outputted to an output terminal 11 via an amplifier 10. Here, the output voltage Vo is fed back to the variable power supplies 7 and 8, and the bias voltage of the variable power supplies 7 and 8 is -
V _B1 and V _B2 are controlled so that their average value is equal to the hold voltage V _CH . In Figure 4,
indicate the voltages at the points in FIG. 3, respectively, and due to the superposition of -S _p1 and +S _p , change from the voltage level +V _B2 and from -V _B1 . +V _B2 , -
V _B1 indicates the voltage level after control. As shown in Figure 4, if V _i = V _CH , the positive and negative S _p is V _i
Distance equal to (V _cH ) (initial voltage value is −V _B1 ,
It will rise (fall) from V _B2 ), and the upper and lower 4
The diodes are on for equal periods of time (between _t1 and _t2 ).

Here, if not controlled as above,
For example, only the top (bottom) two diodes are turned on at the sample time, while the bottom (top) two diodes remain off. When such an operation is performed, the operating current of each diode at the time of sampling is different, so that V _i and V _CH do not match accurately.

In order to match V _CH with V _i with high precision, −V _Bi
It is necessary to turn on the four diodes for equal periods so that the average value of +V _B2 and +V B2 matches V _CH . Also, since the putot strap is applied so that the average value of V _B1 and V _B2 becomes V _CH and _Vi , the apparent resistance value R _B is increased (when the diode bridge is on, R _B is large). (need to become).
For these reasons, this method can improve sampling efficiency and linearity. This method is particularly advantageous when sampling the same point (same voltage) of the input voltage V _i multiple times.

However, in this method, the system including the sampling head (including the diode bridge and hold capacitor) and the feedback circuit always forms a closed loop through the off-capacitance of diode bridge 2, so that V _CH and V _p
It takes a considerable amount of time to stabilize. Therefore, it is difficult to quickly stabilize the output voltage, detect the absolute value of the input voltage V _i at high speed, and perform analog-to-digital (A/D) conversion. In addition, the influence of feedback voltage is reduced by the diode capacitance and hold capacitance C _H when off.
appears on V _CH , and V _CH no longer represents _Vi with high accuracy. Furthermore, if the next sampling is performed before −V _B1 and V _B2 are stabilized, the average value of these voltages will be V _i
Since the voltage has not been adjusted, uncertainty arises in V _CH .

[Purpose of invention]

The present invention maintains the advantages of the conventional circuit described above, eliminates the disadvantages of the conventional circuit, and provides high speed,
An object of the present invention is to provide a highly accurate sampler circuit.

[Summary of the idea]

In the present invention, two track/hold (T/H) circuits are provided after the hold capacitor _CH , and one T/H circuit tracks the hold voltage V CH of the hold capacitor, while the other T/H circuit follows the hold voltage V _CH of the hold capacitor. The /H circuit is in hold mode and maintains the feedback voltage constant. After tracking V _CH , it is electrically isolated from the hold capacitor. Thereafter, the other T/H circuit follows the output of one T/H circuit to determine the feedback voltage. That is, the system including the sampling head and feedback circuit is always open, and the hold voltage V _CH , output voltage Vo, and bias voltage -
V _B1 and V _B2 are rapidly stabilized by the response speed of the amplifier related to these voltages.

[Example of idea]

FIG. 1 is a block diagram of a sampler circuit according to the present invention, and FIG. 2 is an explanatory diagram of its operation. The same parts as in the circuit of FIG. 3 are given the same reference numerals. A sampling head 3 including a diode bridge 2 and a hold capacitor 9 is connected via an amplifier 10 to a first track/hold circuit (T/H) 14. The T/H 14 includes a switch 15, a hold capacitor 16, and an amplifier 17 (gain=-1), and tracks V _CH and holds it. The output of the T/H 14 is supplied to the output terminal 11 as an output voltage Vo, and also to a second track/hold circuit (T/H) 18. The output voltage Vo is A/D converted and the input voltage V _i
The absolute value of is determined. T/H18 is switch 1
9. Hold capacitor 20 and amplifier 21
(gain=1), and tracks the output voltage of the T/H 14 and holds it. The output of the T/H 18 is applied to the positive terminals of the differential amplifiers 12 and 13 via an attenuator 22. 12,
Reference voltages V _P and -V _P are applied to the negative terminals of the circuit 13, respectively. The outputs of the differential amplifiers 12 and 13 are applied to the sampling head 3 as bias voltages V _B1 and V _B2 . Reference numeral 24 denotes a timing signal generator, which turns on and off the switches 15 and 19 at desired timings as will be described later, and also provides a timing signal to the sampling pulse generator 23.
The sampling pulse generator 23 provides positive and negative sample pulses SP, _{-S P to} the sampling head 3,
The input signal V _i is sampled, detected and held by the hold capacitor 9.

Next, the operation will be explained with reference to FIG. S _P ,−
S _P causes the voltage at point , to change as shown, turning on diode bridge 2 momentarily and holding some of V _i in capacitor 9 (V _HC ), after which or almost simultaneously switch 1
5 turns on and T/H14 follows (track)
mode, and the hold voltage of the hold capacitor 16 follows V _CH . Thereafter, the switch 15 is turned off and the T/H 14 enters the hold mode. After that, switch 19 is turned on and T/H1
8 changes from hold mode to track mode. Therefore, the hold capacitor 20
The hold voltage follows the voltage on hold capacitor 16 and holds that voltage after switch 19 is turned off. That is, -V _B1 and V _B2 change, and the voltage at the point changes as shown.
And the amplifiers 12 and 13 have bias voltages, -V _B1 ,
Control is performed so that the average value of V _B2 is always equal to V _CH , that is, V _CH is at the midpoint between -V _B1 and V _B2 .

Therefore, fast settling occurs before the next sample. Note that the attenuator 22 is designed to adjust its output voltage to V _CH in consideration of the entire circuit system. Moreover, this circuit can of course measure V _i by sampling the same point multiple times. Output voltage V _p
is A/ after T/H18 transitions to hall mode.
D-converted and measured. Note that it goes without saying that the measurement may be performed after the T/H 14 shifts to the hold mode. Also, remove T/H14 and connect the output of amplifier 10 directly to T/H18 (amplifier 1
(The output of 0 is Vo)) The open loop may be made only during sampling. In this case,
When switch 19 is turned on and feedback is applied, it becomes a closed loop, and V _B1 , V _B2
Although the settling time of V CH becomes unclear, V _CH stabilizes quickly.

[Effect of idea]

As mentioned above, the circuit of the present invention is always open and no closed loop is formed.
Each of the voltages V _CH , -V _B1 , V _B2 , and Vo is settled by the response speed of the amplifier used in connection therewith. Therefore, these voltages are stabilized quickly, and their settling time can be easily determined by calculation. Furthermore, the sampling efficiency is determined by the efficiency of the sampling head itself, and the relationship between V _i and V _CH can be easily determined. Therefore, the circuit of the present invention can measure the input absolute voltage value at high speed and with high accuracy while maintaining the advantages of the conventional circuit shown in FIG.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a sampler circuit according to the present invention.
Fig. 2 is an explanatory diagram of the operation of the sampler circuit shown in Fig. 1, Fig. 3 is a circuit diagram of a conventional sampler circuit, and Fig. 4 is an explanatory diagram of the operation of the sampler circuit shown in Fig. 1.
This figure is an explanatory diagram of the operation of the circuit shown in FIG. 3. 2...Diode bridge, 9, 16, 20...
...Hold capacitor, 3...Sampling head, 23...Sampling pulse generator, 24...
...timing signal generator.

Claims (1)

[Claims for Utility Model Registration] (1) A sampling head including a switch and a hold element to which a sample pulse is applied, a track/hold circuit connected to the sampling head, and a track/hold circuit connected to the track/hold circuit. a bias circuit that changes the bias voltage to the sampling head;
A sampler circuit characterized in that said track/hold circuit enters a track mode at a time different from when said sample pulse is applied. (2) The sampler circuit according to claim 1, wherein the track/hold circuit comprises a switch and a hold element. (3) The track/hold circuit is composed of first and second track/hold circuits connected in series, each of the first and second track/hold circuits is composed of a switch and a hold element, and The switch is turned on at different times in the utility model registration claim 1.
Sampler circuit described in section. (4) The sampler circuit according to claim 2 or 3, wherein the bias circuit is controlled so that the average value of two voltage values applied to the sampling head is equal to the hold voltage.