JPH0330175B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a memory access control device for an information processing device such as a vector processor that is capable of processing a large amount of data in each cycle, and particularly to a memory access control device that processes multiple access requests to multiple memory units in parallel. Conflict of access requests is an impediment to improving the speed of parallel processing in memory systems that allow for parallel processing.
This invention relates to an improved mechanism for more efficiently processing. Vector processors are provided with multiple ports for accessing memory. When multiple memory access requests are issued from these multiple ports at the same time, conventionally, just like in a general computer, only one port is selected by a priority circuit and memory access is permitted. was. However, vector processors perform parallel high-speed arithmetic processing on large amounts of data using pipeline control.
It is desirable that memory accesses also be processed in parallel. For this reason, a structure that allows memory to be activated from multiple ports at the same time has been proposed. Figure 1 shows
FIG. 2 is a block diagram for explaining such a conventional example. In FIG. 1, memory access control unit 1 controls four memory units in response to four memory access requests from vector unit 2, scalar unit 3, channel, and processor 4.

It has a circuit 9 for performing priority processing and bus selection for connecting [0]5, [1]6, [2]7, and [3]8.
The access control device 1 also includes ports A10 and B1 that accept memory request addresses and control signals from the vector unit 2, the scalar unit 3, and the channel processor 4.
1. Port C12, port D13, and memory unit

Output buffer registers 18, 1 connected to address buses 14, 15, 16, 17 to [0] 5, [1] 6, [2] 7, [3] 8, respectively
9, 20, and 21. Each address bus 14-17 receives one memory request address during one cycle. Furthermore, each memory unit has an interleaved configuration with a plurality of banks. Here, when a certain port issues a memory access request, the main conditions under which that access is prohibited are: (a) The bank to which the address to be accessed belongs is in a busy (operating) state. (b) The address bus to the memory unit is used in conflict with access requests from other ports. Since the time that a memory request address exists on each address bus is one cycle period, the bus may be empty in the next cycle, but the memory request address remains on each address bus for one cycle, but the bus may be empty by the time the accessed memory bank is completed. Several additional cycle periods are required during which the bank is busy and unavailable. Also, if the address bus conflicts with access requests from other high-priority ports, in other words, if there is conflict at the memory unit level, even if they do not conflict with each other at the bank level, and Even if the bank you are trying to access is not busy,
Access request is not granted. In consideration of the above points, the present invention provides that when there are competing access requests to the same memory unit, if the bank containing the access request address of the port with a higher priority is in a busy state, For example, instead of entering a standby state while monopolizing the bus, it would instead accept an access request from a port with a lower priority if it is for a bank that is not in a busy state. It is an object of the present invention to provide a plurality of memory units having a plurality of independently accessible memory banks. , in a data processing system in which each of the memory units has a common access bus to the memory banks within the memory unit; In order to control access requests, a plurality of ports with different priorities are used to accept the addresses of the plurality of access requests, and the addresses of the plurality of access requests from the plurality of ports are set as the priority and other control information of the port. a priority and bus selection circuit that selects and supplies buses to the plurality of memory units in parallel; a bus check circuit that checks whether or not an access request is a bank bus, and controls the priority and bus selection circuit based on the resultant information; and a bus contention check circuit for checking whether or not there is contention on the address bus for the memory unit and controlling the priority and bus selection circuit based on the resultant information, wherein the one access source simultaneously accesses the same memory unit. The feature is that when multiple access requests are made, even if the access request of a high priority port is bank-busy, if there is an access request of a low-priority port that is not bank-busy, the access request is selected. The present invention provides a memory access control device. FIG. 2 is a block diagram for explaining an embodiment of the present invention. In the figures, components common to the system of FIG. 1 are labeled with the same reference numerals. Each port [A] 10, [B] 11, [C] 12,
[D] 13 are set with addresses and control flags (OP codes, etc.) at which memory access requests are made from the vector unit 2, scalar unit 3, and channel processor 4, respectively. The upper 2 bits of the address set for each port are the memory unit address, and the following 3 bits are the memory unit address.
The bit is the bank selection address. The remaining lower bits are the intra-bank address. The upper 5 bits of the address of each port, that is, the memory unit address and the bank selection address, are input to the bus check circuit 22, and the upper 2 bits of the memory unit address are further input to the bus contention check circuit 23. , the presence or absence of the bank's busy state and the address
The presence or absence of bus contention is checked. The checked results are input to the priority and bus selection circuit 24. In the absence of bus contention and bank busses, an address in a port will be transferred to the address bus 14 towards its corresponding memory unit.
The priority and bus selection circuit 24 selects appropriate registers 18 to 17 to
21, and access to the memory is activated. Busy check circuit 22 sends a signal indicating an access request port for which the bank containing the address to be accessed is not busy to priority and bus selection circuit 24 to permit memory access for the access request of that port. However, if the bank is not busy but there is bus contention, then the higher priority port is selected to initiate the access. If the access request with a higher priority is a bank visit,
Since the bus check circuit 22 does not indicate the port to the bus selection circuit 24, the circuit 24 will select the low priority access request port that is not bank busy. Furthermore, bus contention among them is indicated to circuit 24 by bus contention check circuit 23. FIG. 3 is a diagram for explaining the schematic structure of the visit check circuit shown in FIG. 2, and FIG. 4 shows an example of the circuit structure of a portion thereof. Busy check circuit 22 includes a number of latches 25 which hold an indication of the busy status of each bank for all memory units. FIG. 3 illustrates the contents of 32 latches for a case where the number of memory units is 4 and the number of banks is 8. Figure 4 shows the memory unit in particular.

For bank #0 of [0] and bank #7 of memory unit [3], a latch 25 for displaying the bank busy state, a 6-input logic gate 26 for reading the busy state, and a common gate for the whole The 32-input OR gate 27 is shown. Each latch 25 is set by an access activation signal for that bank, and reset by an access termination signal upon completion of a data read or write operation. For each bank, it accepts the upper 2 bits of the memory unit address and the next 3 bits of the bank selection address of the access request address from ports A to D, and responds to the unique input address corresponding to each bank. Four 4-input logic gates 26 with decoder function are provided. Five of the six input terminals of the logic gates 26 in all units and all banks are commonly connected in a port series for the upper five bits of address from ports A to D. The remaining one input terminal of each of the four logic gates 26 in each bank is commonly connected to the Q output of the latch in each bank. When the latch is in the reset state, the Q output becomes "0" and a signal "1" is output from the logic gate of the port that requested access to that bank to the OR gate. When a certain bank is in the busy state, the Q output of the latch 25 belonging to that bank becomes "1" and is applied to the logic gate 26. At that time, even if any of the ports A to D has an access request to that bank, the output is "0" because the logic gate 26 is prohibited. The OR gate 27 is provided corresponding to each port, and receives all the outputs of the logic gates 26 of the same port series of each bank as OR inputs. The output visit of the OR gate 27 corresponding to each port becomes "1" only when the access request for that port does not encounter a bank visit. FIG. 5 shows the bus contention check circuit 23 of FIG.
An example of the configuration is shown below. The circuit 23 includes six comparators 28 to perform six ₄ C ₂ matching comparisons on the memory unit address consisting of the upper two bits of the access request address of ports A to D. When conflicting access occurs on the address bus, that is, when duplicate access requests are made from each port to the same memory unit, the memory unit addresses match, so the corresponding comparator outputs “1”. ``Produces an output. FIG. 6 shows a configuration example of a priority circuit in the priority and bus selection circuit 23 of FIG. 2. In FIG. For convenience, the port priorities are set as A>B>C>D. This circuit consists of gates 29-32 having inputs connected to the comparator outputs of FIG. Gate 29 is for port A, which has the highest priority;
In this case, the access request from port A is unconditionally permitted. Gate 30 is for port B. In this case, on the premise that port B access is not busy, the port B access request is permitted under the following conditions. ●When the signal in Figure 5 is =.●When port A is busy even though A=B.Similarly, access request permission for port C in Figure 6 is 31-1, 31-2, 31-3. This is the logic pointed to by the gate of port C, and if there is no request with a higher priority than the port in the same MSU, and even if there is a request, if the bank accessed by that port is busy, access permission for port C is granted. Port D
Since the access is the same, the explanation will be omitted. In this way, the access of a low priority port is the same as the access of a high priority port.
Improved performance by allowing access to a lower priority port if the other port is not allowed by bank visit, rather than unilaterally disallowing access when there is a conflict in MSU. can be expected. Further, in this embodiment, fixed priority is assigned to port A to port D, but it goes without saying that the priority assignment may be made variable according to conventional technology. The remainder of the priority and bus selection circuit 24 includes the above-described bus check,
It consists of a well-known switch circuit for transferring an address from a port whose access request has been granted through bus contention check and priority processing to the corresponding appropriate register 18-21.
Although not shown in the figure, the data bus is also switched using conventional methods. The circuits described above merely show one specific example, and many details can be modified. For example, the bus check circuit 22 may be designed to indicate only bank-busy ports. The present invention improves the efficiency of memory access by improving the conventional access control based on busses at the memory unit level to perform access control based on busses at the memory bank level. The effect is significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional memory access control device, FIG. 2 is a block diagram of an embodiment of the memory access control device of the present invention, and FIGS. 3 and 4 are a block diagram of a conventional memory access control device. Example of circuit configuration, Figure 5 is an example of the configuration of the bus contention check circuit in Figure 2,
FIG. 6 shows an example of a circuit configuration of a portion of the priority and bus selection circuit of FIG. In the figure, 1' is a memory access control device of the present invention, 2 to 4 are memory access sources, 5 to 8 are memory units, 9 is a priority and bus selection circuit, 10 to 13...ports, 1
4 to 17... Bus, 18 to 21... Register, 22... Busy check circuit, 23... Bus contention check circuit, 24... Priority and bus selection circuit, 25... Latch for indicating bank busy. , 26...logic gate, 27...OR
Gate, 28... comparator, 29-32... gate.

Claims (1)

[Claims] 1. A data processing system comprising a plurality of memory units each having a plurality of independently accessible memory banks, and each memory unit having a common access bus for the memory banks within the memory unit. In order to control a plurality of access requests issued from one access source to a plurality of memory units, a plurality of ports having different priorities for accepting addresses of the plurality of access requests, and a plurality of ports are provided. a priority and bus selection circuit that selects addresses of a plurality of access requests from the plurality of memory units according to priority and other control information of the port and supplies them to buses to the plurality of memory units in parallel; - Possesses information indicating that the bank is in operation and checks whether or not access requests from the plurality of ports become bank busses, and controls the priority and bus selection circuits based on the resulting information. a bus check circuit for checking whether or not access request addresses of the plurality of ports conflict on the address bus for the memory unit and controlling the priority and bus selection circuit based on the resultant information; When one access source makes multiple access requests to the same memory unit at the same time, even if the access request of a high priority port is a bank bus, the access request of the high priority port is A memory access control device characterized in that if there is a low port access request that is not bank busy, it is selected.