JPH033061A - Peripheral device control system - Google Patents

Abstract

PURPOSE:To start up a processor again by controlling a memory start address in a common memory to be accessed by respective processors, the most significant address and the channel of a peripheral device connected to the system so that the controlled objects only for a processor are discriminated from that for common devices and setting up initializing and operation levels. CONSTITUTION:If a processor (A) 11 is stopped during the operation of both the processors (A) 11, (B) 12 by individual OSs, a common memory access means 13 outputs an initializing request to an initializing means 14. The means 14 executes an initializing instruction for a peripheral device control part 17 to initialize the peripheral device. A common memory access means 13 loads the OS of the processor (A) 11 and sets up the level of the peripheral device and an operation level setting means 15 executes an instruction for setting up an instruction in the control device 17 to set up the operation level of the peripheral device. Consequently, the processor can be started up again without exerting any influence upon the peripheral device used by the other OS.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to a plurality of O3 (Operating System)
Regarding the peripheral device control method in a system where em) coexist, in particular, after one OS is stopped, its O
This invention relates to a peripheral device control method when restarting S.

Conventional technology Conventionally, when one OS in a multi-OS coexistence system stops, the other OS is forcibly stopped, and in the process of restarting both OSes, the status of peripheral devices is cleared and the operating level is was being reconfigured.

Problems to be Solved by the Invention The conventional peripheral device control method described above only had information on the connection status of all peripheral devices connected to the system, so if one OS stops and that OS When restarting automatically, all peripheral devices are unconditionally initialized and their levels are set, so restarting is possible without affecting the peripheral devices used by the other OS at all. The disadvantage is that it cannot be done.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a novel peripheral device control method that makes it possible to eliminate the above-mentioned drawbacks inherent in the prior art.

Means for Solving the Problems In order to achieve the above object, the peripheral device control method according to the present invention includes a shared memory access means that manages memory used by multiple OSes and accesses the shared memory, and a peripheral device state control method. and an operation level setting means for setting the operating level of each OS for the peripheral device control unit.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a peripheral device control method according to the present invention.

Referring to FIG. 1, in this embodiment, a processor (A) 1
In a system in which multiple processors 1 and processor (B) 12 are installed and two OSs run, a shared memory access means 13 that accesses the shared memory 16, an initialization means 14 that clears the state of peripheral devices, and a peripheral It is comprised of an operation level setting means 15 that sets an operation level for the device control section 17.

FIG. 2 is a diagram showing a memory management table. This memory management table 20 manages the memory and shared memory that can be used by each processor when two processors operate on different OSs. 2
1 and the highest used address 22, shared memory 16
made in

FIG. 3 is a diagram showing a peripheral device management table. This peripheral device management table 30 manages all peripheral devices connected to the system, including the device name 31 of the device, channel 32, connection usage status of the peripheral device, dedicated to processor A 33, and dedicated to processor B. 34, shared 35
This table is also created in the shared memory 16.

With the above configuration, processor (A) 11 and processor (B
) 12 are operating on different OSs, and the processor (A) 11 causes a system stop, the shared memory access means 13 reads the peripheral device management table 30 and searches for the channel number 32 of the device dedicated to processor A 33. , issues an initialization request to the initialization means 14 on that channel,
The initialization means 14 executes an initialization command to the peripheral device control unit 17 using the channel given from the memory access means 13, and initializes the processor A dedicated 33 on the zero peripheral device management table 30 that initializes the device. After initializing all the devices, the shared memory access means 13 accesses the memory management table 2.
From 0, during use of processor (A) 11 - start address 2
1 and the highest used address 22, load the OS of the processor (A) 11 from the use start address 21,
The shared memory access means 13 reads the peripheral device management table 30 from the shared memory 16 and sets the level for the peripheral device.
By searching for a device 35 shared with the device 35 and providing the channel 32 to the operation level setting means 15, the operation level setting means 15 executes a level setting command to the peripheral device control unit 17, thereby controlling the operation to the peripheral device. Set the level.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, when a plurality of processors operate on different OSs, a shared memory is provided, and in the shared memory, a start address and a highest address of the memory that can be accessed by each processor are set. By managing the channels of peripheral devices connected to the system by distinguishing between processor-dedicated devices and shared devices, and performing initialization and operation level settings, even if one processor causes a system stop, the other processor The effect is that a processor that has stopped system can be restarted without affecting the operation of the system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure shows a memory management table, and FIG. 3 shows a peripheral device management table. 11...Processor A, 12...Processor 8.1
3...Shared memory access means, 14...Initialization means, 15...Operation level setting means, 16...Shared memory, 17...Peripheral device control unit Patent applicant: NEC Corporation Agent Person Patent Attorney Yutabe Kumagai Diagram 2

Claims (1)

[Claims] In a computer system where multiple processors are installed and multiple OSs share the main memory peripheral device, multiple OSs
A shared memory access means that manages the memory used by the system and accesses the shared memory, an initialization means that clears the status of peripheral devices, and an operation that sets the operating level of each OS for the peripheral device control unit. 1. A peripheral device control method in a multi-OS coexistence system, comprising a level setting means.