JPH0329196A - Sense amplifier - Google Patents

Abstract

PURPOSE: To speed up a reading operation by connecting only one of bit lines to an electric current source when respective memory cells are accessed and deciding which bit line is connected with the state of memory cell. CONSTITUTION: A static RAM cell 10 is provided with two pass transistors 30 and 31, which are connected to a first pair of complementary bit lines 72 and 73, and gates are connected to a word line 70. Also, the gates are connected to a latch 39 expressed with two cross combined inverters 32 and 33. And which bit line is connected to the electric current source is decided with the state of memory cell. Also, faster reading operation of memory cell by a second pair of bit lines 74 and 75 is allowed with four additional transistors 34-37. By this way, that type of memory cell is read at a extremely high speed and moreover with a relatively low electric power.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to integrated circuit differential sense amplifiers, and more particularly to CM
This invention relates to an OS differential current amplifier.

BACKGROUND OF THE INVENTION A general rule in integrated circuits is that faster operating speed requires more power.

This is true even in CMOS integrated circuits.

CMOS static RAM integrated circuits are typically arranged in a matrix of rows and columns of memory cells.

Word lines extend along a row of memory cells to access a particular row. A pair of complementary bit lines extends along a column of memory cells for reading information from (or writing information to) an accessed memory cell selected by one of the word lines.

In one type of CMOS static RAM read operation, for high speed operation, one of the differential bit lines connecting columns of memory cells is coupled to a current source by the selected memory cell, while the other bit line is coupled to a current source by the selected memory cell. Not combined. Which bit line is coupled to the current source is determined by information stored in the selected memory cell.

A problem with high speed operation is the production of relatively small signals on bit lines that operate with small currents and have large capacitances. During read operations, small signals must be converted to full CMOS logic levels as quickly as possible. However, in any design of a high speed sense amplifier that senses bit line signals, mere increases in current are discouraged, since unconstrained power dissipation in integrated circuits is undesirable.

The present invention provides a sense amplifier that can read memory cells of that type at very high speeds but with relatively low power.

SUMMARY OF THE INVENTION The present invention has a column of static RAM cells coupled together by a pair of complementary bit lines, each memory cell having a MOS transistor that couples only one of said bit lines to a current source when accessed. Particularly adapted to integrated circuits. The state of the memory cell determines which bit lines are coupled.

Each of a pair of cascode transistors has its source electrode connected to one of the bit lines.

The invention provides a sense amplifier connected to the drain electrode of each cascode transistor. Sense amplifier is 1
It has a pair of current mirrors, each having an input and an output terminal. The input terminal of each current mirror is connected to the respective drain electrode of one of the cascode transistors, and the output terminal carries a current proportional to the current through the input terminal. An active load is connected to both output terminals of the current mirror. The active load has an output node that is responsive to a difference in current through the output terminals. The voltage at the output node connected to the input terminal of the inverter fluctuates due to the current difference. In this way, the state of the inverter output terminal is determined by the state of the accessed memory cell.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS FIG. 1 illustrates a type of static RAM memory cell that can be read at high speeds. The static RAM cell 10 has two pass transistors 30, 31, which are the first
are connected to a pair of complementary bit lines 72, 73. N
The gates of MOS transistors 30 and 31 are connected to word line 70. The two transistors 30, 31 are also connected to a latch 39 represented by two cross-coupled inverters 32, 33. (The inverter includes complementary PMOS transistors and forms a complementary MOS circuit.) These cross-coupled converters 32 and 33
has two stable states, ``1'' and ``0'' logic states, and thus can store logic states for later accesses.

This information is accessed or "read" by placing a high signal on word line 70, thus turning on pass transistors 30, 31 and thus connecting bit lines 72, 73 to inverters 32, 33. During this successive cycle, the voltage on one of the bit lines remains high in its precharged state and the other goes low.

This state sets the sense amplifier in one state or another, which is connected to the bit lines 72,73.

Similarly, to set the logic state of inverters 32, 33, two pass transistors 30131 are turned on by a signal on word line 70.

The voltage on one of the bit lines 72, 73 is set high and the other low to drive or "write" the memory cell. Latch 39 formed by inverters 32, 33 is set to its logic state.

The four additional transistors 34, 35, 36 and 37 allow faster read operation of the memory cells by the second set of bit lines 74, 75.

NMOS transistors 34, 36 are connected in series, with the source electrode of transistor 36 connected to ground and the drain electrode of transistor 34 connected to bit line 74. The gate 4 electrode of the transistor 36 is connected to the latch 39 of the memory cell, ie the output terminal of the inverter 32 and the input terminal of the second inverter 33. The gate electrode of transistor 34 is connected to second word line 71 .

Similarly, NMOS} transistors 35 and 37 are connected in series, and the source electrode of transistor 37 is connected to ground.
The drain electrode of transistor 35 is connected to second bit line 75 . The gate electrode of the transistor 37 is connected to the latch 39 of the memory cell, ie the output terminal of the inverter 33 and the input terminal of the second inverter 32 . The gate electrode of transistor 35 is connected to second word line 7l.

High speed read operations are performed by turning on transistors 34 and 35 with a signal on word line 71.

The two bit lines 74, 75 are then connected to transistors 36, 37, respectively, which are also "on" or "off" in a complementary manner. The state of the two transistors depends on the information stored in the latch 39 of the memory cell.

If transistor 35 is on, then bit line 74 is connected to ground and transistor 37 is off, so complementary bit line 75 is not connected to ground. If transistor 37 is on, then bit line 75 is instead connected to ground. In this manner, bit lines 74, 75 provide faster access to the state of the memory cells.

FIG. 2A is a generalized diagram of memory cells and bit lines 74, 75. With respect to their bit lines, the memory cell of FIG.
When connected to 75, the current Ist! N! 11! pull.

Current tX82 (including transistors 34, 36) is coupled to bit line 74 and current source 83 (including transistors 3
5, 37) are coupled to bit line 75. Thus, the signal on word line 7l and the information stored in latch 39 determine which one of current sources 82, 83 is switched on.

FIG. 3 illustrates the invention. Since the present invention pertains to high speed read operations of memory cells, FIG. , 73 and related circuitry will be understood by those skilled in the art to reside in a fully integrated circuit device.

As typical of integrated circuit memory devices, memory cell 10
are replicated in a grid array. A number of memory cells are arranged vertically between bit lines 74, 75, with each memory cell connected to a bit line.

A column of memory cells is represented by a RAM core 85. One end of the bit line 74 is connected to the MOS transistor 42.
The other end of the bit line is connected to the source electrode of NMOS transistor 40. Complementary bit line 75 is similarly connected at one end to a small current source represented by transistor 43 and at the other end to the source electrode of NMOS transistor 41.

The two NMOS transistors 40, 41 function as cascode transistors, separating the large capacitance associated with each of the bit lines 74, 75 from the much smaller capacitance associated with the sensing circuitry coupled to the drain electrodes of transistors 40, 4l. .

Without such isolation, a read operation of one of the memory cells in core 85 would be much slower and cumbersome.

The gate electrodes of the transistors 40 and 41 are connected to the reference voltage VR,
, which ideally should be some distance from the supply voltage Vcc, such as Vcc/2. This allows some freedom in the design of the detection circuit. Capacitor 89 is also connected to transistor 40
, 41 and from the power supply voltage transient at ground vRI! Protect F.

A better approach than simply tying the gate electrode to some fraction of the supply voltage is described in a U.S. patent filed on the same day as this application by its assignee entitled "Current Regulator, Threshold Voltage Generator." Disclosed in the application. One of the inventors of this application, William See Plants (Wi.
lliam C., Plants) is the inventor of the second application, which is hereby incorporated by reference.

Additionally, to allow transistors 40, 41 to operate faster, a small current is constantly passed through the transistors so that the source-gate voltage swing is reduced when memory cells in core 85 are read. FIG. 2A shows transistors 42 and 43 connected to current sources 80 and 81, respectively.
Illustrated as.

As illustrated in FIG. 2B, each of the cascode transistors 40, 41 operates at a small supply voltage! . ．． is displaced by By increasing the current through the cascode transistors 40, 41, the transistors operate in a steeper part of the saturation region, so that V. The swing at S is reduced.

FIG. 4 is a circuit diagram of the circuit used to generate the voltage on the gate electrodes Vcs of transistors 42, 43. N
MO3} The transistor 87 and the resistor 86 are connected to the power supply voltage (
Vcc is typically +5 volts) and ground. Transistor 87 is in a diode configuration;
Its gate electrode is therefore tied to its drain electrode.

The source electrode is coupled to ground. The value of resistor 86 is hundreds of kilohms, so the small current (actually Ics)
flows through the resistor and transistor. transistor 4
The gate electrodes of transistors 2 and 43 are connected to the gate electrode of transistor 87 so that transistors 42 and 43 act as current mirrors for the current flowing through transistor 87. Capacitor 88 acts as a cushion against variations in ground voltage.

The present invention uses changes in current, rather than voltage, through bit lines 74, 75 when memory cells in core 80 are read. This provides much faster operation.

The sense amplifier of the present invention has a current mirror connected to each of the drain electrodes of transistors 40,41. The drain electrode of the cascode transistor 40 is connected to the drain electrode of a diode-connected PMOS transistor 46, which when operated draws a current of 1c to the bit line.
Give s or 1sC”l91!N!JE. 1.2-
In one embodiment of the described circuit implemented in micron CMOS technology, Ics is 8 to 20 microamps and ■seNsFL is 150 to 3
00 microamps.

The source electrode of transistor 46 is connected to the Vcc power supply. A second PMOS transistor 48 has its source electrode connected to Vcc and its gate electrode connected to the gate electrode of transistor 46. Transistor 48, scaled by a factor of three, amplifies the current through transistor 46.

Thus, the current through the drain electrode of transistor 48 is three times the current through the drain electrode of transistor 46.

Similarly, PMOS transistors 47 and 49 are connected to the drain electrode of cascode transistor 41 which is coupled to bit line 75.

The drain electrode of PMOS transistor 48 is a diode-connected NM whose source electrode is connected to ground.
OS} connected to the drain electrode and gate electrode of the transistor 60. The drain electrode of the PMOS transistor 49 is also an NMOS transistor whose source electrode is connected to ground.
S} connected to the drain electrode of the transistor 61. The two transistors 60, 6■ have the same size. Their gate electrodes are connected together so that NMOS
Transistor 61 attempts to conduct as much current as transistor 60.

Operationally, the two transistors 60, 6l form a current mirror that functions as an active load. A mismatch between the currents through the two transistors 49, 61 results in a voltage swing at the output node 63. For example, if transistors 48 and 60 carry a larger current (IcS+Isg
NsF. 3 times), transistor 6
1 tries to follow. However, transistor 49 carries a much smaller current (3 times Ics) to transistor 6l.
giving to In this way, the node 6 formed by the drain electrode of the transistor 61 and the drain electrode 49
The capacitance associated with 3 must supply current to transistor 61. The node voltage drops rapidly until the node is very close to ground and transistor 61 is in linear mode.

On the other hand, if transistor 49 is conducting a larger current and transistor 48 is conducting a smaller current, transistor 61, which is trying to follow transistor 60, cannot accept the larger current. Therefore, the node capacitance is charged and the node voltage becomes high near Vcc. Transistor 49 then enters linear mode and ceases tracking the current through transistor 47.

Input terminals of inverter 64 are connected to transistors 49 and 6.
It is connected to a node 63 formed by one drain electrode. The voltage at node 63 may swing from near ground to near Vcc, but the slew rate may be slower than desired. Inverter 64 translates the voltage swing at node 63 to a full CMOS logic level while simultaneously
from any additional capacitance associated with the output node of inverter 64. In this way the completion of the detection operation is accelerated.

Yet another aspect of the invention is that the typically static R
AM is to be laid out, so several columns of memory cells are laid out side by side next to each other. As explained above, a pair of vertical bit lines is associated with each column. There are also horizontal word lines that cross the columns and access memory cells in a column, so that word line signals access memory cells in different columns.

Conventionally, a load element is placed in the bit line current path and produces an operative output voltage for each bit line pair.

A bus transistor is located at a voltage output node associated with each line of the bit line pair. The pass transistor is connected in parallel to some output sense circuit. The multiplexer controller selects only one pair of pass transistors at a time, so only one column is accessed at a time. In this way only one memory cell in a column is accessed at a time.

The problem with this type of arrangement is that the pass transistors add delay to the detection time due to the time required for the signal to propagate through them. This multiplexing arrangement slows down static RAM operation.

The invention also has multiplexing operation, so only one column of memory cells is accessed at a time.

However, because current is used instead of voltage, the read operation is much faster than with conventional multiplexing techniques.

FIG. 3 illustrates four columns of memory cells represented by RAM core 85, which are active load transistors 60,
61 and an inverter 64. Each PMOS transistor 46 associated with each bit line pair 74, 75
, 47 are PMOS transistors 44, 45, which function as current switches.

When turned on, these transistors 44, 45 steal current from transistors 46, 47, so these transistors 46, 47 do not conduct current. The gate electrode of each transistor 44, 45 is connected to a multiplexer control (not shown). When a particular column of memory cells is not selected, the output signal from the multiplexer turns on transistors 44, 45 of that pair. Transistors 46 and 47 are thus non-conductive, as are transistors 48 and 49. When a column is selected, transistors 44, 45 are turned off by multiplexer control. PMOSs 46 and 47 are now active and the resulting current mirror transistors 48, 49 are also active.

The selected column affects the voltage at node 63.

This technique is thus inherently faster than voltage sensing. Transistors 44 and 45 are turned on and turned off at the same time as transistors 34 and 35 in the memory cell are turned on. Multiplexer selection is thus performed in parallel with the core memory cells. No additional delay is added in series with the detection path.

Although the above description provides a full and complete disclosure of the preferred embodiments of this invention, various modifications, alternative constructions, and equivalents may be used without departing from the true scope and spirit of this invention. good. For example, the circuit of this invention is CM
It may be designed with BicMOs technology rather than an OS. Accordingly, the invention should be limited only by the limits of the claims appended hereto.

[Brief explanation of drawings]

Figure 1 shows a high-speed static RA to which this invention is applied.
FIG. 2 is a circuit diagram of one type of M cell. FIG. 2A is a generalized circuit diagram of the static RAM cell of FIG. FIG. 2B is a circuit diagram of a cascode transistor connected to a pair of bit lines, which is also connected to the memory cell of FIG. 1. FIG. 3 is a circuit diagram of the present invention. FIG. 4 is a circuit diagram of a reference voltage generator used in the present invention. In the figure, 10 is a static RAM cell, and 30
, 31 is a pass transistor, 39 is a latch, 86 is a resistor, 87 is an NMOS transistor, 88 is a capacitor, 63 is an output node, and 64 is an inverter.

Claims (6)

[Claims] (1) In a MOS integrated circuit having a column of static RAM cells coupled together by a pair of complementary bit lines, each memory cell, when accessed, couples only one of said bit lines to a current source; The state of the memory cell determines which bit line is coupled, a pair of cascode transistors having first and second source/drain electrodes and a gate electrode, the first source/drain electrode coupled to the bit line. a sense amplifier connected to the second source/drain electrode of each cascode transistor and including a pair of current mirrors having input and output terminals;
The input terminal of each current mirror is connected to a respective source/drain electrode of the cascode transistor, the output terminal carries a current proportional to the current through the input terminal, and both output terminals of the pair of current mirrors an active load connected to the output node, the active load having an output node responsive to a difference in current through the output terminal, and an inverter having an input terminal and an output terminal, the input terminal being connected to the output node. a sense amplifier connected so that the state of the inverter output terminal is determined by the state of the accessed memory cell. (2) the active load includes a first transistor in a diode configuration having first and second source/drain electrodes and a gate electrode, the first source/drain electrode being one of the current mirror output terminals; a second transistor connected to the first transistor and further having first and second source/drain electrodes and a gate electrode, the gate electrode connected to the gate electrode of the first transistor; 2. The sense amplifier of claim 1, wherein a source/drain electrode is connected to the other of the current mirror output terminals and forms the output node. (3) the cascode transistors, first and second
3. The sense amplifier of claim 2, wherein the transistors are of a first polarity and the current mirror includes transistors of a second polarity. (4) The first polarity transistor is an NMOS transistor, and the second polarity transistor is a PM transistor.
4. The sense amplifier of claim 3, which is an OS transistor. 5. The sense amplifier of claim 1, wherein the current through the current mirror input terminal is amplified by a predetermined factor for the gain in the current through the current mirror output terminal. (6) A MOS integrated circuit having a plurality of static RAM cells arranged in rows and columns, each memory cell in a row to be accessed, and each column of static RAM cells held together by a pair of complementary bit lines. coupled, each memory cell couples only one of said bit lines to a current source when accessed, the state of said memory cell determines which bit line is coupled, and a pair of cascode transistors couples one of said bit lines to a current source; and a second source/drain electrode and a gate electrode;
a source/drain electrode of the current mirror is connected to one of the bit lines, a pair of current mirrors have input and output terminals, and the input terminal of each current mirror is connected to a respective source/drain electrode of the cascode transistor. the output terminal carries a current proportional to the current through the input terminal, and an active load is connected to both output terminals of the pair of current mirrors, the active load responsive to a difference in current through the output terminal. an inverter having an input terminal and an output terminal, the input terminal being connected to the output node such that the state of the inverter output terminal is determined by the state of the accessed memory cell. integrated circuit.