JPH03289139A - Manufacture of mos field-effect transistor - Google Patents

Abstract

PURPOSE:To prevent the damage of a gate electrode by stacking a semiconductor film on the whole surfaces of a gate electrode and source and drain regions, which are covered with the gate protective film by an insulating film and the spacer by an insulating film, and then etching back the whole face excellently in controllability so as to expose one part of the spacer and the gate protective film. CONSTITUTION:A gate electrode, which is equipped with a gate protective film 6 consisting of a first insulating film, is formed at the surface of a silicon substrate, and a pacer 8 consisting of a second insulating film is formed at the surface of the gate electrode. Next, by stacking semiconductor films 9, 10, 11, and 12 on the whole face, and etching back them, these semiconductor films are left excellently in controllability of thickness on a source and drain diffusion layer formation planned region, and after removing the gate protective film 6, a conductive film is stacked on the whole face. Next, by ion implantation, a source and drain diffusion layer 14 is formed at the source and drain diffusion layer formation planned region, and by heat treatment, an alloy film of a semiconductor film and a conductor film is formed, and also an unreacted conductor film in contact with the spacer 8 is removed in a self alignment manner. Hereby, the damage of the gate electrode in the formation process of a semiconductor can be prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a MOS field effect transistor, and in particular to a method for manufacturing a MOS field effect transistor, particularly for So I <5 ilicon on Tns.
The present invention relates to a method of manufacturing an MO8 field effect transistor formed on a substrate.

[Conventional technology]

In recent VLSIs, MO8 type field effect transistors with a gate length of about 0.8 μm are being used as the integration becomes higher and smaller. In addition, in MO8 field effect transistors formed on S○■ substrates, the film thickness of the SOI layer is conventionally 05 μm because crystal growth is easy.
A single-crystal layer of about 1.0 m was used. However, 0.5μ
It has been known that when an 801 layer as thick as m is used, the characteristics of the MO8 field effect transistor deteriorate due to two-dimensional effects such as bunch-through and short channel effects.

However, it has recently been reported that the two-dimensional effect and substrate floating effect can be reduced by making the thickness of the SOI layer less than or equal to the maximum depletion layer thickness.

[Problem to be solved by the invention]

However, in an MO8 field effect transistor (MOSFET) having a minute gate length, the two-dimensional effect cannot be sufficiently suppressed unless the thickness of the SOI layer is approximately 50 nm or less. At this time, the conventional SO
, in the IMOS structure, the source and drain diffusion layers must be the same as the channel portion (approximately 50 nm or less), and the sheet resistance in the source and drain diffusion layers becomes high, making it impossible to obtain a sufficient drain current value.

Therefore, a method is used to lower the sheet resistance by siliciding the surfaces of the source and drain diffusion layers.
Since the film thickness of the layer is very thin, about 50 nm or less, sufficient silicidation cannot be performed.

Therefore, a method is used in which a semiconductor film is formed only on the surface of the region where the source and drain diffusion layers are to be formed to increase the film thickness of the region where the source and drain are to be formed, and the upper part thereof is silicided to lower the sheet resistance.

However, when forming this structure, it is difficult to control the thickness of the semiconductor film formed on the surface of the region where the source and drain diffusion layers are to be formed, and there is a risk that the gate portion may be damaged in the process of forming the semiconductor film.

The present invention solves these conventional problems.
The purpose of the present invention is to provide a novel method for manufacturing field effect transistors.

[Means to solve the problem]

A method for manufacturing a MOS field effect transistor of the present invention is a method for manufacturing a MOS field effect transistor formed in a single crystal semiconductor layer on an insulating substrate, in which a gate is provided with a gate protection film made of a first insulating film on the upper surface. A step of forming an electrode and forming a spacer made of a second insulating film on the side wall surface of the gate electrode, and a step of depositing a semiconductor film on the entire surface and etching it back over the area where the source and drain diffusion layers are planned to be formed. A step of leaving the semiconductor film with good film thickness control, a step of depositing a conductor film on the entire surface while removing the gate protective film, and a step of depositing the source and drain diffusion layers in the region where the source and drain diffusion layers are to be formed by ion implantation. , a step of forming an alloy film of a semiconductor film and a conductor film by heat treatment, and a step of removing an unreacted conductor film in contact with the spacer in a self-aligned manner.

[Effect]

The method of forming a semiconductor film with well-controlled thickness on the surface of the region where the source and drain diffusion layers are to be formed in the present invention is to form a semiconductor film with a well-controlled thickness on the surface of the region where the source and drain diffusion layers are to be formed. A semiconductor film is deposited on the entire surface of the region where the source and drain diffusion layers are to be formed, and then etched back of the entire surface is performed in a well-controlled manner to form part of the spacer.
Expose the gate protection film. In this manufacturing method, the gate electrode portion is the first. Since it is covered with the second insulating film, damage such as damage caused by etching or etching process of the film constituting the gate electrode will not be applied to the gate electrode.

In addition, due to the presence of the semiconductor film on the surface of the region where the source and drain diffusion layers are to be formed, the film thickness of the region where the source and drain are to be formed becomes substantially thick enough, and if the semiconductor film is polysilicon, this and the conductor film are This makes it possible to set the thickness to be sufficient to form silicide.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(f) are schematic cross-sectional views showing an embodiment of the present invention in the order of steps.

FIG. 1(a) shows a gate oxide film 4 (5 nm), a gate polysilicon film 5 (
300 layers m), silicon nitride film 6 (20 nm), which is the first insulating film and gate protection film, and polysilicon/7 (30 nm) were sequentially deposited.
cused Ion Beam), E B (Ele
ctron beam) exposure process, and E CR (E
lectronCyclotron Re5o-nan
ce) Gate by dry etching process! This shows the state in which the extreme part is formed.

FIG. 1(b) shows HTO (High Temperat
A silicon oxide film (100 nm), which is the second insulating film, is deposited using ureOxide), and by etching back the entire surface, the silicon oxide film, which is the second insulating film, is deposited in a self-aligned manner on both side walls of the gate electrode part. A state in which spacers 8 made of a film are formed each having a width of 1100n is shown.

Next, FIG. 1(c) shows polysilicon Il (9 (250 nm), which is a semiconductor film, and silicon nitride film 10).
(300nm), silicon oxide film 11 (500nm),
and a flattening agent 12 (1) made of, for example, styrene resin.
The figure shows the state in which µm) were sequentially deposited.

In this state, the entire surface is etched back to the - dotted line AA", and then the silicon oxide film 11, silicon nitride film 10, and polysilicon film 9 are etched at a constant speed to the dashed line BB', as shown in FIG. The state shown in d) is reached.

Subsequently, the silicon nitride film 10 remaining on the regions where the source and drain diffusion layers are to be formed is removed by a wet etching process. In this case, the polysilicon 7 at the top of the gate electrode part plays the role of a protective film for the silicon nitride film 6, and the silicon nitride film 6, which is the gate protective film, is not etched. Further, the polysilicon film 9 remaining on the regions where the source and drain diffusion layers are to be formed and the polysilicon 7 remaining on the top of the gate electrode portion are etched by 50 nm by a low temperature ECR etching process.

As a result of this etching, a polysilicon film 9 of a predetermined thickness remains on the area where the source and drain diffusion layers are planned to be formed, but the polysilicon film 7 at the top of the gate electrode part is completely removed, leaving the area where the source and drain diffusion layers are planned to be formed. The polysilicon film 9 left on the region is separated from other parts, as shown in FIG.
).

In addition, in this etching process, since the selectivity between the polysilicon film and the silicon nitride film is high, the silicon nitride 1116 above the gate electrode part functions as a protective film for the gate electrode part, and the etching process of the gate polysilicon film 5 is performed. , damage such as damage caused by the etching process can be suppressed.

After i&, the silicon nitride film 6 on the upper part of the gate electrode part is removed by a wet etching process, and titanium (not shown), which is a conductive film, is deposited by sputtering.
Through ion implantation and annealing steps, a source/drain diffusion layer 14 is formed on the area where the source/drain diffusion layer is to be formed, and titanium silicide 13 is formed by an alloying reaction between the polysilicon wA9 existing thereon and titanium.

At the same time, due to the alloying reaction between the gate polysilicon film 5 and titanium, titanium silicide 13a is formed on the upper part of the gate electrode, and the gate polysilicon film 5 on the lower part of the gate electrode is replaced with the highly impurity-doped gate polysilicon film 5a.
By converting to , the gate electrode has a polycide structure. Furthermore, unreacted titanium existing in contact with the spacer 8 is removed in a self-aligned manner by a wet etching process using an ammonia-based solution, and a source composed of the highly impurity-doped gate polysilicon film 5a and the titanium silicide 13 is removed. , the drain region and the gate electrode are separated, resulting in the state shown in FIG. 1 (f>).

In this embodiment, a polycide structure made of polysilicon and titanium silicide was used as the material and structure of the gate electrode, but a polycide structure using molybdenum silicide, tungsten silicide, etc. may also be used.

Further, it is not necessary to limit the structure to a polycide structure, and it is also possible to use only these silicides or only polysilicon.

Similarly, for the material of the upper part of the source and drain regions, high melting point metals such as molybdenum and tungsten, high melting point continuous silicides such as molybdenum silicide and tungsten silicide, or polysilicon can be used.

〔Effect of the invention〕

As explained above, the method for manufacturing a MOS field effect transistor of the present invention includes a gate protection film using a first insulating film;
A semiconductor film is deposited on the entire surface of the gate electrode and the regions where the source and drain diffusion layers are to be formed, which are covered by the spacer made of the second insulating film, and then the entire surface is etched back using low-temperature etching.
Part of the spacer is well controlled by CR dry etching.

source by exposing the gate protection film.

A semiconductor film is formed on the surface of a region where a drain diffusion layer is to be formed with a well-controlled film thickness. This manufacturing method is a gate! The extreme part is the first
．． Since it is covered with the second insulating film, damage such as damage caused by etching the film constituting the gate tigM and the etching process will not be applied to the gate electrode. Furthermore, due to the presence of the semiconductor layer on the surface of the region where the source and drain diffusion layers are to be formed, the film thickness of the region where the source and drain are to be formed becomes substantially thick enough to form an alloy film of the semiconductor film and the conductor film. It becomes possible to set it to a sufficient thickness.

[Brief explanation of drawings]

FIGS. 1(a) to 1(f) are schematic cross-sectional views in order of steps for explaining an embodiment of the present invention. 1... Silicon substrate, 2... Silicon oxide film, 3.
801 layer, 4... Gate oxide film, 5... Gate polysilicon film, 5a... Highly doped gate polysilicon film, 6... Silicon nitride film, 7... Polysilicon, 8... Spacer, 9... Polysilicon film, 10... Silicon nitride film, 11... Silicon oxide film, 12... Planarizing agent, 13.13a... Titanium silicide, 14...・Source and drain diffusion layers.

Claims (1)

[Claims] 1. A method for manufacturing a MOS field effect transistor formed in a single crystal semiconductor layer on an insulating substrate, comprising: forming a gate electrode having a gate protection film made of a first insulating film on the upper surface; A second layer is formed on the side wall surface of the gate electrode.
a step of forming a spacer made of an insulating film; a step of forming a semiconductor film having a thickness thinner than that of the gate electrode on the region where the source and drain diffusion layers are to be formed; and removing the gate protective film; Depositing a conductor film over the entire surface, forming source and drain diffusion layers in the region where the source and drain diffusion layers are to be formed by ion implantation, and removing the conductor film in contact with the spacer in a self-aligned manner. A method for manufacturing a MOS field effect transistor, characterized by: 2. The method of manufacturing a MOS field effect transistor according to claim 1, wherein the first insulating film and the second insulating film are made of different materials.