JPH0321170A - Synchronizing signal separator circuit - Google Patents

Abstract

PURPOSE:To prevent a synchronizing signal from being phase shifted by turning on a switch within a synchronizing signal period and variably charging a coupling capacitor with electricity through a 1st bias means in accordance with the output potential of an inverted amplifier means. CONSTITUTION:A separated synchronizing signal is applied to a switch 14 as a control signal for turning on a switch 14 within the period of an L level and turning off the switch 14 within the period of an H level. Thereby, the capacitor 1 is charged by the capacitor corresponding to the shown voltage through 1st bias resistor 10 by turning on the switch 14 within the period of a synchronizing signal. When a composite video signal having a different APL is inputted, the value of the voltage V is changed in accordance with the difference of the APL and the charging capacity of the capacitor 1 is varied in accordance with each composite video signal. Namely, the voltage V is changed in accordance with each composite video signal, the capacitor 1 is charged in accordance with the voltage V and the DC bias of a point A is varied. Even if a composite video signal having a different APL is inputted, a separation level from the top level of a synchronizing signal is always fixed.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an improvement in a synchronization separation circuit that separates a synchronization signal from a composite video signal.

(b) Prior Art FIG. 10 shows a conventional synchronous separation circuit, which includes a coupling capacitor (1), a comparator (2),
Inverter (3) (4), p-channel MOS type FET
(5), n-channel MOS type FET (6), and bias resistors (7) and (8). Now, when a composite video signal of positive polarity is input, a synchronization signal of negative polarity is output from the comparator (2), and is output to the next stage synchronization determination circuit, etc.

By the way, this negative polarity synchronization signal is further passed through two inverters (3) and (4) to the p-channel MOS type F.
It is input to each gate of ET (5) and n-channel MOS type FET (6). Then, during the synchronization signal period, the p-channel MOS type FET (5) is turned on, and the coupling capacitor (1) is charged from the power supply VCC via the bias resistor (7). On the other hand, during a period other than the synchronization signal, the n-channel MOS FET (6) is turned on, and the coupling capacitor (1) is discharged via the bias resistor (8).

Therefore, synchronous separation is performed by making the W current bias determined by the ratio of the bias resistors (7) and (8) substantially equal to the reference potential at the minus side input terminal of the comparator (2).

(c) Problems to be Solved by the Invention However, according to the synchronous separation circuit of Jumei, the amount charged from the power supply Vcc through the bias resistor (7) during the synchronous period is constant for video signals with different APLs. becomes. Therefore, as shown in FIG. 11, the separation level varies greatly depending on video signals with different APLs. Therefore, A P L
If the separation level is changed for different video signals and this separation level is near the lower or upper end of the sync signal, a signal other than the sync signal may be undesirably output as the sync signal due to noise, burst signals, etc. Put it away.

(2) Means for Solving the Problems The present invention provides an inverting amplifying means connected to a composite video signal path via a coupling capacitor, and a first inverting amplifying means that is opened and closed according to the output signal from the inverting amplifying means. switch means and first and second switch means for charging or discharging said coupling capacitor;
comprising bias means, the input and output of the inverting amplification means are connected by a series circuit of the first switch means and the first bias means, and the connection point and the reference potential are connected by a second bias means. I decided to do so.

(E) Effect The present invention has the above-mentioned structure, so that the switch is turned on during the synchronization signal period, and the coupling capacitor is variable through the first bias means in accordance with the output potential (APL level) of the inverting amplification means. and is charged.

3. Therefore, since the amount charged in the coupling capacitor during the synchronization signal period varies depending on the APL of the composite video signal, the separation level with respect to the synchronization signal remains constant.

On the other hand, during periods other than the synchronization signal, the first switch is turned off and the coupling capacitor is discharged by the second bias means.

(F) Embodiment An embodiment of the synchronous separation circuit of the present invention will be described below with reference to the drawings.

FIG. 1 shows a principle diagram of the synchronous separation circuit of the present invention. In FIG. 1, a positive polarity composite video signal is applied to the input terminal (9) of the sync separation circuit. The synchronous separation circuit consists of a coupling capacitor (1) and a first bias resistor (10).
, second bias resistor (11), inperter (12), (
13) and a switch (14), and the input and output of the inverter (12) are connected by a series circuit of the switch (14) and the first bias resistor (10), and the connection point and the reference potential The space between is the second bias resistor (11)
connected via. Then, the composite video signal is input to the inverter (12) via the coupling capacitor (1), inverted and amplified, then inverted and amplified via the inverter (13), and then sent as a synchronization signal to the next-stage synchronization determination circuit. etc. and the switch (1
4) It is also used as a control signal.

Note that this control signal turns on the switch (14) during the synchronization signal period of the composite video signal.

Next, the operation of the synchronous separation circuit of the present invention will be explained.

Now, when a positive polarity composite video signal is input to the input terminal (9), the signal at point A becomes as shown in FIG. 3 (a), and this composite video signal is inverted and amplified by the inverter (12).
At point B, the signal becomes as shown in FIG. 3 (b). and,
This inverted and amplified composite video signal is further processed through an inverter (
13), the synchronizing signal shown in FIG. 3(C) can be separated by being inverted and amplified.

By the way, this separated synchronization signal is further used as a control signal to turn on the switch (14) during the L level period and turn off the switch (14) during the H level period.
4). Therefore, by turning on the switch (14) during the synchronization signal period (L level period), the coupling capacitor (1) generates the voltage shown in FIG. 3 (b) via the first bias resistor (10). will be charged by the amount equivalent to Here, when composite video signals with different APLs are input, the value of the voltage V varies according to the difference in APL, and the amount charged in the coupling capacitor (1) varies depending on each composite video signal. That is, each composite video signal has a different voltage (V), the coupling capacitor (1) is charged according to this voltage (V), and the DC bias at point A changes. Therefore, as shown in FIG. 4, even if composite video signals with different APLs are input, the separation level from the leading edge level of the synchronization signal is always constant.

On the other hand, during a period other than the synchronization signal (H level period), the switch (14) is turned off and the voltage charged in the coupling capacitor (1) is discharged via the second bias resistor (11).

Here, the larger the second bias resistor (11.)/first bias resistor (10), or the higher the gain of the inverter (2), the more the characteristics become -1.

Next, FIG. 2 shows a specific embodiment of the synchronous separation circuit according to the present invention.

In FIG. 2, the basic circuit structure is the same as in FIG. 1, but a comparator (14) is used as a control means for the switch (14).
5) and the insertion of a low-pass filter (16) in the output stage of the synchronized signal are added to FIG.

The operation will be explained below according to FIG. When a composite video signal of positive polarity is input, the signal at point A' becomes the signal shown in Figure 5 (a), while at point B', the composite video signal is inverted by the inverter (12), This is the symbol that indicates. By inputting the signal shown in Fig. 5 (a) to the negative terminal of the comparator (5) and the signal shown in Fig. 5 (b) to the positive terminal, the comparator (15 ), it is possible to obtain a positive synchronization signal as shown in (c). Next, after inverting and amplifying the synchronizing signal shown in FIG.
A control signal as shown in FIG. 5 (2) is obtained to turn on the 7.

Further, this control signal is further supplied to a horizontal AFC circuit, etc. via an inverter (17). And the inverter (
The signal from 12) is sent to the switch (14) during the synchronization signal period.
is turned on and the coupling capacitor (1) is charged via the first bias resistor (10), thereby providing positive feedback so that the separation level is always constant. On the other hand, during periods other than the synchronization signal, the switch (14) is turned off and the coupling capacitor (1) is discharged.

Further, the signal from the inverter (12) is transmitted to the inverter (12).
18), a capacitor (19), a resistor (20), a low-pass filter (16), and an inverter (21). In addition, inverter (12)
The low-pass filter (16) was inserted in the output stage of
This is to improve separation sensitivity in a weak electric field. That is, in general, when the electric field is weak, the synchronization signal is buried in noise, and if a synchronization signal containing this noise is input to the subsequent synchronization determination circuit, it will malfunction.

8. By inserting the low-pass filter (16) in the output stage of the inverter (12) in this way, malfunctions in weak electric fields can be prevented.

In this embodiment, the switch (22) is turned on by inputting the vertical equivalent pulse, and the second bias resistor (22) is turned on by inputting the vertical equivalent pulse.
A third bias resistor (23) is inserted in parallel with the first bias resistor (23). By doing this, the separation sensitivity during the vertical retrace period is increased.

Further, although the above-mentioned synchronization signal is a composite synchronization signal including a vertical synchronization signal, the vertical synchronization signal can be separated by further adding an integrating circuit and a rectangular synchronization separation circuit.

Next, FIG. 6 shows a synchronous separation circuit according to another embodiment of the invention.

The embodiment shown in FIG. A second synchronization separation circuit (25) that separates only the synchronization signal.The first and second synchronization separation circuits (24) and (25) each separate from the second synchronization separation circuit (25), except for the following points. The configuration is the same as that of the synchronization separation circuit shown in Figure 1. That is, the first synchronization separation circuit (24) is an OR game that receives a pseudo horizontal synchronization signal and a pseudo vertical synchronization signal} (26) and an AND gate (27) that receives the output of the OR gate (26) and the synchronization determination signal, and an inverter (28) that further inverts the output of the inverter (13).
), the output of this invert (28) and the AND gate (
A NOR gate (29) receiving the output of the switch (27) is provided, and the output of the NOR gate (29) is given to the switch (14) as a control input. The above-mentioned synchronization determination signal is a signal supplied from a synchronization determination circuit (not shown), and is at H level when synchronized, and at L level when asynchronous.

In addition, the pseudo horizontal synchronization signal and the pseudo vertical synchronization signal are generated by a voltage controlled oscillator (VCo) (30) in the horizontal AFC circuit.
The pseudo-horizontal synchronization signal is obtained by frequency-dividing the oscillation output of
The pseudo vertical synchronization signal is a signal that remains at H level for a period approximately equal to the vertical synchronization period.

FIG. 7 is a block diagram showing such a horizontal AFC circuit.

Referring to FIG. 7, the V CO (30), the low-pass filter (31), the first frequency divider (32), and the phase comparator (33) constitute an AFC loop, and the horizontal A V CO (
The oscillation output of 30) is frequency-divided by a predetermined frequency division ratio by a low-pass filter (31) and a first frequency divider (32), and is applied to one input of a phase comparator (33). On the other hand, the horizontal synchronization signal separated by the synchronization signal separation circuit (24) of iS1 in FIG. 6 is applied to the other input of the phase comparator (33), and the phases of both signals are compared.

Then, the phase comparator (33) outputs the horizontal synchronization signal and the VC
Generate an error output so that it has a predetermined phase relationship with the oscillation output of O (30) and give it to V CO (30),
Adjust the oscillation period of VCO (30). Here, the output of the first frequency divider (32) is supplied as a pseudo horizontal synchronization signal to the OR gate (26) in FIG. 6, and also to the 112-th frequency divider (34). , this second frequency divider (
34) divides the applied pseudo horizontal synchronizing signal to generate a pseudo vertical synchronizing signal, which is applied to the OR gate (26) in FIG.

Returning to the explanation of the first synchronous separation circuit (24) in FIG. 6,
The output of the inverter (13) is taken out as a composite synchronization signal containing a horizontal synchronization signal and a vertical synchronization signal, and is supplied to the horizontal AFC circuit shown in Fig. 7, and is also monitored by a resistor (35) and a capacitor (36). It is integrated by a low-pass filter (37) and supplied to the second synchronous separation circuit (25).

This second synchronous separation circuit (25) basically has the same structure as the synchronous separation circuit in FIG. 1, but is similar to the synchronous separation circuit in FIG. Bias resistance (11
') is connected in series in parallel with the second bias resistor (23
') and a switch (22') are provided. Incidentally, the opening and closing of the switch (22'') is controlled by vertical equivalent pulses as in the embodiment shown in FIG.

Here, the first synchronous separation circuit (24) in FIG. 6 includes an OR gate (26), an AND gate (27), and a NOR gate.
2 The reason for providing point (29) will be explained.

In the first and second embodiments shown in FIGS. 1 and 2,
As described above, even if the APL of the composite video signal fluctuates for each horizontal period, the synchronization signals can be normally separated.

However, since the coupling capacitor (1) is discharged during a period other than the synchronization signal period, the AP
If L changes rapidly, a composite video signal with a different APL will be input before the coupling capacitor ( ) is sufficiently discharged, and the leading level of the synchronization signal will fluctuate relative to the separation level. Accurate separation of synchronization signals becomes impossible. The first synchronous separation circuit (24) in Fig. 6
The proposed method is intended to solve this problem, and even if the APL changes rapidly, the synchronization signals can be separated accurately.

FIG. 8 is a waveform diagram for explaining the operation of the first synchronization separation circuit (24) in FIG.
A2) shows the signal waveform at the connection point A'', and FIG.
B1) and (B2) show signal waveforms at the connection point B''.

First, when the composite synchronization signal shown in FIG.
The signal shown in Figure (B1) is output and applied to the input of the inverter (13) and also to the connection point A'' via the switch (14) and the first bias resistor (10). As in the embodiment, the switch (14) is turned on during the synchronization signal period, and the coupling capacitor (1) is charged with an amount of electricity corresponding to the voltage V1 in FIG. 8 (Bl).

here,]. Considering the case where a composite video signal with an APL close to 0% suddenly changes to a composite video signal with an APL close to 0%, the next Since the horizontal period composite video signal is input to the coupling capacitor (1), connection point A
The potential at ” is as shown in Figure 8 (A2),
The separation level (single-dot chain I9) becomes lower than the lower end of the synchronization signal.

When such a signal is inverted and amplified by the inverter (13), the potential at the connection point B'' becomes as shown in FIG. 8 (B2), and the synchronizing signal is not separated.

Therefore, in the embodiment shown in FIG. By using a pseudo synchronous signal generated based on the oscillation output of the VCO (30) and a signal obtained by NOR processing the output of the inverter (28) as a control signal for the switch (14), the signal from the inverter (13) is Even if the synchronization signal is not output, the switch (14) is turned on for a period approximately equal to the original synchronization signal period.

That is, when the switch (4) is turned on by the pseudo horizontal synchronizing signal in the states shown in FIGS. 8 (A2) and (B2), an amount of charge corresponding to the voltage V2 is discharged from the coupling capacitor (1). Since the resistance value of the first bias resistor (lO) is smaller than that of the second bias resistor (1), this discharge occurs rapidly, and the relationship between the separation level and the leading edge level of the horizontal synchronization signal is normal. return to a good relationship. As a result, horizontal synchronization signals can be separated normally.

Furthermore, in one circuit (24) during the first synchronization period of the sixth example, {
Because of the doubt, the vertical synchronization signal is also connected to the output of the inverter (28).
15 16 R processed and applied to the switch (14) as control power, so for example, the AGC characteristics of Juna! A Even if the vertical synchronization signal in the composite video signal fluctuates greatly due to regular radio waves, the switch (]4) is turned on for a period approximately equal to the original vertical synchronization signal, and the coupling capacitor (1) is turned on. The relationship between the separation level and the leading edge level of the synchronization signal can be maintained constant. That is, complete synchronization separation can be performed for the vertical synchronization signal as well, as in the case of the horizontal synchronization signal described above. Then, the output of the inverter (13) is supplied as a composite synchronization signal to the horizontal AFC circuit described above, and is integrated by a low-pass filter (37) consisting of a resistor (35) and a capacitor (36) to the second synchronization separation circuit. (25).

9 is a timing chart for explaining the operation of the second synchronous separation circuit (25) in FIG. The composite synchronization signal is separated by the synchronization separation circuit (24) in FIG. At point E'', the signal becomes as shown in FIG. 9 (b). This signal is inverted and amplified by the inverter (12') and becomes a signal as shown in FIG. 9 (C) at point F'' in FIG.
3'), and at point G'' in FIG. 6, only the vertical synchronizing signal is separated as shown in FIG. 9(2) and supplied to various circuits not shown.

In addition, in the second synchronous separation circuit (25) in FIG.
Similarly to the embodiment shown in the figure, the switch (22') is turned on according to the vertical equivalent pulse period between the vertical synchronizing signals Jul, and the connection point E
” and the reference potential point. As a result, during the vertical same IUj signal period, the 9th
11i for the leading edge level of the vertical synchronization signal in Figure (b)
The 11i level is raised by 1, the influence of noise included in the tip level can be removed, and the IW sensitivity in the vertical JIJI signal period can be increased by -1.

In addition, as shown in Figures 12 and 13, the switch (1
As 4), electronic switches such as diodes (38) and transistors (3) can be used.

(g) Effects of the Invention As described in 2., according to the synchronization separation circuit of the present invention, even when composite video signals of different APLs are input, the separation level of the synchronization signal does not fluctuate and the separation is always constant. level can be obtained, and phase fluctuations of the synchronization signal can be prevented.

Additionally, by inserting a low-pass filter into the output stage of the synchronous separation circuit, malfunctions due to noise can be prevented.

[Brief explanation of drawings]

Fig. 1 is a synchronous separation circuit of the present invention, Fig. 2 is a diagram showing a specific embodiment of the synchronous separation circuit of the invention, and Fig. 3 (a) and (b).
(C) is a diagram showing the signals at points A, B, and C in Figure 1, Figure 4 is a diagram showing the effects of the present invention, and Figures 5 (A), (B), (C), and (2) are Points A′, B′, C′, and D in Figure 2
6 is a diagram showing another embodiment of the present invention, FIG. 7 is a diagram showing a horizontal AFC circuit of the present invention, and FIG. 8 is a diagram showing the signal at point A of another embodiment of the present invention. FIG. 9 is a diagram showing signals at points "Point, B", and FIG.
0 is a diagram showing a conventional synchronous separation circuit, FIG. 11 is a diagram showing that the separation level of the conventional synchronous distribution circuit changes, and FIGS. 12 and 13 are diagrams showing other embodiments of the present invention. It is a diagram.

Claims (4)

[Claims] (1) In a synchronization separation circuit that inputs a composite video signal and separates a synchronization signal, an inverting amplifying means connected to the composite video signal path via a coupling capacitor, and an output signal from the inverting amplifying means and first and second bias means for charging or discharging the coupling capacitor. What is claimed is: 1. A synchronous separation circuit, characterized in that one bias means is connected in a series circuit, and the connection point and a reference potential are connected by a second bias means. (2) The synchronous separation circuit according to claim 1, characterized in that a low-pass filter is connected to the output stage of the inverting amplification means. (3) The synchronization separation circuit according to claim 1, characterized in that a series circuit comprising a second switch means turned on during a vertical synchronization period and a third bias means is connected in parallel with the second bias means. (4) The first switch means is controlled by a pseudo horizontal synchronization signal and a pseudo vertical synchronization signal that are substantially equal to the horizontal and vertical synchronization signals, respectively, in addition to the output from the inverting amplification means. 1. The synchronous separation circuit according to 1.