JPH03218543A - Processor - Google Patents

Abstract

PURPOSE:To execute a user program at high speed and to improve execution efficiency by designating a prescribed address in a virtual storage space, reading data and altering the content of a conversion table means. CONSTITUTION:The conversion table means 4 shows the corresponding relation of the address in the real storage space including a storage means 1 which stores a micro code and which can be rewritten and address information in the virtual storage space that a setting means 2 designates. Thus, the real storage space including the storage means 1 which stores the micro code and which can be rewritten is set to be virtual. Then, a program by the micro code arranged in the virtual address space is executed. Thus, the address space viewed from a processor-side is virtually extended and the program of a large size is easily executed. Then, access with an external part is reduced and execution efficiency is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION 8. Field of Industrial Application The present invention relates to a microprogram-controlled processor having an internal rewritable storage means for storing microcode. B. Summary of the Invention The present invention provides a microprogram-controlled processor having an internal rewritable storage means for storing microcode, which includes a virtual storage space setting means and an address of the virtual storage space specified by the setting means. Conversion table means indicating a correspondence relationship between information and addresses of a real storage space including the storage means is provided, and the data can be read out by specifying a predetermined address of the virtual storage space, and the contents of the conversion table means can be changed. By doing so,
For example, the size of an executable program is not restricted by the size of real storage space, making it possible to directly execute large programs or multiple programs. C. PRIOR TECHNOLOGY In general, a microprogram control type processor has a control memory (11) for storing microcode inside the processor (10), as shown in FIG. The user program on the memory (l2) is interpreted and executed according to the microcode stored in the control memory (11). Conventionally, a control memory built into a processor is usually read-only, and a control memory in which preprogrammed microcode is written is built into the processor.

In addition, for the purpose of high-speed execution of user programs, a method is known in which a control memory built into a processor can be written to and read from the outside, and the user program is loaded directly onto the control memory and executed. D. Problems to be Solved by the Invention By the way, a microprogram control type processor can execute user programs at high speed by having a built-in control memory that can be written to and read from the outside. However, because the storage capacity of the control memory described above cannot be increased, large-scale programs cannot be directly executed.
Therefore, when executing a large-scale program or when executing multiple programs in a time-sharing manner, it is necessary to replace the program with an external device, and this replacement work significantly reduces execution efficiency. There is a problem. SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to enable high-speed execution of user programs in a microprogram-controlled processor and to improve execution efficiency. E i! Means for Solving JN In order to achieve the above-mentioned object, the present invention provides a microprogram-controlled processor having an internal rewritable storage means for storing microcode, and a virtual storage space setting means. and conversion table means indicating a correspondence relationship between address information of the virtual storage space specified by the setting means and addresses of a real storage space including the storage means, and a conversion table means for specifying a predetermined address of the virtual storage space. This device is characterized in that it is possible to read data and change the contents of the conversion table means. F. Effect In the processor according to the present invention, the correspondence relationship between the address of the real storage space including the rewritable storage means for storing the microcode and the address information of the virtual storage space specified by the setting means is indicated by the conversion table means. By this, a real storage space including a rewritable storage means for storing the above-mentioned microcode is virtualized, and a program based on the microcode placed in this virtual address space is executed. G. Embodiment Hereinafter, an embodiment of the processor according to the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, the processor according to the present invention includes a rewritable control memory (1) storing microcode.
It is a microprogram-controlled processor that has an internal microprogram control system, and uses virtual address information generated by a program counter (2), a pace register (3), a page table (4), adders (5), (6), etc. , the address of the control memory (1), that is, the physical address, is generated as described later.

In this embodiment, a collection of codes for performing a certain set of processing is called a code block, and one virtual address space is allocated to each code block. As shown in Figure 2, each code block shares the zero address and is given a sufficiently large virtual address space. The program counter (2) generates 17-bit virtual address information in order to refer to the microcode stored in the control memory (1).The virtual address information generated by the program counter (2) is , as shown in Figure 3, the virtual page number (VPN) is the virtual address space divided into 256-word page units.
The upper 9 bits [16 to 8] are assigned to the page, and the lower 8 bits are assigned to the word offset within the page. In addition, in the above virtual address space, as shown in FIG. 4, the MSB side 2 bits (16.15) are r1, I
The address space of J is used as system space, and the other address spaces are used as user space. The above-mentioned HAS register (3) also contains the physical base address (PBA) of the page table entry in the user space currently being used.
), and contains the offset value (BR) of the page table entry for the block of code currently being executed. The page table (4) is a conversion table for address conversion from a virtual address to a physical address, and the physical page number (PPN) of the control memory (1) is entered as a page table entry. This page table entry is used only for user space address translation. Note that the physical page number (PPN) is a page number of the physical address space and takes a value from 0 to 511.

In this embodiment, as shown in FIG. 5, the address of the page table (4) is the address of the program counter (
The offset value (BR) of the page table entry given by the pace register (3) is added by the adder (5) to the virtual page number [vPN] given by the MSB side 9 bits of the virtual address information generated by 2). It is indicated by the value (BR+VPN). Then, the adder (5
) The above address value (BR
The page table entry stored in the storage location of the page table (4) specified by +VPN), that is, the physical page number [PPN] of the control memory (1), is read, and the above is set to this physical page number (PPN). A physical address is formed by adding a word offset indicated by the LSB side 8 bits of the virtual address information generated by the program counter (2) using an adder (6). Note that a page table entry with a physical page number (PPN) of zero means that the corresponding virtual address space is not mapped to a physical page, and if an attempt is made to access that area, a page fault will occur and the external The necessary code blocks are loaded from the backup memory (8) to the control memory (1). Further, the control memory (1) and the page table (4) are both memories whose data can be rewritten from the outside.
Processors use interrupts, etc. to notify external parties of their operating status. In the processor of this embodiment, the address space of the control memory (1) is virtualized through the above processing, and the microcode in which the desired user program is written is virtually stored and executed. In this processor, the address space seen from the processor side is virtually expanded, making it possible to easily execute large programs that were difficult to execute with conventional microprogram-controlled processors. Furthermore, by virtualizing the address space of the control memory (1), programs can be arbitrarily located without being restricted by physical addresses. Therefore, when multiple programs are executed in a time-sharing manner, by storing these programs in virtual memory, programs can be switched without external access, improving execution efficiency. do. Note that if one virtual space is given to the entire code section whose content, size, and number change dynamically, the virtual address space that was continuous at a certain time will be changed after ΔL time. This discontinuity complicates the management of the virtual address space, and the page table for managing the virtual address space becomes large, resulting in poor utilization efficiency of the virtual address space. The above-mentioned problems can be avoided by allocating virtual address space in units of code blocks, as in H. Effects of the Invention As described above, in the processor according to the present invention, by virtualizing the address space of the control memory, the address space seen from the processor side is virtually expanded, so that the conventional microprogram control method cannot be used. This makes it possible to easily execute large programs that would be difficult to execute on other processors.

Also, since the program is placed in a virtual address space, there is a degree of freedom in its allocation. Therefore, without being constrained by physical addresses,
In an environment where various programs are executed in a time-sharing manner, it is possible to switch between programs. This makes it possible to reduce external access and improve execution efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main part configuration of a processor according to the present invention, FIG. 2 is a diagram showing the contents of the virtual address space in the processor, and FIG. 3 is a diagram showing virtual address information generated by the program counter in the processor. Figure 4 is a diagram showing the contents, and Figure 4 is a diagram showing the correspondence between the virtual address space and physical address space in the above processor.
The figure is a diagram used to explain the address conversion process between virtual addresses and physical addresses in the above processor. 6th
The figure is a block diagram showing the basic configuration of a conventional processor. (1)......Control memory (2)...
・・・・・・Program counter (3)・・・・・・
...Pace register (4)...Page table (5), (6)...Adder special
Applicant: Sony Corporation

Claims (1)

[Scope of Claims] A microprogram-controlled processor having an internal rewritable storage means for storing microcode, comprising a virtual memory space setting means and an address of the virtual memory space specified by the setting means. It has a conversion table means that shows the correspondence between information and addresses of a real storage space including the storage means, and it is possible to read data by specifying a predetermined address in the virtual storage space and change the contents of the conversion table means. A processor characterized by: