JPH03203377A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03203377A JPH03203377A JP34284989A JP34284989A JPH03203377A JP H03203377 A JPH03203377 A JP H03203377A JP 34284989 A JP34284989 A JP 34284989A JP 34284989 A JP34284989 A JP 34284989A JP H03203377 A JPH03203377 A JP H03203377A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- diffusion layer
- well
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000009792 diffusion process Methods 0.000 claims abstract description 42
- 230000015556 catabolic process Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 73
- 239000012535 impurity Substances 0.000 abstract description 16
- 239000011229 interlayer Substances 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に高耐圧型ＭＯＳトラン
ジスタを有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a high voltage MOS transistor.
従来の半導体装置は、第２図に示すように、Ｎ型シリコ
ン基板１の上にＮ−型エピタキシャル層３を成長し、Ｎ
−型エピタキシャル層３の表面にＰ型不純物を選択的に
イオン注入して熱拡散し、Ｐ型ウェル５を形成する。次
に、Ｐ型ウェル５の外周に接して環状のＰ型拡散層６を
形成し、Ｐ型拡散層６の表面を選択酸化してフィールド
酸化膜７を形成する。次に、フィールド酸化膜７の外周
に設けたゲート酸化膜を介してゲート電極８を選択的に
設け、フィールド酸化膜７及びゲート電極８をマスクと
してＮ型不純物をイオン注入し、熱拡散してＮ型拡散層
１０を形成する。次に、フィールド酸化膜７及びゲート
電極８に整合してＰ型不純物をイオン注入し、Ｐ型ウェ
ル５の表面にＰ“型拡散層１１を形成し、同時にＮ型拡
散層１０の表面に選択的にＰ＋型拡散層１２を形成する
。次に、ゲート電極８を含む表面に層間絶縁膜１３を堆
積してコンタクト用開口部を選択的に設け、コンタクト
用開口部を含む表面にアルミニウム層を堆積して選択的
にエツチングし、Ｐ“型拡散層１１と接続するトレイン
電極１４と、Ｐ′″型拡散拡散層１２Ｎ１型拡散層４と
接続するソース電極１５を設けて高耐圧のオフセットゲ
ート型ＰチャネルＭＯ３ＦＥＴを構成する。In the conventional semiconductor device, as shown in FIG. 2, an N-type epitaxial layer 3 is grown on an N-type silicon substrate 1.
A P-type impurity is selectively ion-implanted into the surface of the −-type epitaxial layer 3 and thermally diffused to form a P-type well 5 . Next, an annular P-type diffusion layer 6 is formed in contact with the outer periphery of the P-type well 5, and a field oxide film 7 is formed by selectively oxidizing the surface of the P-type diffusion layer 6. Next, a gate electrode 8 is selectively provided through a gate oxide film provided on the outer periphery of the field oxide film 7, and N-type impurities are ion-implanted using the field oxide film 7 and gate electrode 8 as masks, and then thermally diffused. An N-type diffusion layer 10 is formed. Next, P-type impurity ions are implanted in alignment with the field oxide film 7 and the gate electrode 8 to form a P"-type diffusion layer 11 on the surface of the P-type well 5, and at the same time selectively implant the P"-type impurity on the surface of the N-type diffusion layer 10. Next, an interlayer insulating film 13 is deposited on the surface including the gate electrode 8 to selectively form contact openings, and an aluminum layer is formed on the surface including the contact openings. By depositing and selectively etching, a train electrode 14 connected to the P" type diffusion layer 11 and a source electrode 15 connected to the P'' type diffusion layer 12 and the N1 type diffusion layer 4 are provided to form a high breakdown voltage offset gate type. Configure a P-channel MO3FET.
ここで、ソース電極１５とドレイン電極１４との間に逆
バイアスを印加した場合、高耐圧ＭＯ９ＦＥＴのＰＮ接
合のうち電界集中のため最も耐圧の低い一部分（例えば
Ｐ型ウェル５やＰ型拡散層６の端部の丸みを帯びた部分
）で降伏現象が生じ耐圧が決定されていた。Here, when a reverse bias is applied between the source electrode 15 and the drain electrode 14, the portion of the PN junction of the high voltage MO9FET with the lowest voltage due to concentration of the electric field (for example, the P-type well 5 or the P-type diffusion layer 6) A yielding phenomenon occurred at the rounded end of the steel, and the withstand voltage was determined.
上述した従来の半導体装置は、−導電型のエピタキシャ
ル層と、逆導電型のウェル及び拡散層との間に形成され
るＰＮ接合に逆バイアスが印加された場合に、このＰＮ
接合の端部の丸みを有する部分に電界集中を生じて降伏
現象を生じ、流れる過電流か一部分に集中して、その部
分のＰＮ接合が熱的破壊を起こすという問題点がある。In the conventional semiconductor device described above, when a reverse bias is applied to the PN junction formed between the − conductivity type epitaxial layer and the opposite conductivity type well and diffusion layer, this PN
There is a problem in that an electric field is concentrated in the rounded end of the junction, causing a breakdown phenomenon, and the flowing overcurrent is concentrated in one part, causing thermal breakdown of the PN junction in that part.
〔課題を解決するための手段〕
本発明の半導体装置は、−導電型半導体基板の一主面に
設けた高濃度の一導電型の埋込層と、前記埋込層を含む
表面に設けた低濃度一導電型のエピタキシャル層と、前
記エピタキシャル層に設けて前記埋込層と接続し素子形
成領域を区域する一導電型の第１の拡散層と、前記素子
形成領域に設けた環状の逆導電型のウェルと、前記ウェ
ルの内側に設けて降伏現象発生時に過電流を流す一導電
型の第２の拡散層と、前記ウェルの内側の前記第２の拡
散層よりも浅く設けて前記ウェルと接続した逆導電型の
第３の拡散層とを有する。[Means for Solving the Problems] A semiconductor device of the present invention includes a buried layer of a high concentration of one conductivity type provided on one main surface of a semiconductor substrate of a conductivity type, and a buried layer of one conductivity type provided on a surface including the buried layer. a low concentration epitaxial layer of one conductivity type; a first diffusion layer of one conductivity type provided in the epitaxial layer and connected to the buried layer to define an element formation region; and a first diffusion layer of one conductivity type provided in the element formation region; a well of a conductivity type; a second diffusion layer of one conductivity type that is provided inside the well and causes an overcurrent to flow when a breakdown phenomenon occurs; and a second diffusion layer that is provided shallower than the second diffusion layer inside the well and that and a third diffusion layer of an opposite conductivity type connected to the third diffusion layer.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を説明するための半導体チッ
プの模式的断面図である。FIG. 1 is a schematic cross-sectional view of a semiconductor chip for explaining one embodiment of the present invention.
Ｎ型シリコン基板１の一主面にＮ型不純物を選択的にイ
オン注入して熱拡散し、Ｎ＋＋埋込層２を設け、Ｎ２型
埋込層２を含む表面にＮ−型エピタキシャル層３を成長
させる１次に、Ｎ−型エピタキシャル層３の表面にＮ型
不純物を選択的にイオン注入して熱拡散し、Ｎ“型埋込
層２に達する環状のＮ＋型型数散層４形成して素子形成
領域を区画する。次に、素子形成領域の表面にＰ型不純
物を選択的にイオン注入して熱拡散し、環状のＰ型ウェ
ル５を設ける。次に、Ｐ型ウェル５の外周に接して環状
のＰ型拡散層６を形成し、Ｐ型拡散層６の表面を選択酸
化してフィールド酸化膜７を形成する。次に、フィール
ド酸化膜７の外周に設けたゲート酸化１１１Ｉ８を介し
てゲート電極８を選択的に設ける。次に、フィールド酸
化膜７及びゲート電極８をマスクとしてＮ型不順物をイ
オン注入し、Ｐ型ウェル５の内側及びゲート電極８の外
周のＮ−型エピタキシャル層３にＮ型不純物をＰ型ウェ
ル５よりも浅くイオン注入してＮ型拡散層９及びＮ型拡
散層１０をそれぞれ設ける。次に、同様にフィールド酸
化膜７及びゲート電極８をマスクどしてＰ型不純物をイ
オン注入しＮ型拡散層９．１０よりも浅いＰ型拡散層１
１．１２を夫々設ける。次に、ゲート電極８を含む表面
に眉間絶縁膜１３を堆積して選択的にコンタクト用開口
部を設け、コンタト用開口部を含む表面にアルミニウム
層等の金属層を設けて選択的にエツチングし、Ｐ″″型
拡散拡散層１１続するドレイン電極１４と、Ｐ＋型拡散
層１２及びＮ＋型型数散層４接続するソース電極１５を
設けて高耐圧のオフセットゲート型ＰチャネルＭＯ３Ｆ
ＥＴを構成する。N-type impurities are selectively ion-implanted into one main surface of the N-type silicon substrate 1 and thermally diffused to form an N++ buried layer 2, and an N- type epitaxial layer 3 is formed on the surface including the N2-type buried layer 2. First, N-type impurities are selectively ion-implanted into the surface of the N-type epitaxial layer 3 and thermally diffused to form an annular N+-type scattered layer 4 that reaches the N"-type buried layer 2. Next, a P-type impurity is selectively ion-implanted into the surface of the element-forming region and thermally diffused to form an annular P-type well 5.Next, the outer periphery of the P-type well 5 is An annular P-type diffusion layer 6 is formed in contact with the P-type diffusion layer 6, and the surface of the P-type diffusion layer 6 is selectively oxidized to form a field oxide film 7. Next, a gate oxide 111I8 provided on the outer periphery of the field oxide film 7 is formed. Then, using the field oxide film 7 and the gate electrode 8 as a mask, N-type impurities are ion-implanted to form an N-type impurity inside the P-type well 5 and on the outer periphery of the gate electrode 8. N-type impurities are ion-implanted into the epitaxial layer 3 to a depth shallower than that of the P-type well 5 to form an N-type diffusion layer 9 and an N-type diffusion layer 10, respectively.Next, the field oxide film 7 and gate electrode 8 are formed using a mask in the same manner. P-type impurity is ion-implanted to form a P-type diffusion layer 1 shallower than the N-type diffusion layer 9.10.
1.12 are provided respectively. Next, a glabellar insulating film 13 is deposited on the surface including the gate electrode 8 to selectively provide contact openings, and a metal layer such as an aluminum layer is provided on the surface including the contact openings and selectively etched. , a drain electrode 14 connected to the P'''' type diffusion layer 11, and a source electrode 15 connected to the P+ type diffusion layer 12 and the N+ type scattered layer 4 are provided to form a high breakdown voltage offset gate type P channel MO3F.
Configure ET.
ここで、Ｎ−型エピタキシャル層３はＮ＋＋埋込層２及
びＮ＋型型数散層４介してソース電位が印加される。ま
た、Ｐ＋型拡散層とＮ型拡散層９のＰＮ接合面１６の降
伏電圧を他の部分の耐圧より低くなるようにＮ型拡散層
９の不純物濃度を設定する。Here, a source potential is applied to the N- type epitaxial layer 3 via the N++ buried layer 2 and the N+ type scattering layer 4. Further, the impurity concentration of the N type diffusion layer 9 is set so that the breakdown voltage of the PN junction surface 16 between the P+ type diffusion layer and the N type diffusion layer 9 is lower than the breakdown voltage of other parts.
このようにしてソース電極１５とドレイン電極１４に逆
バイアスを印加すると、前記ＰＮ接合面１６で均一な降
伏現象が生じ、この時流れる過電流はＮ“型拡散層４及
びＮ”型埋込層２を通ってＰＮｔ１合面１６の全平面を
流れ、均一な降伏現象を生ずる。When a reverse bias is applied to the source electrode 15 and the drain electrode 14 in this way, a uniform breakdown phenomenon occurs at the PN junction surface 16, and the overcurrent flowing at this time is transferred to the N" type diffusion layer 4 and the N" type buried layer. 2 through the entire plane of the PNt1 interface 16, resulting in a uniform breakdown phenomenon.
以上説明したように本発明は、−導電型エピタキシャル
層に設けた環状の逆導電型のウェルの内側に低い降伏電
圧を有する均一なＰＮ平面接合を設けて低い電圧で降伏
現象を生じさせ、過電流をそのＰＮ平面接合の全面を通
して流すことにより、高耐圧ＭＯＳＦＥＴのＰＮ接合の
一部分に集中して流れる過電流によって生じるＰＮ接合
の熱的破壊を防止することができるという効果がある。As explained above, the present invention provides a uniform PN plane junction having a low breakdown voltage inside an annular opposite conductivity type well provided in a -conductivity type epitaxial layer to cause a breakdown phenomenon at a low voltage. By flowing a current through the entire surface of the PN plane junction, it is possible to prevent thermal breakdown of the PN junction caused by an overcurrent flowing concentratedly in a part of the PN junction of the high voltage MOSFET.
また、外部からのホールの注入も高濃度のＮ型不純物層
に吸収されるため、ラッチアップ耐量の向上につながる
。In addition, holes injected from the outside are also absorbed by the highly concentrated N-type impurity layer, leading to an improvement in latch-up resistance.
１・・・Ｎ型シリコン基板、２・・・Ｎ１型埋込層、３
・・・Ｎ−型エピタキシャル層、４・・・Ｎ＋型型数散
層５・・・Ｐ型ウェル、６・・・Ｐ型拡散層、７・・・
フィールド酸化膜、８・・・ゲート電極、９，１０・・
・Ｎ型拡散層、１１．１２・・・Ｐ′″型拡散拡散層３
・・・層間絶縁膜、１４・・・ドレイン電極、１５・・
・ソース電極、１６・・・ＰＮ接合面。1... N type silicon substrate, 2... N1 type buried layer, 3
...N- type epitaxial layer, 4...N+ type scattering layer 5...P type well, 6...P type diffusion layer, 7...
Field oxide film, 8... Gate electrode, 9, 10...
・N type diffusion layer, 11.12...P''' type diffusion layer 3
...Interlayer insulating film, 14...Drain electrode, 15...
- Source electrode, 16...PN junction surface.
Claims (1)
型の埋込層と、前記埋込層を含む表面に設けた低濃度一
導電型のエピタキシャル層と、前記エピタキシャル層に
設けて前記埋込層と接続し素子形成領域を区域する一導
電型の第１の拡散層と、前記素子形成領域に設けた環状
の逆導電型のウェルと、前記ウェルの内側に設けて降伏
現象発生時に過電流を流す一導電型の第２の拡散層と、
前記ウェルの内側の前記第２の拡散層よりも浅く設けて
前記ウェルと接続した逆導電型の第３の拡散層とを有す
ること特徴とする半導体装置。A buried layer of one conductivity type with high concentration provided on one main surface of the semiconductor substrate of one conductivity type, an epitaxial layer of one conductivity type with low concentration provided on the surface including the buried layer, and an epitaxial layer of one conductivity type with low concentration provided on the surface including the buried layer; a first diffusion layer of one conductivity type connected to the buried layer and defining an element formation region; a ring-shaped well of an opposite conductivity type provided in the element formation region; and a first diffusion layer provided inside the well to cause a breakdown phenomenon. a second diffusion layer of one conductivity type that sometimes causes an overcurrent to flow;
A semiconductor device comprising: a third diffusion layer of an opposite conductivity type provided inside the well, shallower than the second diffusion layer, and connected to the well.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34284989A JPH03203377A (en) | 1989-12-29 | 1989-12-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34284989A JPH03203377A (en) | 1989-12-29 | 1989-12-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03203377A true JPH03203377A (en) | 1991-09-05 |
Family
ID=18356971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34284989A Pending JPH03203377A (en) | 1989-12-29 | 1989-12-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03203377A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5374569A (en) * | 1992-09-21 | 1994-12-20 | Siliconix Incorporated | Method for forming a BiCDMOS |
| US5541123A (en) * | 1992-09-21 | 1996-07-30 | Siliconix Incorporated | Method for forming a bipolar transistor having selected breakdown voltage |
| US5643820A (en) * | 1992-09-21 | 1997-07-01 | Siliconix Incorporated | Method for fabricating an MOS capacitor using zener diode region |
| WO1998011609A1 (en) * | 1996-09-10 | 1998-03-19 | Spectrian, Inc. | Lateral dmos transistor for rf/mircrowave applications |
| US5869875A (en) * | 1997-06-10 | 1999-02-09 | Spectrian | Lateral diffused MOS transistor with trench source contact |
| JP2006041533A (en) * | 2004-07-27 | 2006-02-09 | Robert Bosch Gmbh | High voltage MOS transistor and corresponding manufacturing method |
| US9722041B2 (en) | 2012-09-19 | 2017-08-01 | Vishay-Siliconix | Breakdown voltage blocking device |
-
1989
- 1989-12-29 JP JP34284989A patent/JPH03203377A/en active Pending
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5643820A (en) * | 1992-09-21 | 1997-07-01 | Siliconix Incorporated | Method for fabricating an MOS capacitor using zener diode region |
| US5416039A (en) * | 1992-09-21 | 1995-05-16 | Siliconix Incorporated | Method of making BiCDMOS structures |
| US5422508A (en) * | 1992-09-21 | 1995-06-06 | Siliconix Incorporated | BiCDMOS structure |
| US5426328A (en) * | 1992-09-21 | 1995-06-20 | Siliconix Incorporated | BICDMOS structures |
| US5541123A (en) * | 1992-09-21 | 1996-07-30 | Siliconix Incorporated | Method for forming a bipolar transistor having selected breakdown voltage |
| US5541125A (en) * | 1992-09-21 | 1996-07-30 | Siliconix Incorporated | Method for forming a lateral MOS transistor having lightly doped drain formed along with other transistors in the same substrate |
| US5547880A (en) * | 1992-09-21 | 1996-08-20 | Siliconix Incorporated | Method for forming a zener diode region and an isolation region |
| US5559044A (en) * | 1992-09-21 | 1996-09-24 | Siliconix Incorporated | BiCDMOS process technology |
| US5618743A (en) * | 1992-09-21 | 1997-04-08 | Siliconix Incorporated | MOS transistor having adjusted threshold voltage formed along with other transistors |
| US5583061A (en) * | 1992-09-21 | 1996-12-10 | Siliconix Incorporated | PMOS transistors with different breakdown voltages formed in the same substrate |
| JP2007335881A (en) * | 1992-09-21 | 2007-12-27 | Siliconix Inc | BiCDMOS structure and manufacturing method thereof |
| US5648281A (en) * | 1992-09-21 | 1997-07-15 | Siliconix Incorporated | Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate |
| US5374569A (en) * | 1992-09-21 | 1994-12-20 | Siliconix Incorporated | Method for forming a BiCDMOS |
| US5751054A (en) * | 1992-09-21 | 1998-05-12 | Siliconix Incorporated | Zener diodes on the same wafer with BiCDMOS structures |
| EP1119043A3 (en) * | 1992-09-21 | 2005-07-13 | SILICONIX Incorporated | BiCDMOS process technology and structures |
| US5821144A (en) * | 1996-09-10 | 1998-10-13 | Spectrian, Inc. | Lateral DMOS transistor for RF/microwave applications |
| WO1998011609A1 (en) * | 1996-09-10 | 1998-03-19 | Spectrian, Inc. | Lateral dmos transistor for rf/mircrowave applications |
| US5869875A (en) * | 1997-06-10 | 1999-02-09 | Spectrian | Lateral diffused MOS transistor with trench source contact |
| JP2006041533A (en) * | 2004-07-27 | 2006-02-09 | Robert Bosch Gmbh | High voltage MOS transistor and corresponding manufacturing method |
| US9722041B2 (en) | 2012-09-19 | 2017-08-01 | Vishay-Siliconix | Breakdown voltage blocking device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5248627A (en) | Threshold adjustment in fabricating vertical dmos devices | |
| JPS6359545B2 (en) | ||
| JPH0354855A (en) | Hybrid technique integrated circuit including high early voltage cmos structure and effective lateral bipolar transistor and manufacturing method of the same | |
| JP3448546B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH11251597A (en) | Semiconductor device | |
| JPH03203377A (en) | Semiconductor device | |
| JPH09129868A (en) | Semiconductor device and its manufacture | |
| JPH0237777A (en) | vertical field effect transistor | |
| JP2002170952A (en) | Field MOS transistor and semiconductor integrated circuit including the same | |
| JP3997886B2 (en) | Method for manufacturing silicon carbide semiconductor device | |
| US6878998B1 (en) | Semiconductor device with region that changes depth across the direction of current flow | |
| JP2000174218A (en) | Semiconductor device and manufacturing method thereof | |
| WO2006082618A1 (en) | Semiconductor device and method for manufacturing the same | |
| JP2508218B2 (en) | Complementary MIS integrated circuit | |
| JPH0955496A (en) | High voltage MOS transistor and method of manufacturing the same | |
| JPS62181458A (en) | Complementary type mos transistor and manufacture thereof | |
| JP2816985B2 (en) | Vertical MOS field-effect transistor | |
| JP3223125B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| JP2953061B2 (en) | High breakdown voltage MOS transistor and method of manufacturing the same | |
| JPH1065154A (en) | Semiconductor device and manufacturing method thereof | |
| JPH03120836A (en) | Semiconductor device | |
| JPS62219555A (en) | Bipolar mos semiconductor device | |
| JPH05129535A (en) | Semiconductor integrated circuit and manufacture thereof | |
| JP2689719B2 (en) | Semiconductor device | |
| JPH04113669A (en) | Semiconductor device |