JPH03203350A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (b) Industrial application field The present invention relates to a method for manufacturing a semiconductor device.

In particular, the present invention relates to a method for forming element isolation regions of submicron devices.

(b) Conventional technology Conventionally, element isolation regions have been formed by the LOCOS method, or it has been difficult to reduce the width of the element isolation regions to 1 μm or less to prevent bird's beak (bird's beak-shaped insulation regions) from forming. Have difficulty.

Recently, after forming a trench on the surface of a silicon semiconductor, C
There is a box method in which an oxide film is embedded using the VD method.

(c) Problems to be Solved by the Invention With the conventional box method, as the density of wiring patterns increases, trench miniaturization and an increase in aspect ratio (depth/opening width) are required. There is a drawback that it is difficult to bury the embedding material in the trench with good uniformity.

The present invention has been made to solve the above-mentioned drawbacks, and it is possible to simultaneously fill the inside of a trench formed with a cross-sectional shape with a small opening width and a large aspect ratio, and the inside of a small trench with a wide opening width and a small aspect ratio. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a embedding material can be buried so as to have a flat surface with good uniformity.

(D) Means for Solving the Problems According to the present invention, in a substrate having a plurality of trenches formed with openings having a small width and a cross-sectional shape having a large aspect ratio, a) at least the inside of the trenches is buried; A glass layer with good meltability is laminated as shown in FIG.
A method of manufacturing a semiconductor device is provided, which comprises repeating each step of c) one or more times to fill the trench.

The substrate used in the method of the present invention is, for example, a silicon substrate in which a trench having a cross-sectional shape with a small width opening and a large aspect ratio is formed. A trench with a small width opening and a large aspect ratio cross section is
It is used to form a fine element isolation region. Its dimensions are not particularly limited. As for its specific dimensions, for example, the width of the opening is 05 to 2.04 ua, and the aspect ratio is 0.
Examples are 5 to 3. The pattern of the trench on the substrate is not particularly limited.

For a substrate having such a trench, the glass layer embedded in the trench is preferably formed of a glass with good melting properties that flows sufficiently during the high-temperature annealing process, such as boron phosphorus silicate glass. (BPSG), boron silicate glass (BSG), phosphorus silicate glass (PSG)
can be mentioned. The glass layers may be laminated by embedding the glass in the trench, and usually the glass layer is also formed on the silicon substrate outside the trench. This method can be carried out by laminating a glass layer on a substrate by, for example, a CVD method, a sputtering method, or the like. When the glass layers are laminated, for example, as shown in FIG.
There is a tendency for unevenness to occur on the surface.

In this invention method, a high temperature annealing treatment is then performed. This high temperature annealing treatment is usually 700°C to 12°C.
It can be carried out at 00°C. This temperature is preferably selected appropriately depending on the properties of the glass layer used. By this high-temperature annealing treatment, the glass layer 2a as shown in FIG. 1(a), for example, is changed to a glass layer 2 whose surface is flattened by filling the gaps in the trench, as shown in FIG. 1(b).
It becomes b.

Next, in the method of the present invention, a dry or wet etching process is performed to remove the glass layer on the substrate. An example of the dry etching process is reactive ion etching (RIE). As a wet etching process, for example, buffered hydrofluoric acid (B
This can be carried out using an etching solution made of diluted hydrofluoric acid such as HF). This etching process is continued until the surface of the substrate outside the trench is exposed. On this occasion,
A portion of the glass layer within the trench may also be removed.

In the present invention, each of the above steps is further repeated one or more times until the glass is buried in the trench and the substrate surface is flattened. This repetition may be performed once, but may be repeated two or more times as necessary.

The thus obtained substrate has a fine element isolation region.

Such a substrate can be formed into a final product by forming desired elements according to conventional methods.

(E) Effect According to the present invention, by laminating a glass layer that exhibits good meltability in annealing treatment on a substrate having a trench, and repeating annealing treatment and etching treatment, it is possible to easily form a glass layer regardless of the opening width of the trench. It is possible to easily form a fine element isolation region.

(f) Example Embodiments of the invention will be described with reference to the drawings.

Example 1 First, a silicon substrate 1 with a depth of 1.0 μm and a width of 0.5 μm
A trench having a cross-sectional shape with an aspect ratio of 2.0 is formed, and a first BPSG (boron phosphorus silicate glass) layer 2 is formed in the trench by CVD (FIG. 1(a)).

Next, smoothing is performed by high temperature annealing treatment at 1000°C. The smaller the aspect ratio, the larger the buried volume in the trench, and as a result, the thickness of the BPSG layer 2b becomes thinner (
Figure 1(b)).

Next, the first BPSG layer 2b is etched with a wet etching solution (
Etch the silicon substrate using buffered hydrofluoric acid (BHF) until the surface of the silicon substrate is exposed.

As a result, the thickness of the BPSG layer 2C in the trench is 0.8μ
m (Figure 1 (C)).

Next, as shown in FIGS. 1(d) to 1(f), the deposition of the second BPSG layers 3a, 3b, high temperature annealing and etching steps are repeated once to obtain a uniformly flat surface within the trench. A buried layer of BPSG is formed to form an element isolation region 4, and a semiconductor device is manufactured.

Example 2 First, a silicon substrate 11 with a depth of 1.0 μm and a width of 2.0 μm
A trench having a cross-sectional shape with an m1 aspect ratio of 0.5 is formed, and the first BPSGl 12a is deposited in the trench by the CVD method (FIG. 2(a)).

Next, smoothing is performed by high temperature annealing treatment at 1000°C. As a result, the first BPSGI 112bll becomes thinner (FIG. 2(b)).

Next, the first BPSG 112b is etched using a wet etching solution (buffered hydrofluoric acid (BHF)) until the surface of the silicon substrate is exposed.

As a result, the film thickness of BPSGIl12c in the trench is 0.
．． 4μ- (Fig. 2(C)).

Next, as shown in FIG. 2(d) to (f), the second BPS
The formation, heating, and etching steps of the G layers 13a and 13b are performed in 2 steps.
By repeating this process several times, the buried layer of BPSG buried in the trench is shaped so as to have a uniformly flat surface, an element isolation region 14 is formed, and a semiconductor device is manufactured.

(G) Effects of the Invention According to this invention, a flat surface with good uniformity can be obtained simultaneously in a trench having a cross-sectional shape with minute dimensions and a large aspect ratio, and in a trench with a wide opening width and a small aspect ratio. Thus, it is possible to provide a method for manufacturing a semiconductor device in which an element isolation region with minute dimensions can be formed by embedding a embedding material. By using the method of the present invention, a semiconductor device having a high-density wiring pattern can be manufactured regardless of the trench opening width and the wiring pattern density.

[Brief explanation of drawings]

FIGS. 1 and 2 are explanatory views of the manufacturing process of a semiconductor device manufactured in an example of the present invention. 1.11... Silicon substrate, 2 a, 2 b, 2 c, 12 a 12 b...
...First BPSG layer, 3a, 3b, 3c, 13a, l 3b...Second
BPSG layer, 4, Step 4... Element isolation region. Figure 1 (a) Figure (b)

Claims (1)

[Claims] 1. On a substrate having a plurality of trenches formed in a cross-sectional shape with a small width opening and a large aspect ratio, a) a glass layer with good meltability is laminated so that at least the inside of the trench is buried, and b) High-temperature annealing treatment, then c) dry or wet etching treatment to remove the glass layer on the substrate, and repeating each step of a), b), and c) one or more times to remove the inside of the trench. A method of manufacturing a semiconductor device comprising burying the device.