JPH03201882A - Video display circuit - Google Patents

Abstract

PURPOSE:To attain stable and easy to see display of a video signal from a storage element and convenience of use by generating an internal synchronizing signal based on a readout clock when no external video signal is inputted, supplying the generated synchronizing signal to a monitor, reading a video signal from the storage element and supplying the signal to the monitor. CONSTITUTION:A detection circuit 21 detects the presence of an external video signal fed externally. In the absence of the external video signal, an internal synchronizing signal is generated based on a readout clock generated by clock generating means 6A, 7, 8 and fed to a monitor, and a video signal is read from a storage element 9 and the only the read video signal is fed to the monitor, Where the signal is displayed. That is, the external video signal is deleted and only the video signal from the storage element 9 is displayed as if it is a character written on a blackboard.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention reads a video signal from a storage element based on a synchronization signal of an external video signal supplied from the outside, superimposes it on the external video signal, and outputs the superimposed signal. The present invention relates to a video display circuit.

[Summary of the Invention] The present invention provides a video display circuit that reads a video signal from a storage element based on a synchronization signal of an external video signal supplied from the outside, superimposes it on the external video signal, and outputs the superimposed image signal. a detection circuit that detects the presence or absence of the
It is equipped with a clock generating means for forming a read clock for reading a video signal from the storage element, and a switching circuit that selectively supplies the external video signal and the video signal from the storage element to the monitor, and the detection circuit detects the external video signal. When it is detected that there is no human input, a synchronizing signal is internally generated based on the readout clock generated by the clock generation means and supplied to the monitor, and the image is output from the storage element based on the readout clock. By reading the signal and controlling the switching circuit based on the output signal of the detection circuit so that only the read video signal is supplied to the monitor, noise caused by selecting a non-broadcasting channel or at the end of a broadcast can be avoided. This reduces discomfort and makes it possible to stably display the video signal from the memory element and make it easier to use.

(Prior Art) A conventional video display circuit as shown in FIG. In the figure, (1) is an input terminal to which a video signal is supplied from the outside, and the video signal from this input terminal (1) is supplied to a synchronization separation circuit (2). Here, a composite synchronization signal including a horizontal synchronization signal and a vertical synchronization signal is synchronously separated.This synchronously separated composite synchronous signal is supplied to a horizontal synchronization separation circuit (3) and a frame head detection circuit (4). The composite synchronization signal obtained at the synchronization output terminal (5) is supplied to a monitor (not shown).

A horizontal synchronization signal is extracted from the composite synchronization signal by a horizontal synchronization separation circuit (3), and is supplied to a clock generation PLL circuit (6) from a phase comparator, low-pass filter (LPF), dot clock oscillator, etc. (not shown). be done. The PLL circuit (6) generates a dot clock (readout clock) synchronized with the human input video signal based on the supplied horizontal synchronization signal.
will occur. This dot clock is a dot counter (7
), and each time this dot counter (7) counts one line worth of dot clocks, the line counter (
8) is incremented. Line counter (8) is 1
The number of scanning lines is equal to one frame, and it returns to the original number every time the lines of one frame are counted. However, in order to synchronize with the human video signal, a frame start detection circuit (4
) is reset by the frame start detection pulse detected from the vertical synchronization signal. The output of the dot counter (7) is used as a horizontal address signal, and the output of the line counter (8) is used as a vertical address signal for a video RAM (hereinafter referred to as VRAM) (
9) and its contents are read out.

The video signal from this VRAM (9) and the input terminal (
By switching the external video signal from 1) at high speed using a high-speed switch circuit (lO), the external video signal has νRA? I(
9) is superimposed, taken out to the video output terminal (11), and supplied to the monitor.

Here, the compound synchronization signal separated in synchronization by the synchronization separation circuit (2) is directly used as the synchronization output, because when a source with loose synchronization jitter such as a VTR is input, the output of the dot counter (7) is used. For horizontal synchronization, the PLL circuit (
This is because the tracking performance deteriorates due to the LPF in 6).

[Problem to be solved by the invention]

By the way, in the case of the conventional circuit with the configuration shown in Figure 4, the external video signal from the input terminal (1) is directly displayed on the monitor, so if, for example, a non-broadcast channel is selected with the tuner, noise may appear on the screen. It was very difficult to see, and the audio output was difficult to hear due to the noise.

Also, even if the video signals such as characters and figures from the VRAM (9) were superimposed on the external video signal (main screen signal) from the input terminal (1), there was noise on the main screen. In addition to the unpleasant blur, the synchronization of the VRAM (9) video signal for superimposing also became unstable, causing the image to flow on the monitor.

This invention has been made in view of the above points, and includes a detection circuit for external video signals, and constantly monitors the external video signals to determine whether or not a regular human input signal is being input. If it is determined that no video signal is being input,
The synchronization signal is switched to the synchronization system of the character generation circuit including VRAM, and all screens are switched to the character generation circuit side to prevent noise from being displayed on the main screen (external video signal) side, and the audio output is also muted. The present invention provides a video display circuit capable of switching from one source to another.

The video signal is read out from the storage element (9) based on the read clock, and switched based on the output signal of the detection circuit (21) so that only the read video signal is supplied to the monitor. It is configured to control the circuit (10).

[Means for Solving the Problems] A video display circuit according to the present invention reads a video signal from a storage element (9) based on a synchronization signal of an external video signal supplied from the outside, and superimposes the video signal on the external video signal. The video display circuit that outputs the video signal includes a detection circuit (21) that detects the presence or absence of an external video signal, and a clock generation unit (6A, 7.8) that forms a read clock for reading the video signal from the storage element (9). ), a switching circuit (10) that selectively supplies the external video signal and the video signal from the storage element (9) to the monitor, and a detection circuit (21).
When it is detected that the external video signal is not inputted by the detection circuit (21), the detection circuit (21) internally generates a synchronization signal based on the readout clock generated by the clock generation means (6A, 7.8). ) detects the presence or absence of an external video signal supplied from the outside. When there is an external video signal, the superimpose mode is set in which the video signal read from the storage element (9) is superimposed on the external video signal and displayed, but when there is no external video signal, the clock generating means (6)
A, 7.8) internally forms a synchronizing signal based on the readout clock formed and supplies it to the monitor to achieve internal synchronization, and reads the video signal from the storage element (9) based on the readout clock; Only this read video signal is supplied to the monitor for display. That is, the external video signal is erased and only the video signal from the storage element is displayed as if it were written on a blackboard (hereinafter referred to as blackboard mode). This alleviates the discomfort caused by noise when selecting a non-broadcasting channel or when a broadcast ends, making it possible to stably display the video signal from the storage element (9) and make it easier to use.

[Example] Hereinafter, an example of the present invention will be described in detail based on FIGS. 1 to 3.

FIG. 1 shows the overall configuration of this embodiment. In the figure, parts corresponding to those in FIG. 4 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

In this embodiment, a video signal detection circuit (21) is provided at the input end to detect the presence or absence of an external video signal from the input terminal (1). This video signal detection circuit (2) generates, for example, a high level output signal when there is an external video signal, and generates, for example, a low level output signal when there is no external video signal or when noise other than the regular video signal is present. Generates an output signal. The output signal of the video signal detection circuit (21) is supplied to the enable terminal EN of the clock generation PLL circuit (68), and is also supplied to the synchronization switching switch circuit (22) as a switching signal, and is further supplied to the NAND circuit (23). ) as a gate signal.

The PLL circuit (6A) has an enable terminal EN, and when the output signal of the video signal detection circuit (21) is high level, the phase comparator is enabled and phase comparison is performed, and when it is low level, phase comparison is not performed. , the internal oscillator is applied with a constant voltage and becomes free running. The synchronization switching circuit (22) selects the composite synchronization signal (external synchronization signal) from the synchronization separation circuit (2) when the output of the video signal detection circuit (21) is high level, and when it is low level,
An adder (24) adds the outputs of the dot counter (7) and the line counter (8), and selects an internal synchronization signal that is a composite of horizontal and vertical synchronization.

The high-speed switch circuit (23) is configured to be switched by the output signal of the NAND circuit (23).
23) When the output signal is high level, V RAM
(It passes the video signal from 91, and when it is low level, it passes the external video signal from the input terminal (1).The other input terminal of the NAND circuit (23) is connected to the inverter (25).
A high-speed switch control human input signal is supplied from the control input terminal (26) via the control input terminal (26).

Next, the operation of the circuit shown in FIG. 1 will be explained. Now, input terminal (1
), the presence of the external video signal is detected by the video signal detection circuit (21),
A high level output signal is output to its output side. This high-level output signal is supplied to the enable terminal (6A) of the PLL circuit (6A), and is also supplied to one input terminal of the synchronization switching circuit (22) and the NAND circuit (23).

When the enable terminal (6A) of the PLL circuit (68) becomes high level, the internal phase comparator (not shown) is enabled, and a dot clock synchronized with the external video signal is output from the PLL circuit (6A). Ru. Based on this dot clock, an address signal is generated by the dot counter (7) and line counter (8), whereby the contents of VRAM (9) are read out and supplied to the high speed switch circuit (10). .

Since one input terminal of the NAND circuit (23) is now at a high level, the output signal of the NAND circuit (23) depends on the high speed switch control manual signal from the control input terminal (26). The output signal of the NAND circuit (23) is supplied as a switching signal to the high speed switch circuit (10), and high speed switching is performed depending on the high speed switch control input signal. As a result, a signal is obtained at the output terminal (11) in which the video signal from the VRAM (9) is superimposed on the external video signal from the input terminal (1).

Furthermore, when the output signal from the video signal detection circuit (21) is at a high level, the synchronization switching switch circuit (22) selects the composite synchronization signal from the synchronization separation circuit (2) and sends it to the synchronization output terminal (5). Output. This makes it possible to provide the monitor with synchronization that can quickly track even signals with a lot of jitter, such as those from a VTR.

Next, when the external video signal supplied from the input terminal (1) disappears, the output signal of the video signal detection circuit (21) becomes low level. As a result, the phase comparator of the PLL circuit (6A) is disabled, and a constant voltage is applied to the internal oscillator (not shown), resulting in a free run state.

A dot counter (7) and a line counter (8) operate on the oscillation frequency of the oscillator in this free-running state, and their outputs are combined in an adder (24) to form an internal synchronization signal, which is used in the switch circuit ( 22) and is led out to the synchronous output terminal (5) and supplied to the monitor.

Also, dot counter (7) and line counter (8)
The contents of V RAM (9) are read out by the address signal from V RAM (9) and supplied to the high speed switch circuit (10). Since one input terminal of the NAND circuit (23) is now at low level, the output signal of the NAND circuit (23) is always at a high level regardless of the high speed switch control input signal from the control input terminal (26). Therefore, the high speed switch circuit (10) outputs only the video signal from the VRAM (9) to the video output terminal (11) and supplies it to the monitor. In other words, the display mode of the monitor becomes a blackboard mode in which the main screen (external video signal) is turned off and only the video signal from V RAM (9) is displayed.

In this way, in this embodiment, the noise component becomes the input signal when a non-broadcast channel is selected or after the broadcast ends, but in such cases, only the video signal from V RAM (9) is internally synchronized. Since it is displayed, the video signal from the VRAM (9) can be viewed in a stable state without being affected by noise. Furthermore, when an external video signal is not present, the audio signal is also often not normal. For example, when a non-broadcast channel is selected, the sound is filled with noise in addition to the video, making it difficult to hear. Therefore, in such a case, it may be possible to mute the sound or generate an artificial sound to indicate that the official signal is not being generated manually.

Figure 2 shows an example of a specific circuit configuration of the video signal detection circuit (21) used in Figure 1.
A sync separation circuit (32) extracts a composite sync signal including a horizontal sync signal and a vertical sync signal from an external video signal from an external video signal, and extracts only a vertical sync signal from the composite sync signal extracted by the sync separation circuit (32). a sufficiently narrow-band low-pass filter (33), a waveform shaping circuit (34) that shapes the vertical synchronization signal extracted by this low-pass filter (33), and a vertical synchronization signal from this waveform shaping circuit (34). A retriggerable mono multi (3) that is triggered by a signal and outputs a signal indicating the presence of an external video signal at the output terminal (36).
5) It is empty.

Next, the operation of the circuit shown in FIG. 2 will be explained with reference to FIG. Now, when an external video signal S1 as shown in FIG. 3A is supplied from the input terminal (31) to the synchronization separation circuit (2), a horizontal synchronization signal (as shown in FIG. 3B) is supplied to the output side of the synchronization separation circuit (2). Hsy
A composite synchronization signal S2 is obtained, which includes a vertical synchronization signal (Vsync) and a vertical synchronization signal (Vsync). This composite synchronization signal S2 is supplied to a low-pass filter (33), where only the vertical synchronization signal S3 is extracted as shown in FIG. 3C. This vertical synchronizing signal S3 is waveform-shaped by a waveform shaping circuit (34) to become a signal S4 as shown in the third diagram. This waveform-shaped vertical synchronization signal S4 is supplied to a retriggerable multi-channel (35). The time constant of this retriggerable multiple (35) is set to a length of one vertical period or more, as shown in FIG. 3E.

Therefore, the retriggerable multi (35) uses the vertical synchronization signal S4.
When supplied, as shown in Figure 3, it is triggered in synchronization with the falling edge of the signal, maintains that state, and outputs the output terminal (3).
6) outputs a high level signal S5.

In other words, the high level of the output terminal (36) indicates that the external video signal is present at the input terminal (31).

Further, if there is no signal at the input terminal (31), no output is output from the synchronous separation circuit (32), and the low-pass filter (33
) and the waveform shaping circuit (34) also have no output, the retriggerable multi (35) is not triggered, its output becomes low level, and the level of the output terminal (36) also becomes low level. Also, when noise is input from the input terminal (31), binarized noise is output to the output side of the synchronization separation circuit (32), but this noise is cut by the narrow band low-pass filter (33). As a result, the retriggerable multi (35) is not triggered and the output terminal (
36) is a low level. In other words, the low level of the output terminal (36) means that the level of the input terminal (36) is low.
31) indicates that no external video signal exists.

In this way, when a regular signal is input, the retriggerable multi (35) continues to be triggered, but when there is no human power or noisy human power, the retriggerable multi (35) is not triggered, and this retriggerable multi (35) 35, that is, the level of the output terminal (36), it is possible to detect the presence or absence of an external video signal.

〔Effect of the invention〕

As described above, according to the present invention, a detection circuit is provided for detecting the presence or absence of an external video signal, and when the detection circuit detects that the external video signal is not input manually, the readout signal generated by the clock generation means is activated. A synchronizing signal is internally formed based on the clock and supplied to the monitor, and a video signal is read out from the storage element based on the read clock and supplied to the monitor, so it can be used when selecting a non-broadcasting channel or when a broadcast ends. The discomfort caused by the noise is alleviated, and the display of the video signal from the storage element can be made stable and easy to see and use.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing an example of essential parts of the invention, FIG. 3 is a diagram for explaining the operation of FIG. FIG. 4 is a circuit configuration diagram showing an example of a conventional circuit. (2) is a sync separation circuit, (3) is a horizontal sync separation circuit, (
4) is a frame start detection circuit, (68) is a clock generation PLL circuit, (7) is a dot counter, (8) is a line counter, and (9) is a video RAM (VRAM).
, (10) is a high-speed switch circuit, (21) is a video signal detection circuit, and (22) is a synchronous switching circuit.

Claims (1)

[Scope of Claims] A video display circuit that reads a video signal from a storage element based on a synchronization signal of an external video signal supplied from the outside, superimposes it on the external video signal, and outputs the superimposed signal, comprising: a detection circuit for detecting the presence or absence of the video signal; a clock generating means for forming a read clock for reading the video signal from the storage element; and selectively supplying the external video signal and the video signal from the storage element to a monitor. a switching circuit, when the detection circuit detects that the external video signal is input, internally generates a synchronizing signal based on the read clock generated by the clock generating means, and The switching circuit is controlled based on the output signal of the detection circuit so as to supply the video signal to the monitor, read the video signal from the storage element based on the read clock, and supply only the read video signal to the monitor. A video display circuit characterized in that: