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JPH03190413A - Voltage controlled oscillator - Google Patents

Voltage controlled oscillator

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Publication number
JPH03190413A
JPH03190413A JP33207789A JP33207789A JPH03190413A JP H03190413 A JPH03190413 A JP H03190413A JP 33207789 A JP33207789 A JP 33207789A JP 33207789 A JP33207789 A JP 33207789A JP H03190413 A JPH03190413 A JP H03190413A
Authority
JP
Japan
Prior art keywords
varactor
voltage
reverse bias
varactors
oscillation frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33207789A
Other languages
Japanese (ja)
Inventor
Toshihiko Kaneko
俊彦 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP33207789A priority Critical patent/JPH03190413A/en
Publication of JPH03190413A publication Critical patent/JPH03190413A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To make the oscillating frequency wide by applying a voltage bringing a 1st varactor into a reverse bias state externally via a 2nd terminal and an RF blocking resistor circuit, and also a 2nd varactor. CONSTITUTION:When capacitors C5, C6 are connected in series with frequency adjustment varactors D1, D2 respectively and a reference voltage is applied to the varactors D1, D2 via reference voltage supply terminals 14, 15 and RF blocking resistors R4, R5 with a sufficiently high resistance to keep the reverse bias state of the varactors D1, D2. Moreover, 2nd varactors D3, D4 in the reverse bias state are connected in parallel with inductors L1, L2 via capacitors C3, C4 with a control voltage applied externally through control voltage supply terminals 12, 13 and RF blocking resistors R2, R3 with a sufficiently high resistance. Thus, the oscillation at a broad band is attained while the modulation sensitivity of an oscillator is suppressed even at an oscillating frequency over the X band.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電圧制御発振器に関し、特に発振周波数調整用
素子としてバラクタを用いた非安定マルチバイブレータ
の発掘周波数の可変回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voltage controlled oscillator, and more particularly to a variable circuit for excavating frequency of an unstable multivibrator using a varactor as an oscillation frequency adjusting element.

〔従来の技術〕[Conventional technology]

従来この棟のMMIC化電圧制御発振器として、第2図
の回路図に示すものがある。この回路は、発振用GaA
s F E T Qt 、Q2、キャパシタ(又は逆バ
イアス状態のバラクタ)(、x、Cz、及びインダクタ
L 1. L z で非安定マルチバイブレータを構成
し、バラクタIh、Dzは制御電圧供給用端子11並び
にその抵抗値の充分誦いRF阻止用抵抗R1を介して外
部から制御電圧VCONT 1が印加され逆バイアス状
態となっており、これらは等制約に逆パイアス電圧値に
依存して決定される内部の接合容量を持つキャパシタと
みなすことができる。この逆バイアス電圧値によって決
まる接合容量の変化により発振周波数の制御が可能とな
る。
A conventional MMIC voltage controlled oscillator in this building is shown in the circuit diagram of FIG. This circuit uses GaA for oscillation.
s F E T Qt , Q2, a capacitor (or a varactor in a reverse bias state) (, A control voltage VCONT 1 is applied from the outside through the RF blocking resistor R1, resulting in a reverse bias state. The oscillation frequency can be controlled by changing the junction capacitance determined by the reverse bias voltage value.

ここでF E T Qsは発振用FETQt、Qhの電
流源用FETであり、バクファアンプ1,2はそれぞれ
非安定マルチバイブレータの正相、逆相各出力を受けそ
の出力はそれぞれ出力端子16.17に出力される。ま
た、各回路の電源は正電源供給端子18.19を介して
正電源VDDが、負′1源供給端子6を介して負’RE
源Vssが供給される。
Here, FET Qs is a current source FET for oscillation FETs Qt and Qh, and buffer amplifiers 1 and 2 receive the positive phase and negative phase outputs of the unstable multivibrator, respectively, and the outputs are sent to output terminals 16 and 17, respectively. Output. In addition, the power supply for each circuit is such that the positive power supply VDD is supplied through the positive power supply terminals 18 and 19, and the negative 'RE' is supplied through the negative '1 source supply terminal 6.
A source Vss is supplied.

なお、この徨のMMIC化電圧制電圧制御発振器常、分
訓器、位相比較器、クリスタルを用いた基準周波数発振
器、ローパスフィルタ、あるいはこれらが一体制された
フェーズロックルーズ(PLL)ICと組合せて使用さ
れ、そのフェーズロックルーズ(PLL)fこより周波
数の安定化に用いられる。
In addition, this MMIC-based voltage control voltage control oscillator, divider, phase comparator, reference frequency oscillator using a crystal, low-pass filter, or in combination with a phase-lock-loose (PLL) IC in which these are integrated The phase-lock-loose (PLL) f is used to stabilize the frequency.

次に、集2図の回路の各素子値と発振周波数の関係を計
算機シミュレーシ叢ンした結果を説明する。
Next, the results of computer simulation of the relationship between each element value and the oscillation frequency of the circuit shown in Figure 2 will be explained.

第3図はこのシミュレーシ箇ンで用いた周波数a4整用
バラクタ(Dl、D2)の逆バイアス電圧対接合容量の
関係を示すグラフである。同図は能動層をイオン注入で
形成したゲート長0.8μm1ゲ一ト巾300μm O
) GaAs F E Tのドレイン・ソース間をショ
ートして得られたシ1ットキパリアダイオードの実測値
より等価回路のパラメータを求め、その計算結果により
算出したものである。
FIG. 3 is a graph showing the relationship between the reverse bias voltage and the junction capacitance of the frequency a4 adjusting varactors (Dl, D2) used in this simulation. The figure shows an active layer formed by ion implantation with a gate length of 0.8 μm and a gate width of 300 μm.
) The parameters of the equivalent circuit were determined from the actual measured values of a shutt-chip parier diode obtained by shorting the drain and source of a GaAs FET, and the parameters were calculated based on the calculation results.

第4図は第3図に示す特性の周波数調整用バラクタを用
いた時の周波IPI調整用バラクタの逆バイアス直圧に
対する発振器の発振周数数の変化を示すグラフである。
FIG. 4 is a graph showing the change in the oscillation frequency of the oscillator with respect to the reverse bias direct pressure of the frequency IPI adjusting varactor when the frequency adjusting varactor having the characteristics shown in FIG. 3 is used.

ここで発振用F E T Q s 、 Q 2は、ゲー
ト長0.8 A m 、ゲート幅100 tim (7
) GaAsF E T 、インダクタLx、Lzは0
.36nH,キャパシタCI、C2は0.3 p Fに
設定した。なお、ノ(ッファアンプとしては、ソースフ
ォロワを用い、コc))時I)供給電sハv、D= +
5 V、 vss=−5Vとしている。同図より周波数
調整用バラクタの逆バイアス電圧が−1〜−2■の範囲
、すなわち第3図より周波数調整用バラクタの接合容量
が0.33〜0.23pFの範囲で発振周波数が約IG
H2変化していることがわかる。従って、この時の発振
器の変調感度は約IGHz/Vとなる。
Here, the oscillation FETQs, Q2 has a gate length of 0.8 A m and a gate width of 100 tim (7
) GaAsF E T , inductors Lx and Lz are 0
.. 36 nH, capacitors CI and C2 were set to 0.3 pF. In addition, when (a source follower is used as an amplifier, c)) I) Supply power s, D=
5V, vss=-5V. From the figure, when the reverse bias voltage of the frequency adjustment varactor is in the range of -1 to -2■, that is, from Fig. 3, when the junction capacitance of the frequency adjustment varactor is in the range of 0.33 to 0.23pF, the oscillation frequency is approximately IG.
It can be seen that H2 is changing. Therefore, the modulation sensitivity of the oscillator at this time is approximately IGHz/V.

次に、第2図のインダクタLs、Lzと並列にキャパシ
タCc P接続した時の各素子値と発振周波数の関係の
計算機シミーレージ覆ン結果を8g5図のグラフに示す
。なお、計算の簡略化の為、シミエレーシ曹ンでは周波
数調整用バラクタ、バツファアング及び電流源用FET
を省略し、また、発振用FETはゲート長0.8μm、
ゲート巾300μmのGaAs F E ’1’ 、発
振器の負荷をIKΩの抵抗としている。この図からイン
ダクタンスL=0、25 n Hの時、インダクタお並
列に接続したキャパシタの容量Ccが0.3〜0.6p
Fの範囲で発振周波数が約2GH,変化していることが
わかる。
Next, the computer shimmy results of the relationship between each element value and the oscillation frequency when the capacitor CcP is connected in parallel with the inductors Ls and Lz of FIG. 2 are shown in the graph of FIG. 8g5. In order to simplify the calculation, in the simulation, a varactor for frequency adjustment, a buffer angle, and an FET for the current source are used.
is omitted, and the gate length of the oscillation FET is 0.8 μm,
The gate width is 300 μm, and the load of the oscillator is made of GaAs F E '1' with a resistance of IKΩ. From this figure, when the inductance L=0, 25 nH, the capacitance Cc of the capacitor connected in parallel with the inductor is 0.3 to 0.6 p.
It can be seen that the oscillation frequency changes by about 2 GH within the F range.

この容量をバラクタで実現しようとすると、@3図から
約−1,2〜−〇、1■の逆バイアス電圧をバラクタに
印加すればよい。従って、この時の発振器の変調感度は
約2GH,/Vとなる。
If this capacitance is to be realized by a varactor, a reverse bias voltage of approximately -1, 2 to -0, 1 ■ should be applied to the varactor, as shown in Figure @3. Therefore, the modulation sensitivity of the oscillator at this time is approximately 2 GH,/V.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のMMIC化電圧制電圧制御発振器い発振
周波数(例えばXバンド以上)が要求される場合、発振
周波数に対する各素子の素子感度が大きくなり、僕のた
めバラクタに印加する逆バイアス電圧に対する発振周波
数の変化率も大きくなり、すなわち電圧制御発振器の変
調感度が大きくなる。この電圧制御発振器は、周波数調
整用バラクタD1.Dzによる発振周波数制御の他に、
インダクタL1.Ltに並列にバラクタを入れても同様
な発振周波数の制御が可能なことがわかるが、その変調
感度はいずれもG HZ/Vオーダと可成高い。
When an oscillation frequency (for example, X band or higher) is required for the above-mentioned conventional MMIC voltage controlled voltage controlled oscillator, the element sensitivity of each element to the oscillation frequency increases, and the oscillation to the reverse bias voltage applied to the varactor increases. The rate of change in frequency also increases, ie, the modulation sensitivity of the voltage controlled oscillator increases. This voltage controlled oscillator includes a frequency adjusting varactor D1. In addition to the oscillation frequency control by Dz,
Inductor L1. It can be seen that similar control of the oscillation frequency is possible even if a varactor is inserted in parallel with Lt, but the modulation sensitivity is quite high, on the order of GHZ/V.

この電圧制御発振器を用いて外部のPLL構成回路とフ
ェーズロックルーズを構成する場合、系の位相雑音の増
加を招くという問題があり、またDCラインへのRF酸
成分ノイズの廻り込みにより発振周波数の変動が発生す
る確率が高くなるため、高い同波数安定度が必要とされ
る発振器の場合高安定の電源が必要になる。また、DC
ライン上ζこバイパスコンデンサを多用することによる
ペレットサイズの増大、すなわちベレットのコストアッ
プする等の欠点がある。
When this voltage controlled oscillator is used to configure a phase-locked loose circuit with an external PLL configuration circuit, there is a problem that the phase noise of the system increases, and the oscillation frequency decreases due to the RF acid component noise entering the DC line. Since the probability of fluctuations increasing, a highly stable power source is required for oscillators that require high same-wavenumber stability. Also, D.C.
There are drawbacks such as an increase in pellet size due to frequent use of bypass capacitors on the line, that is, an increase in pellet cost.

これらの問題の対策として、電圧感度の低いバラクタを
用いることが考えられるが、MMIC化する場合、バラ
クタはGaAsシlットキバリアダイオードを用いるこ
とになり、その接合容量の電圧感度を下げるIこは、能
動層を深くして、その深さに応じてキャリア濃度に勾配
を設ける必要があり、これはプロセス的にその制御性が
難しく、また仮に実現できたとしても特殊なプロセスが
追加されることになり、コストアップの要因となる。
One possible solution to these problems is to use a varactor with low voltage sensitivity, but when implementing an MMIC, a GaAs Schittky barrier diode will be used as the varactor, which reduces the voltage sensitivity of its junction capacitance. To do this, it is necessary to deepen the active layer and create a gradient in carrier concentration depending on the depth, which is difficult to control in terms of process, and even if it could be achieved, a special process would be required. This results in an increase in costs.

また、電圧感度の低いバラクタを用いると発振周波数の
変化範囲が狭くなり、発振器の汎用性が薄れるという欠
点がある。
Further, if a varactor with low voltage sensitivity is used, the range of change in the oscillation frequency becomes narrow, and the versatility of the oscillator is reduced.

本発明の目的は、このような欠点を除き、Xバンド以上
の周波数でも特殊な構造のバラクタを必要とせずに、発
振器の変調感度の増大を防ぎつつ発振周波数の広帯域化
を実現できるMMIC化電圧制電圧制御発振器すること
にある。
The purpose of the present invention is to eliminate such drawbacks and provide an MMIC voltage that can realize a wide band of oscillation frequencies while preventing an increase in the modulation sensitivity of the oscillator without requiring a varactor with a special structure even at frequencies above the X band. There is a voltage control oscillator.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の構成は、発振用能動素子としてGaA 5FE
Tを発掘周波数決定素子としてインダクタ及び第1キャ
パシタ(または逆バイアス状態とした第2のバラクタ)
を、発掘周波数調整用素子として第1の端子から印加さ
れた制御電圧により逆バイアス状態におかれた第1のバ
ラクタをそれぞれ用い、出力部にバッファアンプを備え
た非安定マルチバイブレータからなる電圧制御発振器に
おいて、前記第1のバラクタの容量変化範囲を低減する
ようにこの第1のバラクタに直列に第2キャパシタを接
続し、この接続点に第2の端子及びRF阻止用抵抗を介
して外部から前記第1のバラクタを逆バイアス状態にす
る電圧を印加し、前gピインダクトに並列Iこ直流阻止
用キャパシタを介して、第3のバラクタを接続し、この
接続点に第3の端子及びRF阻止用抵抗を介して外部か
らこの第3のバラクタを逆バイアス状態にする電圧を印
加したことを偶徴とする。
The configuration of the present invention uses GaA 5FE as an oscillation active element.
An inductor and a first capacitor (or a second varactor in a reverse bias state) with T as an excavation frequency determining element.
The voltage control system consists of an unstable multivibrator equipped with a buffer amplifier at the output section, using a first varactor put in a reverse bias state by a control voltage applied from the first terminal as an excavation frequency adjustment element, respectively. In the oscillator, a second capacitor is connected in series to the first varactor so as to reduce the range of capacitance change of the first varactor, and a second capacitor is connected to the connection point from the outside via a second terminal and an RF blocking resistor. A voltage is applied that puts the first varactor in a reverse bias state, a third varactor is connected to the front g pin induct via a parallel I DC blocking capacitor, and a third terminal and an RF blocking capacitor are connected to this connection point. It is assumed that a voltage is applied from the outside through the resistor to put the third varactor in a reverse bias state.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の回路図である。本実施例は
、従来の欠点を解決するため、第1図のように、変調感
度低減の目的で、周波数調整用バラクタD1.D2の接
合容量の変化範囲を狭くするように、これらバラクタI
h、Dzと直列にキャパシタCs 、Csをそれぞれ接
続すると共にその接続点にバラクタ基準電圧供給用端子
14.15及び抵抗ll&の充分高いRF阻止用抵抗R
a、Rsを介して外部より基準電圧を印加してバラクタ
DI 、Dzの逆バイアス状態を維持している。
FIG. 1 is a circuit diagram of an embodiment of the present invention. In this embodiment, in order to solve the conventional drawbacks, as shown in FIG. 1, for the purpose of reducing modulation sensitivity, a frequency adjustment varactor D1. These varactors I
Capacitors Cs and Cs are connected in series with h and Dz, respectively, and a varactor reference voltage supply terminal 14.15 and a sufficiently high RF blocking resistor R of resistor ll& are connected at the connection point.
A reference voltage is applied externally via a and Rs to maintain the reverse bias state of the varactors DI and Dz.

また、これによって生じる発幾周波数帝゛域の狭帯域化
は、インダクタL1.L2と並列に直流阻止コンデンサ
C3,C4を介して制御電圧供給用端子12.13及び
抵抗値の充分^いRF阻止用抵抗Rz、Rsを通じて外
部より印加される制御電圧vcoNTgにより逆バイア
ス状態にある第2のバラクタDa、D4を接続している
。これらバラクタDs、Daの逆バイアス電圧値に応じ
たバラクタの接合容量により、8g5図に示した如き発
振周波数の変化が得られるので解決される。
Moreover, the narrowing of the frequency range caused by this is caused by the inductor L1. It is in a reverse bias state by a control voltage vcoNTg that is applied from the outside through DC blocking capacitors C3 and C4 in parallel with L2 and through control voltage supply terminals 12.13 and RF blocking resistors Rz and Rs with sufficient resistance. Second varactors Da and D4 are connected. The problem is solved because the oscillation frequency changes as shown in Fig. 8g5 due to the junction capacitance of the varactors depending on the reverse bias voltage value of these varactors Ds and Da.

ここで第2のバラクタD3.D4の制at圧VCONT
 2は発儀器の発振可能周波数帯域のうち、必要な発振
周波数、例えはfl の近傍まで発振周波数をシフトす
るもので、これは固定′電圧となる。
Here, the second varactor D3. D4 control pressure VCONT
2 shifts the oscillation frequency to a necessary oscillation frequency, for example, near fl, within the oscillation frequency range of the oscillator, and this becomes a fixed voltage.

一方、810周波数調整用バラクタDI 、Dzの制御
電圧vcoNr□は発振周波数の安定化の目的でPLL
IC等より印加され、発振周波数の漂動と共に常に変化
する。
On the other hand, the control voltage vcoNr□ of the 810 frequency adjustment varactors DI and Dz is connected to the PLL for the purpose of stabilizing the oscillation frequency.
It is applied from an IC or the like, and constantly changes as the oscillation frequency fluctuates.

次に、具体例として、第1図の周波数調整用バラクタD
I 、D2がθ〜2vの逆バイアス電圧に対して0.3
〜0.6pFの範囲で接合容量が変化したと仮定して、
これに直列に0.3 p Fのキャパシタを接続すると
その合成容量は0.15〜0.2pFとなり、同じ逆バ
イアス電圧に対して接合容菫賀化illは1/6となる
。このとき、谷貸値の低下分に対応してインダクタL*
、Lzのインダクタンスを増やし、発振周波数を一定値
に保つと、発振器の変調感度は接合容量変化範囲の低減
分と同等の低減が期待できる。
Next, as a specific example, the frequency adjustment varactor D shown in FIG.
I, D2 is 0.3 for a reverse bias voltage of θ~2v
Assuming that the junction capacitance changes in the range of ~0.6 pF,
When a 0.3 pF capacitor is connected in series with this, the combined capacitance becomes 0.15 to 0.2 pF, and the junction capacitance Suga ill becomes 1/6 for the same reverse bias voltage. At this time, in response to the decrease in the valley value, the inductor L*
, Lz is increased and the oscillation frequency is kept at a constant value, the modulation sensitivity of the oscillator can be expected to be reduced by the same amount as the reduction in the junction capacitance change range.

尚、第2のバラクタDs、Daの制御電圧VcoNrz
は半固定ボリューム等を用いである種変可変できるよう
にしておけば、001路素子のバラツキを吸収できる。
Note that the control voltage VcoNrz of the second varactors Ds and Da
If it is made variable by using a semi-fixed volume or the like, variations in the 001 path elements can be absorbed.

また、本実施例では発振周波数決定用キャパシタとして
固定キャパシタC1,C2を用いているが、これを逆バ
イアス伏態のバラクタを使用しても同様な効果か得られ
る。
Further, although fixed capacitors C1 and C2 are used as the oscillation frequency determining capacitors in this embodiment, the same effect can be obtained even if a reverse biased varactor is used instead.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、非安定マルチバイブレー
タ構成のMMIC化屯圧制御発振器の周波数A壁用バラ
クタに直列iこキャパシタを接続してバラクタの逆バイ
アス電圧による接合容量変化範囲を狭くすると共に、発
振周波数決定用インダクタに並列に直流阻止キャパシタ
を介して逆バイアスされた第2のバラクタを並列に接続
することにより、Xバンド以上の発振周波数でも発振器
の変調感度をおさえつつ広帯域での発振が可能となる。
As explained above, the present invention connects a series capacitor to the frequency A wall varactor of an MMIC pressure-controlled oscillator having an unstable multivibrator configuration to narrow the range of change in junction capacitance due to the reverse bias voltage of the varactor. By connecting a second reverse-biased varactor in parallel with the oscillation frequency determining inductor via a DC blocking capacitor, wideband oscillation can be achieved while suppressing the modulation sensitivity of the oscillator even at oscillation frequencies above the X band. It becomes possible.

従って、次のような効果がある。Therefore, there are the following effects.

1)特殊なバラクタを必要としないため、コストダウン
できる。
1) Cost can be reduced because no special varactor is required.

2)変調感度が低減されるため、DCラインへのRF酸
成分ノイズの廻り込みによる周波数変動が低減され、D
Cライン上のバイパスコンデンサの数量を少くでき、ペ
レットサイズを小形化でき、外部のPLL構成回路とフ
ェーメロックループを構成した場合、系の位相雑音を低
減できる。
2) Since the modulation sensitivity is reduced, frequency fluctuations caused by RF acid component noise entering the DC line are reduced, and D
The number of bypass capacitors on the C line can be reduced, the pellet size can be reduced, and when a femelock loop is configured with an external PLL configuration circuit, the phase noise of the system can be reduced.

3)発振周波数帯域が広帯域であるため汎用性が大きい
3) The oscillation frequency band is wide, so it has great versatility.

4)第2のバラクタの制御電圧がマニュアルで可変でき
るので素子値のバラツキをある程度吸収できる。
4) Since the control voltage of the second varactor can be varied manually, variations in element values can be absorbed to some extent.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のMMIC化電圧制電圧制御発振器施例
の回路図、第2図は従来のMMIC化電圧制御発奈器の
一例の回路図、第3図は第2図のバラクタの逆バイアス
電圧対接合容量の関係を示すグラフ、第4図は従来例と
して第2図の回路の各素子値と発掘周波数の関係を計算
機シミエレーシlンにより求めたグラフ、第5図は第2
図の発振周波数決定用インダクタに並列にキャパシタを
接続した際のそのキャパシタの容量、インダクタのイン
ダクタンスと発振器の発振周波数の関係を示したグラフ
である。 1.2・・・・・・バッファアンプ、11〜15・・・
・・・電圧印加端子、16.17・・・・・・出力端子
、18〜20・・・・・・′電源端子、Ql、C2・・
・・・・発振用GaAs FET、Qs・・・・・・′
Kl!il!、源用FET%n、 *Dz +D3 e
D4・・・・・・発振周波数調整用バックタ=需=ヰ、
Cs 、 Cz 、−0−0発振周波数決定用キャパシ
タ、C3゜C4・・・・・・直流阻止キャパシタ、C5
,C6・・・・・・キャパシタ、Lx、Lx・・・・・
・発振周波数決定用インダクタ、R1〜Rs・・・・・
・RF阻止用抵抗。 竿1図
Fig. 1 is a circuit diagram of an example of an MMIC voltage controlled voltage controlled oscillator according to the present invention, Fig. 2 is a circuit diagram of an example of a conventional MMIC voltage controlled oscillator, and Fig. 3 is the inverse of the varactor shown in Fig. 2. A graph showing the relationship between bias voltage and junction capacitance. Figure 4 is a graph showing the relationship between each element value and excavation frequency of the circuit in Figure 2 as a conventional example, obtained by computer simulation. Figure 5 is a graph showing the relationship between
It is a graph showing the relationship between the capacitance of the capacitor, the inductance of the inductor, and the oscillation frequency of the oscillator when a capacitor is connected in parallel to the oscillation frequency determining inductor shown in the figure. 1.2...Buffer amplifier, 11-15...
...Voltage application terminal, 16.17...Output terminal, 18-20...'Power terminal, Ql, C2...
...GaAs FET for oscillation, Qs...'
Kl! Il! , source FET%n, *Dz +D3 e
D4...Oscillation frequency adjustment backter = demand = ヰ,
Cs, Cz, -0-0 oscillation frequency determining capacitor, C3゜C4...DC blocking capacitor, C5
, C6... Capacitor, Lx, Lx...
・Inductor for determining oscillation frequency, R1 to Rs...
・RF blocking resistor. Rod 1 diagram

Claims (1)

【特許請求の範囲】[Claims] 発振用能動素子としてGaAsFETを発振周波数決定
素子としてインダクタ及び第1のキャパシタ(または逆
バイアス状態とした第2のバラクタ)を、発振周波数調
整用素子として第1の端子から印加された制御電圧によ
り逆バイアス状態におかれた第1のバラクタをそれぞれ
用い、出力部にバッファアンプを備えた非安定マルチバ
イブレータからなる電圧制御発振器において、前記第1
のバラクタの容量変化範囲を低減するようにこの第1の
バラクタに直列に第2キャパシタを接続し、この接続点
に第2の端子及びRF阻止用抵抗を介して外部から前記
第1のバラクタを逆バイアス状態にする電圧を印加し、
前記インダクタに並列に直流阻止用キャパシタを介して
、第3のバラクタを接続し、この接続点に第3の端子及
びRF阻止用抵抗を介して外部からこの第3のバラクタ
を逆バイアス状態にする電圧を印加したことを特徴とす
る電圧制御発振器。
A GaAsFET is used as an oscillation active element, an inductor and a first capacitor (or a second varactor in a reverse bias state) are used as an oscillation frequency determining element, and a control voltage applied from the first terminal serves as an oscillation frequency adjusting element. In a voltage controlled oscillator comprising an unstable multivibrator using first varactors placed in a bias state and having a buffer amplifier at an output section, the first
A second capacitor is connected in series to this first varactor so as to reduce the capacitance change range of the varactor, and the first varactor is connected to this connection point from the outside via a second terminal and an RF blocking resistor. Apply a voltage to reverse bias,
A third varactor is connected in parallel to the inductor via a DC blocking capacitor, and this third varactor is externally reverse biased via a third terminal and an RF blocking resistor at this connection point. A voltage controlled oscillator characterized by applying a voltage.
JP33207789A 1989-12-20 1989-12-20 Voltage controlled oscillator Pending JPH03190413A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33207789A JPH03190413A (en) 1989-12-20 1989-12-20 Voltage controlled oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33207789A JPH03190413A (en) 1989-12-20 1989-12-20 Voltage controlled oscillator

Publications (1)

Publication Number Publication Date
JPH03190413A true JPH03190413A (en) 1991-08-20

Family

ID=18250887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33207789A Pending JPH03190413A (en) 1989-12-20 1989-12-20 Voltage controlled oscillator

Country Status (1)

Country Link
JP (1) JPH03190413A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002100962A (en) * 2000-09-21 2002-04-05 Texas Instr Japan Ltd Frequency characteristic adjustment circuit
US6667539B2 (en) * 2001-11-08 2003-12-23 International Business Machines Corporation Method to increase the tuning voltage range of MOS varactors
JP2006180513A (en) * 2004-12-22 2006-07-06 Agere Systems Inc Low-power dissipation cmos oscillator circuit having capacitively coupled frequency control
JP2007295198A (en) * 2006-04-24 2007-11-08 Mitsumi Electric Co Ltd Voltage-controlled oscillation circuit and its adjustment method
JP2011182459A (en) * 2011-05-20 2011-09-15 Mitsumi Electric Co Ltd Voltage-controlled oscillation circuit and pll circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002100962A (en) * 2000-09-21 2002-04-05 Texas Instr Japan Ltd Frequency characteristic adjustment circuit
US6667539B2 (en) * 2001-11-08 2003-12-23 International Business Machines Corporation Method to increase the tuning voltage range of MOS varactors
JP2006180513A (en) * 2004-12-22 2006-07-06 Agere Systems Inc Low-power dissipation cmos oscillator circuit having capacitively coupled frequency control
JP2007295198A (en) * 2006-04-24 2007-11-08 Mitsumi Electric Co Ltd Voltage-controlled oscillation circuit and its adjustment method
JP2011182459A (en) * 2011-05-20 2011-09-15 Mitsumi Electric Co Ltd Voltage-controlled oscillation circuit and pll circuit

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