JPH03198342A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03198342A JPH03198342A JP33966089A JP33966089A JPH03198342A JP H03198342 A JPH03198342 A JP H03198342A JP 33966089 A JP33966089 A JP 33966089A JP 33966089 A JP33966089 A JP 33966089A JP H03198342 A JPH03198342 A JP H03198342A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- film
- photoresist pattern
- forming
- protruding electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 50
- 238000009713 electroplating Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 18
- 230000001681 protective effect Effects 0.000 claims description 29
- 230000015572 biosynthetic process Effects 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 238000000059 patterning Methods 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 abstract description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 16
- 238000005530 etching Methods 0.000 abstract description 16
- 229920001721 polyimide Polymers 0.000 abstract description 16
- 239000009719 polyimide resin Substances 0.000 abstract description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 11
- 239000010931 gold Substances 0.000 abstract description 11
- 229910052737 gold Inorganic materials 0.000 abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- 238000002955 isolation Methods 0.000 abstract 1
- 238000007747 plating Methods 0.000 description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に突起電極を
有する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having protruding electrodes.
一般にテープキャリア方式の半導体装置では、半導体基
板の主面に突出する金属の突起電極を設けている。Generally, in a tape carrier type semiconductor device, a protruding metal electrode is provided on the main surface of a semiconductor substrate.
従来、この種の突起電極を有する半導体装置の製造方法
は、半導体基板に対する所要の素子形成工程及び配線形
成工程を全て終了した後、基板表面全体に新たに金属膜
を被着してこれを電解メッキの際の電流路として構成し
、その後この金属膜上にリフトオフ法等を利用して突起
電極形成領域の下地膜を形成し、更にフォトレジスト等
をマスクとしかつ前記金属膜を電流路とする電解メッキ
により突起電極形成領域に突起電極を形成し、その後不
要となった電解メッキの際の電流路である金属膜を突起
電極をマスクとして全面的に除去し、しかる後保護膜を
基板表面全面に塗布し、突起電極部のみ開口して最終保
護膜を形成する方法となっていた。Conventionally, in the manufacturing method of a semiconductor device having this type of protruding electrode, after completing all the necessary element formation steps and wiring formation steps on the semiconductor substrate, a new metal film is deposited on the entire surface of the substrate and this is electrolyzed. This is configured as a current path during plating, and then a base film is formed on this metal film for the protruding electrode formation area using a lift-off method, etc., and a photoresist or the like is used as a mask, and the metal film is used as a current path. A protruding electrode is formed in the protruding electrode formation area by electrolytic plating, and then the unnecessary metal film, which is a current path during electrolytic plating, is completely removed using the protruding electrode as a mask, and then a protective film is applied to the entire surface of the substrate. The method used was to apply the protective film to the surface of the protective film, and then open only the protruding electrode portions to form the final protective film.
上述した従来の突起電極を有する半導体装置の製造方法
は、突起電極形成後に保護膜を塗布し、フォトレジスト
等をマスクとして突起電極部の保護膜をエツチング除去
して最終保護膜を形成する方法となっていたので、エツ
チング工程でのエツチング残渣やフォトレジストを剥離
する工程での異物の再付着等が突起電極表面に生じやす
く、ボンディング時のリードと突起電極間の密着強度を
著しく低下させる要因となる欠点がある。The conventional method for manufacturing a semiconductor device having a protruding electrode as described above is a method in which a protective film is applied after the protruding electrode is formed, and the protective film on the protruding electrode portion is etched away using a photoresist or the like as a mask to form a final protective film. As a result, etching residue during the etching process and foreign matter re-adhering during the photoresist stripping process are likely to occur on the surface of the protruding electrode, which can significantly reduce the adhesion strength between the lead and the protruding electrode during bonding. There is a drawback.
さらに、突起電極と半導体基板間との密着強度を十分確
保させるためには、突起電極表面の周辺部を最終保護膜
が覆うような構造にしなければならないなめ、突起電極
を有する半導体装置を信頼性よく安定的に製造すること
が非常に困難であるという欠点がある。Furthermore, in order to ensure sufficient adhesion strength between the protruding electrode and the semiconductor substrate, it is necessary to create a structure in which the periphery of the protruding electrode surface is covered with a final protective film. The drawback is that it is very difficult to produce well and stably.
本発明の半導体装置の製造方法は、半導体基板上に配線
用金属膜を形成した後パターニングし、素子用配線及び
電解メッキ用配線を形成する工程と、全面に保護膜を形
成した後パターニングし、前記素子用配線の突起電極形
成領域と前記素子用配線と電解メッキ用配線とを電気的
に接続するための接続膜形成領域の保護膜、を除去する
工程と、保護膜が除去された前記突起電極形成領域およ
び接続膜形成領域にバリア膜を形成する工程と、突起電
極形成領域のこのバリア膜上に第1のフォトレジストパ
ターンを形成する工程と、全面に保護膜を形成した後第
2のフォトレジストパターンを用いてパターニングし、
前記第1のフォトレジストパターン上部の一部を露出さ
せる工程と、前記第2のフォトレジストパターンを除去
すると同時に第1のフォトレジストパターンも除去し前
記バリア膜を露呈させる工程と、残された前記保護膜を
マスクとした電解メッキにより露呈した前記バリア膜上
に突起電極を形成する工程と、突起電極形成後突起電極
間の短絡を解除するために前記電解メッキ用配線を選択
的に除去する工程とを含んで構成される。The method for manufacturing a semiconductor device of the present invention includes a step of forming a metal film for wiring on a semiconductor substrate and then patterning it to form wiring for an element and wiring for electrolytic plating, and forming a protective film on the entire surface and then patterning it. a step of removing a protective film from a protruding electrode formation region of the element wiring and a connection film formation region for electrically connecting the element wiring and the electrolytic plating wiring; and the protrusion from which the protective film has been removed. A step of forming a barrier film in the electrode formation region and a connection film formation region, a step of forming a first photoresist pattern on this barrier film in the protrusion electrode formation region, and a step of forming a second photoresist pattern after forming a protective film on the entire surface. Patterning using a photoresist pattern,
exposing a part of the upper part of the first photoresist pattern; removing the second photoresist pattern and simultaneously removing the first photoresist pattern to expose the barrier film; A step of forming a protruding electrode on the barrier film exposed by electrolytic plating using a protective film as a mask, and a step of selectively removing the electrolytic plating wiring to release a short circuit between the protruding electrodes after forming the protruding electrode. It consists of:
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)〜(j)及び第2図は本発明をテープキャ
リア式集積回路の突起電極形成に適用した第1の実施例
を説明するための図であり、第2図は製造工程途中にお
ける平面図、第1図(a)〜(j>はそのA−A’線に
おける製造工程順に示した半導体チップの断面図である
。以下製造工程順に説明する。FIGS. 1(a) to (j) and FIG. 2 are diagrams for explaining a first embodiment in which the present invention is applied to the formation of protruding electrodes of a tape carrier type integrated circuit, and FIG. 2 is a diagram showing the manufacturing process. 1(a) to 1(j) are cross-sectional views of the semiconductor chip taken along the line AA' in the order of manufacturing steps.The following will explain the steps in the order of the manufacturing steps.
まず第1図(a)に示すように、シリコンからなる半導
体基板1に素子を形成する。次で厚さ約1μmのシリコ
ン窒化M2が形成された素子領域及び半導体基板1の表
面が露出された幅約200μmのダイシングライン領域
I上に、スパッタ法により厚さ約0.8μmのアルミニ
ウム膜3を形成する。First, as shown in FIG. 1(a), elements are formed on a semiconductor substrate 1 made of silicon. Next, an aluminum film 3 with a thickness of about 0.8 μm is sputtered onto the device region where the silicon nitride M2 with a thickness of about 1 μm is formed and on the dicing line region I with a width of about 200 μm where the surface of the semiconductor substrate 1 is exposed. form.
次に第1図(b)に示すように、所望の厚さ及び形状に
第1のフォトレジストパターン4を形成し、これをマス
クとしたエツチング法により不要部分のアルミニウム膜
3を除去し、半導体装置に必要な素子用配線を形成する
。この素子用配線は突起電極形成領域■を含むアルミニ
ウム配線3aとして形成する。また、同時にダイシング
ライン領域Iに電解メッキ用配線3bを形成する。Next, as shown in FIG. 1(b), a first photoresist pattern 4 is formed in a desired thickness and shape, and unnecessary portions of the aluminum film 3 are removed by an etching method using this as a mask. Form wiring for elements necessary for the device. This element wiring is formed as an aluminum wiring 3a including a protruding electrode forming region (2). At the same time, electrolytic plating wiring 3b is formed in the dicing line region I.
次に第1図(c)のように、第1のフォトレジストパタ
ーン4を剥離した後、保護膜であるシリコン酸化膜5を
全面に約0.5μmの膜厚で成長させる0次で所望の厚
さ及び形状にパターニングした第2のフォトレジストパ
ターン6をマスクにして突起電極形成領域■と、アルミ
ニウム配線3aと電解メッキ用配線3bとを接続するた
めの接続膜形成領域■のシリコン酸化膜5をエツチング
除去する。Next, as shown in FIG. 1(c), after peeling off the first photoresist pattern 4, a silicon oxide film 5 as a protective film is grown on the entire surface to a thickness of about 0.5 μm. Using the second photoresist pattern 6 patterned to the desired thickness and shape as a mask, the silicon oxide film 5 is formed in the protruding electrode formation region (2) and the connection film formation region (3) for connecting the aluminum wiring 3a and the electrolytic plating wiring 3b. Remove by etching.
次に第1図(d)のように、第2のフォトレジストパタ
ーン6を残したまま、メッキ層を成長させる際のバリア
膜となる金属膜7を基板表面に被着する。ここで金属膜
7は、金が下層に拡散することを防ぐことを目的とした
膜厚0.1μmの白金膜と、白金膜と下地密着性を強化
することを目的とした膜厚0.1μmのチタン膜の2層
構造とする。Next, as shown in FIG. 1(d), a metal film 7, which will serve as a barrier film when growing a plating layer, is deposited on the substrate surface while leaving the second photoresist pattern 6 intact. Here, the metal film 7 includes a platinum film with a thickness of 0.1 μm for the purpose of preventing gold from diffusing into the underlying layer, and a platinum film with a thickness of 0.1 μm for the purpose of strengthening the adhesion between the platinum film and the base layer. It has a two-layer structure of titanium film.
次に第1図(e)のように、第2のフォトレジストパタ
ーン6を剥離することにより、同時に不要部分の金属膜
7をリフトオフ法により除去したのち、400°Cの窒
素雰囲気中で60分間熱処理することにより、突起電極
形成領域■内にバリアH7aを、また接続膜形成領域■
に電解メッキ用配線の接続膜7bを形成する。したがっ
て、ここでアルミニウム配線3aは接続膜7bによって
電解メッキ用配線3bと電気的に接続される。Next, as shown in FIG. 1(e), the second photoresist pattern 6 is peeled off, and at the same time, unnecessary portions of the metal film 7 are removed by a lift-off method, and then the metal film 7 is heated in a nitrogen atmosphere at 400°C for 60 minutes. By heat treatment, a barrier H7a is formed in the protruding electrode formation region (■), and a barrier H7a is formed in the connection film formation region (■).
A connection film 7b for electrolytic plating wiring is formed. Therefore, the aluminum wiring 3a is electrically connected to the electrolytic plating wiring 3b by the connection film 7b.
次に第1図(f)のように、約5μmの厚さにフォトレ
ジストを塗布し、突起電極形成領域■内のバリア膜7a
内にのみ所望の形状にパターニングした第3のフォトレ
ジストパターン8を形成する。Next, as shown in FIG. 1(f), a photoresist is applied to a thickness of about 5 μm, and the barrier film 7a in the protruding electrode formation region
A third photoresist pattern 8 patterned into a desired shape is formed only inside the photoresist pattern.
次に第1図(g)のように、最終保護膜であるポリイミ
ド樹脂9を約10μmの厚さに塗布し、所望の厚さ及び
形状にバターニングした第4のフォトレジストパターン
10をマスクにして、第3のフォトレジストパターン8
上の一部の領域及びダイシング領域工の各ポリイミド樹
脂9を除去する。ここに、第3のフォトレジストパター
ン8はその上層部の一部がポリイミド樹脂9の開口部を
通して露出する。Next, as shown in FIG. 1(g), a final protective film of polyimide resin 9 is applied to a thickness of approximately 10 μm, and a fourth photoresist pattern 10 patterned to the desired thickness and shape is used as a mask. Then, the third photoresist pattern 8
The polyimide resin 9 in the upper part of the area and the dicing area is removed. Here, a part of the upper layer of the third photoresist pattern 8 is exposed through the opening of the polyimide resin 9.
次に第1図(h)のように、第4のフォトレジストパタ
ーン10を除去すると同時に第3のフォトレジストパタ
ーン8をも除去し、バリア膜7aの一部を露呈させる。Next, as shown in FIG. 1(h), the fourth photoresist pattern 10 is removed and at the same time, the third photoresist pattern 8 is also removed to expose a part of the barrier film 7a.
ここに、突起電極形成領域■内のポリイミド樹脂9の断
面形状はオーバーハング状となる。なお、第2図の平面
構造はこの第1図(h)の工程完了状態を示している。Here, the cross-sectional shape of the polyimide resin 9 in the protruding electrode forming region (2) has an overhanging shape. Note that the planar structure in FIG. 2 shows the completed state of the process in FIG. 1(h).
次に第1図(i)のように、基板全体を金メッキ液に浸
漬し、半導体基板1と金メッキ装置側に設置された陽極
電極板との間に電流を流して、全突起電極11が突起電
極形成領域■のバリア膜7a上に15〜30μmの厚さ
に形成されるまで電解メッキを行う、ここに、全突起電
極11は、マスクとして用いたポリイミド樹脂9の断面
形状に応じて成長するため、ポリイミド樹脂9によって
バリア膜7a側におさえつけられた断面構造となり、下
地側との密着強度が著しく強固なものとなる。Next, as shown in FIG. 1(i), the entire substrate is immersed in a gold plating solution, and a current is passed between the semiconductor substrate 1 and the anode electrode plate installed on the gold plating equipment side, so that all the protruding electrodes 11 are protruded. Electrolytic plating is performed until a thickness of 15 to 30 μm is formed on the barrier film 7a in the electrode formation region (2). Here, the fully protruding electrodes 11 are grown according to the cross-sectional shape of the polyimide resin 9 used as a mask. Therefore, the cross-sectional structure is held down to the barrier film 7a side by the polyimide resin 9, and the adhesion strength to the base side becomes extremely strong.
次に第1図<j)のように、ポリイミド樹脂9及び全突
起電極11をマスクにしてエツチング法でダイシングラ
イン領域Iのシリコン酸化膜5を除去し、その後、接続
膜7bをエツチングのストッパーとして電解メッキ用配
線3bを除去してダイシングライン領域Iとアルミニウ
ム配線3aを絶縁分離することにより、全突起電極11
を有する半導体装置が完成する。Next, as shown in FIG. 1<j), the silicon oxide film 5 in the dicing line region I is removed by etching using the polyimide resin 9 and all the protruding electrodes 11 as masks, and then the connecting film 7b is used as an etching stopper. By removing the electrolytic plating wiring 3b and insulating and separating the dicing line region I and the aluminum wiring 3a, all the protruding electrodes 11
A semiconductor device having the following is completed.
このように第1の実施例では、電解メッキ時の電流路に
半導体素子用の配線と同時に形成した電解メッキ用配線
3bを利用し、電解メッキ工程の後にダイシングライン
領域工における不要の電解メッキ用配線3bを除去する
だけで、各々の突起電極が絶縁分離される構造となって
いるため、最終保護膜をマスクとして電解メッキを行う
ことが可能で、全突起電極11の表面にエツチング残渣
や異物の再付着等が発生することを根本的に防止するこ
とができる。また、最終保護膜であるポリイミド樹脂9
のオーバーハング状の断面形状により全突起電極11と
半導体基板1との密着強度も十分に確保することができ
る。In this way, in the first embodiment, the electrolytic plating wiring 3b, which is formed at the same time as the semiconductor element wiring, is used in the current path during electrolytic plating, and unnecessary electrolytic plating in the dicing line area processing is performed after the electrolytic plating process. Since each protruding electrode is insulated and separated by simply removing the wiring 3b, electrolytic plating can be performed using the final protective film as a mask, eliminating etching residue and foreign matter on the surface of all protruding electrodes 11. It is possible to fundamentally prevent the occurrence of redeposition, etc. of In addition, polyimide resin 9, which is the final protective film,
Due to the overhanging cross-sectional shape, it is possible to ensure sufficient adhesion strength between the entire protruding electrode 11 and the semiconductor substrate 1.
第3図(a)〜(h)は、本発明の第2の実施例を説明
するための製造工程順に示した断面図であり、第1の実
施例と同じ位置で切断した断面図である。3(a) to (h) are cross-sectional views shown in the order of manufacturing steps for explaining the second embodiment of the present invention, and are cross-sectional views taken at the same position as the first embodiment. .
まず第3図(a)に示すように、第1の実施例と同様に
シリコン窒化膜22を除去して半導体基板21の表面を
露呈させたダイシングライン領域Iと、シリコン窒化膜
22が形成された素子領域の全面にアルミニウム膜を被
着する。次で、所望の膜厚及び形状に形成した第1のフ
ォトレジストパターン24をマスクにして不要部分のア
ルミニウム膜を除去して、突起電極形成領域■を含むア
ルミニウム配線23aと電解メッキ用配線23bを形成
する。First, as shown in FIG. 3(a), similarly to the first embodiment, a dicing line region I is formed in which the silicon nitride film 22 is removed to expose the surface of the semiconductor substrate 21, and the silicon nitride film 22 is formed. An aluminum film is deposited on the entire surface of the element region. Next, unnecessary portions of the aluminum film are removed using the first photoresist pattern 24 formed in the desired thickness and shape as a mask, and the aluminum wiring 23a including the protruding electrode formation region 2 and the electrolytic plating wiring 23b are formed. Form.
次に第3図(b)に示すように、約5μmの厚さにポジ
型フォトレジストを塗布し、突起電極形成領域■及び接
続膜形成領域■内に所望の形状にパターニングした第2
のフォトレジストパターン25を形成する。Next, as shown in FIG. 3(b), a positive photoresist is coated to a thickness of approximately 5 μm and patterned into a desired shape within the protruding electrode formation region (■) and the connection film formation region (■).
A photoresist pattern 25 is formed.
次に第3図(c)のように、最終保護膜であるポリイミ
ド樹脂26を約10μmの厚さに塗布し、所望の厚さ及
び形状にバターニングした第3のフォトレジストパター
ン27をマスクにして、ダイシングライン領域Iのポリ
イミド樹脂26を除去する。Next, as shown in FIG. 3(c), a final protective film of polyimide resin 26 is applied to a thickness of approximately 10 μm, and a third photoresist pattern 27 patterned to the desired thickness and shape is used as a mask. Then, the polyimide resin 26 in the dicing line region I is removed.
次に第3図(d)のように、第3のフォトレジストパタ
ーン27を剥離した後、所望の厚さ及び形状に第4のフ
ォトレジストパターン28を形成し直し、それをマスク
にして第2のフォトレジストパターン25上の一部の領
域のポリイミド樹脂26をヒドラジン系の薬液でエツチ
ング除去する。ここで、ポジ型フォトレジストのヒドラ
ジン系薬液に対する溶解性を利用し、第2のフォトレジ
ストパターン25も同時にエツチング除去して突起電極
形成領域■のアルミニウム配線23aを露呈させる。Next, as shown in FIG. 3(d), after peeling off the third photoresist pattern 27, a fourth photoresist pattern 28 is re-formed to the desired thickness and shape, and this is used as a mask to form the second photoresist pattern. The polyimide resin 26 in a part of the photoresist pattern 25 is removed by etching with a hydrazine-based chemical solution. Here, by utilizing the solubility of the positive type photoresist in hydrazine-based chemical solution, the second photoresist pattern 25 is also removed by etching at the same time to expose the aluminum wiring 23a in the protruding electrode forming region (2).
次に第3図(e)のように、第4のフォトレジストパタ
ーン28を残したままメッキを成長させる際のバリア膜
となる金属膜29を基板表面に被着する。ここで金属膜
29は第1の実施例と同様に、チタン及び白金の2層膜
である。Next, as shown in FIG. 3(e), a metal film 29 is deposited on the substrate surface, leaving the fourth photoresist pattern 28 and serving as a barrier film when plating is grown. Here, the metal film 29 is a two-layer film of titanium and platinum, as in the first embodiment.
次に第3図(f)のように、第4のフォトレジストパタ
ーン28を剥離すると同時に不要部分の金属膜29をリ
フトオフ法、で除去したのち、400℃の窒素雰囲気中
で60分間熱処理を行い、突起電極形成領域■内にバリ
ア膜29aを、接続膜形成領域■内に接続膜29bを形
成する。Next, as shown in FIG. 3(f), at the same time as the fourth photoresist pattern 28 is peeled off, unnecessary portions of the metal film 29 are removed using a lift-off method, and then heat treatment is performed for 60 minutes in a nitrogen atmosphere at 400°C. , a barrier film 29a is formed in the protruding electrode forming region (2), and a connecting film 29b is formed in the connecting film forming region (2).
次に第3図(g>のように、基板全体を金メッキ液に浸
漬し、半導体基板21とメッキ装置側に設置された陽極
電極板との間に電流を流して全突起電極30a及び小金
突起電極30bが15〜30μmに形成されるまで電解
メッキを行う。Next, as shown in FIG. 3 (g>), the entire substrate is immersed in a gold plating solution, and a current is passed between the semiconductor substrate 21 and the anode electrode plate installed on the plating equipment side to remove all the protruding electrodes 30a and the small gold protrusions. Electrolytic plating is performed until the electrode 30b is formed to a thickness of 15 to 30 μm.
電解メッキ終了後、第1の実施例と同様にしてダイシン
グライン領域Iの電解メッキ用配線23bを全て除去し
、ダイシングライン領域Iとアルミニウム配線23aを
絶縁分離すれば、第3図(h)のように全突起電極30
a及び小金突起電極30bを有する半導体装置が完成す
る。After electrolytic plating is completed, all the electrolytic plating wiring 23b in the dicing line area I is removed in the same manner as in the first embodiment, and the dicing line area I and the aluminum wiring 23a are insulated and separated, resulting in the result shown in FIG. 3(h). All protruding electrodes 30
A semiconductor device having a metal protrusion electrode 30b and a metal protrusion electrode 30b is completed.
この第2の実施例においても最終保護膜をマスクとして
電解メッキを行っているため、全突起電極30aの表面
にエツチング残渣や異物の再付着等が発生することを防
止することができ、また最終保護膜であるポリイミド樹
脂26のオーバーハング状の断面形状により全突起電極
30aと半導体基板21との密着強度も十分に確保する
ことができる。In this second embodiment as well, electrolytic plating is performed using the final protective film as a mask, so that it is possible to prevent etching residues and foreign matter from re-adhering to the surface of all protruding electrodes 30a, and to Due to the overhanging cross-sectional shape of the polyimide resin 26 serving as the protective film, sufficient adhesion strength between the all-projecting electrodes 30a and the semiconductor substrate 21 can be ensured.
また、この第2の実施例では突起電極形成領域■内に形
成する第2のフォトレジストパターン25がポジ型であ
るため、ポリイミド樹脂26をパターン形成する際に、
ヒドラジン系の薬液で同時にエツチング除去することが
できるようになり、第4のフォトレジストパターン28
のみでエツチングのパターン形成とリフトオフ法による
バリア膜29aの形成が可能となった。さらに、電解メ
ッキ時に同時に形成された小金突起電極30bは、テー
プキャリアと半導体装置を圧着ボンディングする際に、
テープキャリアのリードが半導体装置のエツジ部と接触
することを防止する役割もはなすことができる。In addition, in this second embodiment, since the second photoresist pattern 25 formed in the protruding electrode formation region 2 is of a positive type, when patterning the polyimide resin 26,
It is now possible to simultaneously perform etching and removal using a hydrazine-based chemical solution, and the fourth photoresist pattern 28
It became possible to form the barrier film 29a by only etching pattern formation and lift-off method. Furthermore, the small gold protrusion electrode 30b formed at the same time as the electrolytic plating is used when bonding the tape carrier and the semiconductor device by pressure bonding.
It can also serve to prevent the leads of the tape carrier from coming into contact with the edges of the semiconductor device.
なお、上記実施例では突起電極の形成に金メッキを用い
た場合について説明したが、他の金属からなるメッキ法
により突起電極を形成してもよい
〔発明の効果〕
以上説明したように本発明は、半導体基板に形成した金
属膜をパターン形成して素子用配線及び電解メッキ用配
線を形成し、突起電極形成領域及び接続膜形成領域を露
出した保護膜を形成したのち、これらの領域にバリア膜
を形成し、突起電極形成領域のみあるいは突起電極形成
領域と接続膜形成領域に電解メッキ用配線を電流路とし
て電解メッキを行い、金属メッキ膜からなる突起電極を
形成し、しかる上で電解メッキ用配線を選択的に除去し
て、半導体装置に必要な配線と半導体基板との絶縁分離
を行うことにより、電解メッキ完了後は電解メッキ用配
線を除去するだけでよく、突起電極の形成工程は極めて
簡単なものとなる。さらに、突起電極形成以前に最終段
階の保護膜を形成しているため、突起電極表面部に保護
膜のエツチング残渣や異物の再付着等が発生することが
ないため、テープキャリヤのリードと突起電極間の密着
強度を十分に確保することができる。また、電解メッキ
の際のマスクとなる最終保護膜はオーバーハング状の断
面形状となっているので、突起電極と半導体基板の密着
強度を十分にかつ簡単に確保することができる。このた
め、突起電極を有する半導体装置を信頼性よく、かつ安
定的に製造することができる。In the above embodiments, the case where gold plating was used to form the protruding electrodes was explained, but the protruding electrodes may be formed by plating with other metals. [Effects of the Invention] As explained above, the present invention After patterning the metal film formed on the semiconductor substrate to form element wiring and electrolytic plating wiring, and forming a protective film exposing the protruding electrode formation area and connection film formation area, a barrier film is applied to these areas. Electrolytic plating is performed using the electrolytic plating wiring as a current path on only the protruding electrode forming area or on the protruding electrode forming area and the connecting film forming area, forming a protruding electrode made of a metal plating film, By selectively removing wiring and insulating and separating the wiring necessary for semiconductor devices from the semiconductor substrate, it is only necessary to remove the wiring for electrolytic plating after electrolytic plating is completed, and the process of forming protruding electrodes is extremely simple. It will be easy. Furthermore, since the final stage of the protective film is formed before forming the protruding electrodes, etching residue of the protective film or re-adhesion of foreign matter will not occur on the surface of the protruding electrodes. It is possible to ensure sufficient adhesion strength between the two. Further, since the final protective film, which serves as a mask during electrolytic plating, has an overhanging cross-sectional shape, sufficient adhesion strength between the protruding electrode and the semiconductor substrate can be ensured easily. Therefore, a semiconductor device having a protruding electrode can be manufactured reliably and stably.
第1図(a)〜(j)は本発明の第1の実施例を説明す
るための工程順に示した半導体チップの断面図、第2図
は第1の実施例の工程途中における平面図、第3図(a
)〜(h)は本発明の第2の実施例を説明するための工
程順に示した半導体チップの断面図である。
1・・・半導体基板、2・・・シリコン窒化膜、3・・
・アルミニウム膜、3a・・・アルミニウム配線、3b
・・・電解メッキ用配線、4・・・第1のフォトレジス
トパターン、5・・・シリコン酸化膜、6・・・第2の
フォトレジストパターン、7・・・金属膜、7a・・・
バリア膜、7b・・・接続膜、8・・・第3のフォトレ
ジストパターン、9・・・ポリイミド樹脂、10・・・
第4のフォトレジストパターン、11・・・金突起電極
、21・・・半導体基板、22・・・シリコン窒化膜、
23a・・・アルミニウム配線、23b・・・電解メッ
キ用配線、24・・・第1のフォトレジストパターン、
25・・・第2のフォトレジストパターン、26・・・
ポリイミド樹脂、27・・・第3のフォトレジストパタ
ーン、28・・・第4のフォトレジストパターン、29
・・・金属膜、29・・・バリア膜、29b・・・接続
膜、30a・・・金突起電極、30b・・・小金突起電
極。1(a) to (j) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention, FIG. 2 is a plan view of the first embodiment in the middle of the process, Figure 3 (a
) to (h) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a second embodiment of the present invention. 1... Semiconductor substrate, 2... Silicon nitride film, 3...
・Aluminum film, 3a...Aluminum wiring, 3b
... Wiring for electrolytic plating, 4... First photoresist pattern, 5... Silicon oxide film, 6... Second photoresist pattern, 7... Metal film, 7a...
Barrier film, 7b... Connection film, 8... Third photoresist pattern, 9... Polyimide resin, 10...
Fourth photoresist pattern, 11... Gold protrusion electrode, 21... Semiconductor substrate, 22... Silicon nitride film,
23a... Aluminum wiring, 23b... Electrolytic plating wiring, 24... First photoresist pattern,
25... second photoresist pattern, 26...
Polyimide resin, 27... Third photoresist pattern, 28... Fourth photoresist pattern, 29
...Metal film, 29...Barrier film, 29b...Connection film, 30a...Gold protrusion electrode, 30b...Small gold protrusion electrode.
Claims (1)
し、素子用配線及び電解メッキ用配線を形成する工程と
、全面に保護膜を形成した後パターニングし、前記素子
用配線の突起電極形成領域と前記素子用配線と電解メッ
キ用配線とを電気的に接続するための接続膜形成領域の
保護膜を除去する工程と、保護膜が除去された前記突起
電極形成領域および接続膜形成領域にバリア膜を形成す
る工程と、突起電極形成領域のこのバリア膜上に第1の
フォトレジストパターンを形成する工程と、全面に保護
膜を形成した後第2のフォトレジストパターンを用いて
パターニングし、前記第1のフォトレジストパターン上
部の一部を露出させる工程と、前記第2のフォトレジス
トパターンを除去すると同時に第1のフォトレジストパ
ターンも除去し前記バリア膜を露呈させる工程と、残さ
れた前記保護膜をマスクとした電解メッキにより露呈し
た前記バリア膜上に突起電極を形成する工程と、突起電
極形成後突起電極間の短絡を解除するために前記電解メ
ッキ用配線を選択的に除去する工程とを含むことを特徴
とする半導体装置の製造方法。A process of forming a metal film for wiring on a semiconductor substrate and then patterning it to form element wiring and electrolytic plating wiring, and forming a protective film on the entire surface and patterning it to form a protruding electrode formation area of the element wiring. a step of removing a protective film in a connection film forming area for electrically connecting the element wiring and the electrolytic plating wiring; and a step of removing a barrier film in the protruding electrode forming area and the connecting film forming area from which the protective film has been removed. a step of forming a first photoresist pattern on the barrier film in the protruding electrode formation region; a step of forming a protective film over the entire surface and then patterning it using a second photoresist pattern; a step of exposing a part of the upper part of the first photoresist pattern, a step of removing the first photoresist pattern at the same time as removing the second photoresist pattern to expose the barrier film, and a step of exposing the barrier film, and the remaining protective film. a step of forming a protruding electrode on the barrier film exposed by electrolytic plating using a mask as a mask, and a step of selectively removing the electrolytic plating wiring in order to release a short circuit between the protruding electrodes after forming the protruding electrode. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33966089A JPH03198342A (en) | 1989-12-26 | 1989-12-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33966089A JPH03198342A (en) | 1989-12-26 | 1989-12-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03198342A true JPH03198342A (en) | 1991-08-29 |
Family
ID=18329598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33966089A Pending JPH03198342A (en) | 1989-12-26 | 1989-12-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03198342A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06224200A (en) * | 1992-01-27 | 1994-08-12 | Gennum Corp | Integrated semiconductor device and method of forming bump structure on integrated semiconductor device |
| WO1998025297A1 (en) * | 1996-12-04 | 1998-06-11 | Seiko Epson Corporation | Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment |
| EP1231629A1 (en) * | 2001-02-07 | 2002-08-14 | STMicroelectronics S.r.l. | A method of forming metal connection elements in integrated circuits |
| US6518665B1 (en) * | 1997-07-11 | 2003-02-11 | Delaware Capital Formation, Inc. | Enhanced underfill adhesion |
| JP2005217445A (en) * | 1996-12-04 | 2005-08-11 | Seiko Epson Corp | Manufacturing method of semiconductor device |
| US7183189B2 (en) | 1996-12-04 | 2007-02-27 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
-
1989
- 1989-12-26 JP JP33966089A patent/JPH03198342A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06224200A (en) * | 1992-01-27 | 1994-08-12 | Gennum Corp | Integrated semiconductor device and method of forming bump structure on integrated semiconductor device |
| US7521796B2 (en) | 1996-12-04 | 2009-04-21 | Seiko Epson Corporation | Method of making the semiconductor device, circuit board, and electronic instrument |
| US7511362B2 (en) | 1996-12-04 | 2009-03-31 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US6475896B1 (en) | 1996-12-04 | 2002-11-05 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US8384213B2 (en) | 1996-12-04 | 2013-02-26 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| US8115284B2 (en) | 1996-12-04 | 2012-02-14 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument |
| US6730589B2 (en) | 1996-12-04 | 2004-05-04 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7888260B2 (en) | 1996-12-04 | 2011-02-15 | Seiko Epson Corporation | Method of making electronic device |
| US7470979B2 (en) | 1996-12-04 | 2008-12-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7183189B2 (en) | 1996-12-04 | 2007-02-27 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| US7049686B2 (en) | 1996-12-04 | 2006-05-23 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| JP2005217445A (en) * | 1996-12-04 | 2005-08-11 | Seiko Epson Corp | Manufacturing method of semiconductor device |
| WO1998025297A1 (en) * | 1996-12-04 | 1998-06-11 | Seiko Epson Corporation | Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment |
| US7842598B2 (en) | 1996-12-04 | 2010-11-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US6518665B1 (en) * | 1997-07-11 | 2003-02-11 | Delaware Capital Formation, Inc. | Enhanced underfill adhesion |
| EP1231629A1 (en) * | 2001-02-07 | 2002-08-14 | STMicroelectronics S.r.l. | A method of forming metal connection elements in integrated circuits |
| US6589816B2 (en) | 2001-02-07 | 2003-07-08 | Stmicroelectronics S.R.L. | Method of forming metal connection elements in integrated circuits |
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