JPH03187513A - Dynamic latch circuit - Google Patents

Abstract

PURPOSE:To eliminate limit on the design of a circuit by respectively inserting Pch (P channel) transistors between the respective source electrodes of two Pch transistors for feedback and a power source, and turning ON/OFF the transistors by two pairs of clocks. CONSTITUTION:Between Pch transistors 31 and 32 to feed back the Lo outputs of inverters 21 and 22 to an input terminal 5 and a power source 4, Pch transistors 51 and 52 are inserted to be respectively turned ON/OFF synchronously with the clocks. Since the added transistors 51 and 52 are the Pch transistors, they ate turned OFF when the data are read and two-phase clocks phi1 and phi2 are Hi. Then, when the data are read, the Pch transistors 31 and 32 are turned OFF without fail by the operations of the added Pch transistors 51 and 52. Therefore, it is not necessary to set the current supply ability of the Pch transistors 31 and 32 within a limited value and thus, the degree of freedom for the circuit design is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to improving the characteristics of a dynamic latch circuit.

[Conventional technology]

2 and 3 are circuit diagrams of a conventional dynamic latch circuit, and FIG. 4 is a waveform diagram of a two-phase clock 0102. In the figure, (11) and (12) are N-channel (hereinafter referred to as ch) transistors, (21) and (22) are inverters, and (31) and (32) are $11i! i! PC for
h transistor, (4) is the power line, (5> is the input terminal,
(6) is the output terminal (7) and (8) are two-phase clocks.
+21', , 02 do not overlap as shown in FIG.

Next, the operation will be explained. First, in the circuit shown in Figure 2, 2
When the phase clock (7) 01 is Hi, the Nch transistor (11) becomes conductive and supplies the data from the input terminal (5) to the inverter (21). Even when the inverter (2
1) is maintained by the parasitic capacitance of the input terminal. Next, when the two-phase clock (8) 02 becomes Hi, the Nch transistor (12) becomes conductive and supplies the output data of the inverter (21) to the inverter (22). 2-phase clock (8) 0
When the clock signal 2 becomes Lo, data is held according to the same principle as when the two-phase clock (7) $l is Lo.

However, in the circuit shown in Figure 2, the Hi data that has passed through the NCh transistor (It) or the inverter (21) is
The voltage decreases by the gate threshold voltage (VTH) of the h transistor (11) and inverter (21). Specifically, Hi
The voltage, which was 5 (v), drops to about 4 (v). For this reason, the input voltage of the inverters (21) and (22) does not become high enough, but the input voltage of the inverters (21) and (22) is very small.
) and (22).

The circuit to solve this problem is shown in Figure 3. When the outputs of the inverters (21) and (22) are Lo (the input is Hi), the PCh transistors (31) and (32) conduct and the inputs are brought to a Hi level. , specifically raised to almost 5(v),
The generation of the above-mentioned through current can be prevented. However, this circuit also has drawbacks as described below.

In Fig. 3, when the Pch transistor is ON, that is, the input of the inverter is Hi, if any of the Nch transistors conducts and inputs the LO voltage, the Pch transistor is ON, so the voltage is higher than that supplied by these transistors. It is necessary to extract the current through the NCh transistor. Therefore, the current value drawn through the Nch transistor (specifically drawn through the Nch transistor of the previous stage inverter) should be designed to be larger than the current supply capacity of the Pch transistor (specifically, the ratio of gate length and width). This poses a problem in that it is necessary and poses a major constraint on circuit design, and also poses a problem in high-speed data reading.

This invention was made in order to solve the above-mentioned problems, and the circuit shown in Fig. 3 is turned on with a two-phase clock of 01.
, add two new Pch transistors that turn OFF, and set the Pch transistors to 0FFL when reading data.
/ To ensure that reading operations can be performed reliably and at high speed. In other words, since the above added transistor is a Pch transistor, the two-phase clock is 0 when reading data.
When 102 is Hi, it is turned off.

(Means for Solving the Problems) The dynamic latch circuit according to the present invention is constructed by inserting two new Pch transistors between the source electrode of the $1in Pch transistor and the power supply of the circuit shown in FIG. p, , , +21', ON, 0FFL/.

(Function) When the dynamic latch circuit of the present invention is read, the conventional Pch transistor is always turned off due to the operation of the added Pch transistor.
There is no need to set the current supply capacity of the h transistor within a limit value (current extraction capacity of the preceding inverter), and the degree of freedom in circuit design increases.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 is a circuit diagram of a dynamic latch circuit.

In the figure (4) to (8), (11), (12), (2
1), (22), (31), and (32) are shown in Figures 2 and 3.
Since this is the same as that shown in the conventional example in the figure, the explanation will be omitted. (51) and (52> are PCh transistors.

Next, the operation will be explained.

First, when the two-phase clock (7) 0+ is Hi, the Nch transistor (11) reads data from the ONL/input terminal (5) into the inverter (21). At this time, since the two-phase clock (7) l + is Hi, the Pch transistor (5N) is OFF, so the Pch transistor (31)
Since the inverter (21) is also turned off, data can be easily read into the inverter (21) without being affected by the Pch transistor (31). Next, the two-phase clock (7) p't is Lo
When the Nchl-transistor (11) becomes 0FFL/,
Since data is no longer read from the input terminal (5) and the Pch transistor (51) is turned on, the Pch transistor (31) is turned on or off depending on the output state of the inverter (21). In other words, if the output of the inverter (21>) is LO, the PCh transistor (31) is ONL/A high level almost equal to the power supply voltage is supplied to the input terminal of the inverter (21), and there is no through current in the inverter (21>). Not flowing.

When the output of the inverter (21) is Hi, the Pch transistor (31) is 0FFt, and the LO level of human power is maintained as it is.

Next, when the two-phase clock (8) 02 becomes Hi, the Nch
Transistor (12) turns on and the above NCh transistor (11), inverter (21), and Pch transistor (3)
1) The same operation as (51) is performed using an NCh transistor (
12) Inverter (22) Pch transistor (32)
) (52) is performed.

(Effects of the Invention) As described above, according to the circuit configuration of the present invention, the Pch transistor that turns on and off in synchronization with the clock is inserted between the Pch transistor that feeds back the LO output of the inverter to the input terminal and the power supply. Data can be read into the inverter at high speed, and restrictions on pattern design for the feedback Pch transistor can be eliminated.

[Brief explanation of drawings]

FIG. 4, a circuit diagram of a conventional dynamic latch circuit, is a waveform diagram of the two-phase clock shown in FIG. 2. In the figure, (4) is the power supply line, (5) is the input terminal, and (6) is the input terminal.
) are output terminals, (7) and (8) are two-phase clocks, (11)
(12) is an Nch transistor, (21) (2
2) is an inverter, (31) (32) (51)
(52) is a PCh transistor. In the figures, the same symbols indicate the same or equivalent parts.

Claims (1)

[Claims] A latch with a configuration in which a plurality of N-channel transistors constituting a transmission gate and an inverter are connected in series, and a first P-channel transistor is added whose gate electrode is connected to the output of the inverter, the drain electrode is connected to the input, and the source electrode is connected to the power source. In the circuit, a second P-channel transistor is inserted between the source of the first P-channel transistor and a power supply, the drain of the second P-channel transistor is connected to the source of the first P-channel transistor, and the drain of the second P-channel transistor is connected to the source of the first P-channel transistor. A dynamic latch circuit characterized in that a source of a P-channel transistor is connected to a power supply, and a gate is connected to a gate of an N-channel transistor constituting the transmission gate.