JPH031734A - Clock slip detection circuit - Google Patents

Abstract

PURPOSE:To detect a clock slip accurately and quickly independently of a phase difference by using two clocks whose phases are different with a shift of 1/n period and detecting the rising transition of an external clock. CONSTITUTION:A phase conversion section 16 extracts two clocks whose phases are out of phase with 1/n period with respect to a reference internal clock being the operating standard. Leading detection sections 18, 19 use n sets of clocks to detect the rising shift of an external clock and when the rise of the external clock is detected between clocks whose phases differ by 1/n period, it is judged as clock slip and an alarm signal is outputted. Thus, even when no phase difference exists between the external clock and the internal clock, the clock slip is surely detected.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a clock slip detection method for detecting a slip in a clock source supplied from the outside and the operating clock of a communication system synchronized with the clock source, which can be performed accurately and quickly regardless of the phase difference. The purpose is to provide a clock slip detection circuit that can detect clock slips, and includes a phase converter that extracts n clocks with different phases, a phase converter that extracts n clocks with different phases, and detects the rise transition of an external clock using the n clocks. The apparatus is configured to include a rising edge detecting section that determines that a rising edge of an external clock is detected between clocks having a phase shift of 1/n cycle and outputs an alarm signal.

[Field of Industrial Application] The present invention relates to a clock slip detection circuit for detecting a slip in an operating clock of a communication system synchronized with an externally supplied clock source.

A communication system requires a reference clock as a communication network in order to perform synchronized communication.

For this reason, each communication terminal draws in a clock from the outside. In recent years, with the demand for higher reliability in each process of each communication system, there has been a demand for duplication of clock sources that serve as operating standards. Due to this duplication, even if an abnormality occurs in the reference clock for some reason than in the past, by supplying a clock from another clock source that is synchronized with the reference clock, early detection of the abnormality and maintenance can lead to system downtime. etc. can be avoided, resulting in higher reliability.

Therefore, clock sources are currently being duplicated, such as mutually supplying clock sources between a plurality of systems. However, the clock phases may differ between communication systems, making it impossible to simply detect a slip. Therefore, it is necessary to enable slip detection of clocks with different phases.

[Prior Art] FIG. 4 shows a conventional configuration diagram for detecting a slip of clocks having different phases. Further, a time chart for the above configuration is shown in FIG. In the conventional method, a reference clock for internal operation and an external clock supplied from the outside are extracted to detect a slip. The conventional method will be explained below with reference to the drawings.

Simply put, the conventional method detects a clock slip by detecting whether there is a rising edge of an externally supplied clock between rising edges of the operating clock of the own system.

The conventional slip detection circuit consists of three columns of Phillips-flops (
(hereinafter abbreviated as FF), a rising differential circuit 41, and a NAND circuit 45. (2) is an external clock, (2) is a signal after the external clock rises and passes through the differentiation circuit 41, (2) is an output signal from the Q terminal of the FF 42,
(2) is an output signal from the Q terminal of the FF 43, (2) is a signal as a result of detection of the rising edge of the internal clock, (2) is an output from the Q terminal of the FF 44, and (2) is an output signal of the NAND circuit 45, which is also an alarm control signal. ■ is an initial false alarm prevention signal.

In addition, the signal ■ is the rising edge detection signal ■ of the internal clock, which is set and reset at the falling edge of the signal ■ extracted from the external clock, and the signal ■ is the internal clock rising detection signal ■, which is reset at the fall of the signal ■ extracted from the external clock. The signal (2) detects continuous setting (the set signal is input before the FF 42 is set and is not reset).

■ indicates the rising clock of the internal clock.

That is, in the conventional method, when it is detected that the FF 42 is successively set or reset by an internal clock or an external clock, this is regarded as a slip detection and an alarm signal is output.

[Problem to be Solved by the Invention] The conventional slip detection circuit described above operates normally if there is a phase difference between the external clock and the internal clock in the initial state of clock slip detection. If there is no slippage at all, an alarm may be issued even though there is no slippage. This is because if there is no phase difference at all, the set and reset signals are simultaneously applied to the FF 42, thereby preventing normal operation. This has caused a problem in that the reliability in operating the communication system is significantly reduced.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a clock slip detection circuit that can accurately and quickly detect clock slips regardless of the phase difference.

[Means to solve the problem]

FIG. 1 shows the principle configuration and system configuration diagram of the present invention.

In the figure, reference numerals 18 and 19 indicate a rising edge detection section that detects the rising transition of each external clock using multiple clocks with different phases extracted from the operating reference internal clock, and 16 indicates a rising phase n that is shifted by 1/n period from the operating reference internal clock.
This is a phase converter that extracts the clocks.

In order to achieve the above object, the present invention extracts n clocks having different phases by shifting l/n cycles from the reference clock, detects the rise transition of the external clock using each of the n clocks, and detects each clock. The configuration is such that a case where a rising transition is detected in the clock is regarded as a clock slip.

(Function) In the present invention, the rising edge of the external clock is detected in multiple clocks extracted by the phase converter.Furthermore, if a rising edge is not detected in the multiple clocks extracted by the internal clock, it is not considered as a slip. Therefore, even if the internal clock and the external clock are in the same phase, erroneous detection of slip will not occur.

[Embodiment] FIG. 2 shows a configuration diagram of an embodiment of the present invention. In this figure, four clocks are extracted by shifting the phase by 1/4 period in the phase conversion section, and the rising edge of the external clock is detected.

Therefore, there are 4 phillip flops connected in series.
There are two. If 10 clocks are extracted, there will be 10 groups of three series-connected flip-flops.

Further, FIG. 3 shows a timing chart of this embodiment.

The symbols assigned to each input/output in FIG. 2 correspond to those in FIG. 3. The present invention will be described in detail below with reference to the drawings.

The feature of this embodiment is that four clocks having different phases are extracted from the clock used for internal reference operation. In this case, the phase difference between each clock is 1/4 period. (Illustration, g.

1, q) The next feature is that the rise transition of the external clock is detected using each of the four clocks.

Here, the rising transition is detected by determining whether or not there is a rising edge of the external clock between the rising edge of a certain clock and the rising edge of the next clock (a clock whose phase is delayed by 1/4 cycle).

The AND circuits 25 to 28 in FIG.
This detects whether or not there is a rising edge of the external clock between the rising edges of the two clocks. For example, as shown in time ~L2, when the external clock a has not risen when the human clock b to the FF 21 rises, the calculation power of the FF 21 becomes 'tli', and in the next OF F22, the human clock g rises. Since the external clock is rising at this time, the Q output of the FF 22 is 'Ili'. Therefore, the AND circuit 25 detects that there is a rising edge of the external clock between the two input clocks, and outputs "old °'". If the external clock, clock or internal clock does not slip, the output of only one of the four AND circuits 25 to 28 will be "old".
°, and other AND circuits will not have the "old" output. In the embodiment, the time t is reached by the start of rising detection.

Then, the AND circuit 28 becomes °'tli''' and the clock g
This is a state in which the external clock rises between the rises of the clock signal B, and the signal U is at a low level.

When the AND circuits 25 to 28 output "' tl i ", that is, the rising edge of the external clock or internal clock changes, and the AND circuits output "11'" one after another, the input clock to each FF group causes the FF 29 ~32
'1 (i'''' output is held at FF37-40 until the reset signal is input. This means that FF37-40 is 'Ili' output.
i'" output, the Q terminal output of the self FF is fed back to the D terminal of the self FF via exclusive OR, so when the output of the Q terminal of the self FF becomes 'Ili", the reset input It will be retained until the end.

In this way, the rising edge of the external clock is detected, and each FF3
By holding the tli'' output at the Q terminals 7 to 40, an alarm signal W is generated, and a clock slip is detected.

In this embodiment, four clocks whose phases are shifted by 1/4 period are used, and the detection of a rising edge of an external clock between each clock is defined as a clock slip. but,
For example, it is also possible to use 10 clocks whose phases are shifted by 1/10 period, and when a rising edge of the external clock is detected in 5 of them, a clock slip occurs. In that case, the structure can be easily configured by outputting the third stage OFF of each FF group via a logic circuit. Although such a configuration has a more complicated circuit configuration than the optical embodiment, it has the advantage of being able to quickly detect clock slips.

〔Effect of the invention 〕

According to the present invention, clock slips can be reliably detected even when there is no phase difference between the external clock and the internal clock. Furthermore, if the case where the rising edge of the external clock is detected in some of the plural clocks is defined as slip detection, detection can be made more quickly.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle of the present invention; Fig. 2 is an embodiment of the rise detection section of the present invention; Fig. 3 is a time chart in the embodiment; Fig. 4 is a block diagram of a conventional rise detection section; FIG. 5 is a conventional time chart. In the figure, 12, 13, 16, 18°, clock selection section, PLL circuit, phase conversion section 9...rise detection section

Claims (2)

[Claims] (1) A plurality of clocks are supplied from the outside, one of the plurality of clocks is selected by a clock selection section (12), and P
In a clock slip detection circuit that detects the rise transition of the external clock using the reference clock in a mutually synchronous communication system that extracts and starts the internal operating reference clock via the LL circuit (13), a phase converter (16) that extracts n clocks having different phases by shifting the phase by 1/n period from the reference clock; A clock slip detection circuit comprising a rising edge detection section (18, 19) that determines a clock slip when a rising edge of an external clock is detected between clocks with a phase shift and outputs an alarm signal. (2) Rising detection section (18 to 19) according to claim 1
However, when detecting the rising edge of the external clock between clocks whose phase is shifted by 1/n period, the rising edge of the external clock is detected between m (<n) clocks out of n clocks. A clock slip detection circuit is characterized in that it determines that there is a clock slip and outputs an alarm signal when the clock slip occurs.