JPH031782A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To attain excellent display with simple constitution by providing a shift register and a sample-and-hold circuit to apply sample and hold to a video signal at each phase thereby supplying the result to a switching element. CONSTITUTION:Two sets of shift registers 2a, 2b used for sampling an input signal are provided to supply a signal to alternate vertical signal lines independently and the shift registers are driven in a different phase and the input signal is sampled and held independently at each phase at sample-and-hold circuits 5a, 5b to supply them to the alternate vertical signal lines independently. Thus, video signal is sampled and held at each phase and fed to a switching element thereby giving a margin to the timing of a pulse signal driving the switching element and excellent display is implemented with simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal display device that displays images by arranging, for example, liquid crystal display elements in an X-Y matrix.

[Summary of the invention]

The present invention relates to a liquid crystal display device, in which HII is provided with shift registers used for sampling input signals, signals are independently supplied to alternate vertical signal lines, and two sets of shift registers are driven in different phases. By independently sampling and holding the input signal at each phase and supplying it to alternate vertical signal lines independently, the video signal can be displayed satisfactorily.

[Prior art] For example, it has been proposed to display television images using a liquid crystal (
(See Japanese Patent Laid-Open No. 59-220793, etc.).

That is, in FIG. 3, (1) is an input terminal to which a television video signal is supplied, and the signals from this input terminal (1) are transmitted to switching elements M, , M, . . . are supplied to lines L, , L2 . . . Lm in the vertical (Y-axis) direction.

Note that m is a number corresponding to the number of pixels in the horizontal (X-axis) direction. Furthermore, an m-stage shift register (2) is provided, and a horizontal start signal H8 corresponding to a horizontal synchronization signal and a horizontal clock signal Φ8 of m times the horizontal frequency are supplied to this shift register (2). ) is supplied to each control terminal of the switching elements M1 to Mn+. Note that the shift register (2) has a low potential (VSS) and a high potential (VSS).
an) is supplied, and drive pulses of these two potentials are formed.

Furthermore, each line Ll-Lm has a switching element M+11M2. composed of, for example, an N-channel FET.・・・
・MIIIM1□9M2□...M,,□,...M
j+1+ Mzm...One end of Mnm is connected.

Note that n is a number corresponding to the number of horizontal scanning lines. The other ends of these switching elements M, ~Mnm are respectively liquid crystal cells CI
l+ C21...Target terminal (
3).

Furthermore, an n-stage shift register (4) is provided, and a vertical start signal (corresponding to a vertical synchronization signal) and a vertical clock signal Φ9 of a horizontal frequency are supplied to this shift register (4). Drive pulse signals φ, 1 . φv2...φVn connect switching elements M l (~Mnm to each column (M+r~) in the X-axis direction through gate lines G, , C, 2...
M,, ), (Ml, -Ml,) ・--(M0~Mn
m) are respectively supplied to the control terminals. Note that the shift register (4) also has V
SS and ■I. is supplied.

That is, in this circuit, the shift register (2).

(4) is a start signal H5 as shown in Fig. 4A and B.
゜■, and clock signals Φi and Φ9 are supplied. The shift register (2) outputs φH1 to φ for each pixel period as shown in FIG.
4), as shown in the same figure, φMl is calculated for each horizontal period.
~φ□ is output. Furthermore, the input terminal (1) is
A signal as shown in is supplied.

When φ9゜φH1 is output, switching elements M, Ml, ~M0 are turned on, and the input terminal (]
) -M, -L, -M, , -C, , -The current path of the target terminal (3) is formed and the liquid crystal cell C11
The signal supplied to the input terminal (1) and the target terminal (
3) is supplied. Therefore, this cell CI+
Charge corresponding to the potential difference due to the signal of the first pixel is sampled and held in the capacity. The light transmittance of the liquid crystal is changed corresponding to this electric current of 1 m. The same process is performed sequentially for cells CI2 to Cnrn, and when the next field signal is supplied, each cell CIl to Cn
The amount of charge of m is rewritten.

In this way, the light transmittance of the liquid crystal cell C+'+'''Cnm is changed corresponding to each pixel of the video signal, and this is sequentially repeated to display a television image.

Furthermore, when displaying on a liquid crystal, -a includes its reliability,
AC drive is used to extend life. For example, in displaying a television image, a signal obtained by inverting the video signal is supplied to the input terminal (1) every 1 field or every frame. In addition, in liquid crystal display devices, the signal is
Reversal is performed every horizontal period. That is, as shown in FIG. 4, the input terminal (1) is supplied with a signal that is inverted every horizontal period and also every 1 field or frame.

[Problem to be solved by the invention]

However, in the above-described apparatus, when the number of pixels in the horizontal direction is increased for the purpose of improving image quality, the operating speed of the shift register (2) increases because the length of the horizontal period is constant. Therefore, there was a risk that the configuration of the shift register (2) would become complicated and power consumption would increase.

In response to this, a device as shown in FIG. 5 was proposed. In other words, in the figure, there are two sets of shift registers (2) ((2a
) (2b) ) The control terminals of every other switching element M+, M3...M6-3 are connected to each output terminal of one shift register (2a), and the remaining switching element Mt1Ma ...The control terminal of Mm is connected to each output terminal of the other shift register (2b). Then, the shift register (2a) is supplied with the conventional horizontal clock signal Φa□ having a frequency of
is supplied.

Therefore, in this device, the shift register (2a) (2
b) is a horizontal clock signal Φ as shown in FIG. 6A, B.
mH+Φ,H is supplied. As a result, each output terminal of the shift registers (2a) (2b) receives drive pulse signals φHI+φH3 as shown in C and D in the same figure.
and φH2+φ□4... are output. Note that drive pulse signals are sequentially generated from the shift registers (2a) and (2b) each time the clock signal is inverted, and when the switching element is turned on during this period, effective sampling is performed in the latter half of the pulse signal. The figure shows effective sampling pulses for this purpose. These drive pulse signals φ□, φH3... and φ
)+2. φ6, 4... are switching elements Ml.

For example, as shown in the figure, the input signal is sampled by being supplied to M3, Mt, Ma, and so on, and is supplied to each signal line L, L, and so on. Ru.

According to this device, the shift register (2a
) The frequency of the clock signal supplied to (2b) can be lowered to (2), a shift register with a simple configuration can be used, and power consumption can also be reduced. Alternatively, when the clock signal frequency is the same, the number of pixels in the horizontal direction can be doubled.

However, in the above device, the shift register (2
a) Clock signals ΦmH and Φ supplied to (2b)
, H, the pulse signal φ output from the shift register (2a) (2b)
The timings of □ to φ may be shifted, and pulse signals may be generated overlapping each other, or the front and back may be reversed. When such a shift occurs, for example, a vertical line with a width of one pixel may disappear or be displayed as a double line.

For this reason, strictness is required in the formation of the clock signal, making it difficult to manufacture the device.

This application was filed in view of these points.

[Means to solve the problem]

The present invention provides a plurality of first signal lines G, . G.

. . . Gn are provided, and these first . A selection element M11. is provided at each intersection of the second signal line. MB...Mnm
In a liquid crystal display device including liquid crystal cells ClllCl□...Cnm, a first shift register (2a
) and a second shift register (2b) corresponding to the remaining first signal line, and the first and second shift registers are driven at mutually different phases (clock signal ΦaN+Φb11). together with the input signal (terminal (
1)) in the first phase (circuit (5)
a)) is the output signal of the first shift register (drive pulse signal φ1..φ3...φH, -1)
Sampling at (switching element M+ 1M3...
...M, -,) is supplied to every other first signal line, and a signal obtained by sampling and holding the input signal at the second phase (circuit (5b)) is sent to the second shift register. Output signal (drive pulse signal φ) lZ+ Hl(
4...φHj (switching elements M, , M4...Mm) and is supplied to the remaining first signal line.

[Effect]

According to this, by sampling and holding the video signal at each phase and supplying it to the switching element, it is possible to provide margin in the timing of the pulse signal that drives the switching element, and a good display can be achieved with a simple configuration. It can be performed.

〔Example〕

In FIG. 1, a video signal supplied to an input terminal (1) is supplied to sampling and holding circuits (5a) and (5b). In addition, these sampling and hold circuits (5a
) (5b) includes the shift register (2a) (
2b) horizontal clock signal Φ0. In relation to Φ, □, sampling pulses Φ□1' and Φ,' are supplied, respectively, at timings that are advanced by a period of time relative to the respective inversion timings. Then, the signal sampled and held by the sampling and holding circuit (5a) is sent to the switching elements M, , M.

. . . A signal is supplied to switching element M2. M4... is supplied to Mm. The rest is the same as the device described in the above-mentioned subject.

Therefore, in this device, the shift register (2a) (2
b) A horizontal clock signal Φ0 as shown in FIG. 2A and B
．． ΦbH is supplied, and drive pulse signals φ□, φl (3... and φH2+ φ1, 4 as shown in CD in the figure) are supplied.
... is output, the input signal as shown in the same figure, for example, is sent to the sampling and hold circuit (5a).
(5b) and are sampled and held as shown in FIG.

. . and the signals in the shaded portions are sampled and supplied to the signal lines L+, Lz . . . .

In this device, the drive pulse signals φ□, φ□2 and φ□2 are sampled and held by input signals.
Even if the timing of ... is slightly shifted, an incorrect signal will not be sampled, the requirement for strictness of the clock signal, etc. is reduced, and the manufacturing of the device can be easily performed.

In this way, according to this device, by sampling and holding the video signal at each phase and supplying it to the switching element, it is possible to provide a margin in the timing of the pulse signal that drives the switching element, and the configuration is simple and good. It is possible to perform a display.

In addition, in the above-mentioned device, the switching elements M1 to Mra
The following configuration is not limited to the case where the sampled signal used in the above explanation is directly supplied to the signal lines L, ~Lrm, but the sampled signal is once held and then
It can also be applied to a configuration in which each horizontal line is supplied to the signal lines L, =Lm.

Further, the signals from the sampling and holding circuits (5a) and (5b) may have polarities inverted from each other.

Further, the number of shift registers and sampling hold circuits is not limited to two, but three or more sets may be provided.

[Effects of the Invention] According to the present invention, by sampling and holding the video signal at each phase and supplying it to the switching element, it is possible to provide a margin for the timing of the pulse signal that drives the switching element, and it is possible to easily It is now possible to perform good display with this configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of the present invention, FIG. 2 is a diagram for explaining the same, and FIGS. 3 to 6 are diagrams for explaining a conventional apparatus. L, ~Lm are vertical signal lines, G, ~G7 are gate lines, M1
1 to Mnm, Ml to Mm are switching elements, C+
+ ~Cnm is the liquid crystal cell, (1) is the input terminal, (2a)
(2b) (4) is a shift register, (5a) (5b
) is a sampling and holding circuit. Agent Hidemori Matsukuma! −−−−−−−−− Figure 4

Claims (1)

[Claims] A plurality of first signal lines arranged in parallel in the vertical direction and a plurality of second signal lines arranged in parallel in the horizontal direction are provided, and these first, In a liquid crystal display device in which a liquid crystal cell is provided at each intersection of second signal lines via a selection element, a first shift register corresponding to every other first signal line; and a first shift register corresponding to every other first signal line; A second shift register corresponding to the first signal line is provided, and the first and second shift registers are driven at mutually different phases, and a signal obtained by sampling and holding the input signal at the first phase is provided. The output signal of the first shift register is sampled and supplied to every other first signal line, and the signal obtained by sampling and holding the input signal at the second phase is output from the second shift register. A liquid crystal display device characterized in that a signal is sampled and supplied to the remaining first signal line.