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JPH03163810A - Laminated ceramic capacitor and manufacture thereof - Google Patents

Laminated ceramic capacitor and manufacture thereof

Info

Publication number
JPH03163810A
JPH03163810A JP30403989A JP30403989A JPH03163810A JP H03163810 A JPH03163810 A JP H03163810A JP 30403989 A JP30403989 A JP 30403989A JP 30403989 A JP30403989 A JP 30403989A JP H03163810 A JPH03163810 A JP H03163810A
Authority
JP
Japan
Prior art keywords
notch
shape
memory alloy
alloy
shape memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30403989A
Other languages
Japanese (ja)
Inventor
Naozo Hasegawa
長谷川 直三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP30403989A priority Critical patent/JPH03163810A/en
Publication of JPH03163810A publication Critical patent/JPH03163810A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0263High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Landscapes

  • Ceramic Capacitors (AREA)

Abstract

PURPOSE:To produce an electrically open state when short failure is generated, and prevent burnout, by arranging shape memory alloy set in a notch which alloy has almost the same shape as the notch at a normal temperature, and largely changes the shape at a temperature higher than or equal to about 300 deg.C. CONSTITUTION:In a notch 4, a nickel-titanium based or stainless based shape memory alloy 5 is set and bonded as shown in figure (a). Said alloy has almost the same shape as the notch at a normal temperature, and are not deform by heating at the time of mounting. Said alloy is made to store a shape which bends up to nearly right angle in the center as shown in figure (b), at a temperature higher than or equal to about 300 deg.C. When short is generated after the alloy is mounted on a board 8, a ceramic body is heated by the generated heat due to excess current, the shape memory alloy 5 changes the shape and pushed up a capacitor element 3 from the board 8, and the ceramic body is completely divided from the notch 4. Thereby an electrical open state is produced, and the damage of a laminated layer ceramic capacitor and the bournout of adjacent electronic parts and, further, of a printed board can be prevented.

Description

【発明の詳細な説明】 r#業1−.の利用分野〕 木発明は積層セラミックコンデンサおよひその製造方法
に関し、特に本部品が短絡不良となった場合に本体を破
壊せしめ電流を遮断する構造を有する積層セラミックコ
ンデンサおよびその製造方法に関する。
[Detailed Description of the Invention] r# Business 1-. Field of Application] The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same, and more particularly to a multilayer ceramic capacitor having a structure that destroys the main body and interrupts current when the component is short-circuited, and a method for manufacturing the same.

〔従来の技術〕[Conventional technology]

従来、積層セラミックコンデンサは第6図に示すように
誘電体セラミックシ一ト上に内部電極11を印刷した後
所望の枚数を積み重ね両端に内部電極11が交互に露出
するように切断し、焼戊することにより一体化させ、次
に、内部電極11が露出した両端面において電気的に接
続させて外部電極12を形成ずることにより得^れる「
発明が解決しようとする課題〕 上述した従来の積層セラミックコンデンサは外部電棒1
2として一般的に銀等を主成分とする金属粉末とガラス
フリッ1〜才3よびセラミックとジ)結罰を良くするた
めの物質からなるベースl・を内部電極11の露出した
端面およびその隣接面の一部に付与し焼きつCつでいる
ことにより体積効率良く小型化されたllI1逍とな−
)でいる、しかしなから最近の積層セラミックコンデン
サ等のチップ形の電子部品は、プリン1〜基板上に多数
の電子部品が実装されるため、それぞれの電子部品に高
信頼度性が要求されるようになってきている。特にショ
ー1・不良については積層セラミック=1ンデン“り゛
にJ3い゛(は−II ;+;?に−斤,ではあるがも
し発生した場合はその電子部品が不良となるばかりでな
く、そのプリント基板全体をも不良にし、延いては焼損
という大事故に至るおそれがあるという重大な欠点があ
った。
Conventionally, multilayer ceramic capacitors are manufactured by printing internal electrodes 11 on a dielectric ceramic sheet, stacking the desired number of sheets as shown in FIG. The internal electrodes 11 are then integrated by forming the external electrodes 12 by electrically connecting them at both end surfaces where they are exposed.
Problems to be Solved by the Invention] The conventional multilayer ceramic capacitor described above has an external electric rod 1.
2) A base 1 made of a metal powder whose main component is generally silver, etc., a glass frit 1 to 3, and a ceramic material and a substance for improving consolidation. By attaching heat to a part of the material and making it compact, it can be miniaturized with volume efficiency.
) However, recent chip-shaped electronic components such as multilayer ceramic capacitors have a large number of electronic components mounted on a printed circuit board, so each electronic component is required to have high reliability. It's starting to look like this. In particular, as for the defect in Show 1, the multilayer ceramic = 1 den "J3"(Ha-II; This had a serious drawback in that it could cause the entire printed circuit board to become defective, leading to a serious accident such as burnout.

本発明の目的は、従来の積層セラミックコンデンサの体
積効率の良い構造を維持しながら目.−)、もしもショ
ート不良が発生した場合にでも電気的にオープン状態を
作り出し、焼損させないという機能を有した椙造を持つ
積層セラミックコンデンサを提供することにある。
It is an object of the present invention to maintain the volumetrically efficient structure of conventional multilayer ceramic capacitors while reducing the volumetric efficiency. -) It is an object of the present invention to provide a multilayer ceramic capacitor having a structure having a function of creating an electrically open state and preventing burnout even if a short-circuit failure occurs.

「課題を解決するための手段〕 本発明の第1の発明の積層セラミックコンデンサは、請
電体セラミックシー1〜を介して相対ずる内部電棒層を
交万に積層・埋設し両端に内部電棒が交互に露出するよ
う切断し焼結させて一体化し、しかる後に電極取り出し
用の外部電極2を付設してなる積層セラミックコンデン
サにおいて、前記コンデンサ素子の表面のほぼ中央部の
電極の黒い部分に外部電極とほぼ平行に設りられた切れ
込みと、その切れ込みにはめ込まれた常温ではその切れ
込みとほぼ同一形状を有し、かつ約300℃以上では大
きく変形する特性を有ずる形状記憶合金とを有すること
を特徴として構成される。
``Means for Solving the Problems'' The multilayer ceramic capacitor of the first aspect of the present invention has inner electrode layers alternately laminated and buried opposite each other via the power receiving body ceramic seam 1 to In a multilayer ceramic capacitor in which external electrodes 2 are cut and sintered so as to be exposed alternately and then integrated, and external electrodes 2 for taking out the electrodes are attached thereto, the external electrodes are placed in the black part of the electrodes approximately in the center of the surface of the capacitor element. and a shape memory alloy fitted into the notch that has almost the same shape as the notch at room temperature and has the property of deforming significantly at temperatures above about 300°C. Constructed as a feature.

なお、切れ込みの断面0形状を鋭角とり−ることにより
本発明を効果的に実施することができる。
Note that the present invention can be effectively carried out by making the cross-sectional shape of the cut an acute angle.

また、本発明の第2の発明の積層セラミックコンデンサ
の製造方法は、コンデンザの表面のほぼ中央部の電極の
無い部分に外部電極とほぼ平行に切れ込みを形成する工
程と、前記切れ込みに常温では切れ込みとほぼ同一形状
を存し、がっ30o℃以上では大きく変形する特性を有
する形状記憶合金をはめ込む工程とを含むことを特徴と
して構成される。
Further, the method for manufacturing a multilayer ceramic capacitor according to the second aspect of the present invention includes the steps of forming a notch substantially parallel to the external electrode in a portion of the surface of the capacitor where there is no electrode at approximately the center; The structure is characterized in that it includes a step of fitting a shape memory alloy having substantially the same shape as the shape memory alloy, which has the property of deforming significantly at temperatures of 30° C. or higher.

〔実施例〕〔Example〕

次に、本発明について図面を参照にして説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a).(Ll)は本発明の−・実胞例の斜視図
および断面図、第2図(a)〜((1)は本発明の製造
方法を説゛明するために工程順に示した断面図および斜
視図であり、また第3図(a)(b)は本発明に使川す
る部品の形状記憶合含の5 常温および300℃以上の形状を示す斜視図である。
Figure 1(a). (Ll) is a perspective view and a cross-sectional view of an actual cell example of the present invention, and Figures 2 (a) to (1) are cross-sectional views and FIGS. 3(a) and 3(b) are perspective views showing the shapes of parts used in the present invention, including shape memory, at room temperature and at 300° C. or higher.

積層セラミックコンデンサの製造方法としては、まず微
細化したセラミ・ツク粉末と有機バインダを混練した後
ドクターブレード法によって生シートを作成しその表面
にスクリーン印刷により内部電極1を作成した後、所望
の枚数を積み重ね、熱圧着することにより第2図(a)
に示すような内部電極1を交互にずらした状態の積層体
6を形成する。
The method for manufacturing a multilayer ceramic capacitor is to first knead finely divided ceramic powder and an organic binder, then create a green sheet using the doctor blade method, create internal electrodes 1 on its surface by screen printing, and then print the desired number of sheets. Figure 2 (a)
A laminate 6 is formed in which internal electrodes 1 are alternately shifted as shown in FIG.

次に、第2図(b)に示すように積層体6を水平移動さ
せながら上下移動する回転切断刃21にて切断位置22
のほぼ中央部の切れ込み位置41の表面に切れ込みを形
成しながら順次切断した後焼成することにより第2図(
c)に示すような焼或体7が得られる。ここで、従来と
同じく銀を主或分とする金属粉末とガラスフリットおよ
びセラミックとの結合を良くするための物質からなるペ
ーストをこの焼成体7の両端面に付設し焼付けることに
より第2図(d)に示すような表面のほぼ6 中央部に切れ込み4を有するセラミックコンデンサ素子
3が得られる。
Next, as shown in FIG. 2(b), the rotary cutting blade 21, which moves vertically while horizontally moving the stacked body 6, cuts to a cutting position 22.
Figure 2 (
A fired body 7 as shown in c) is obtained. Here, as in the conventional case, a paste made of a substance for improving the bond between the metal powder mainly containing silver, the glass frit, and the ceramic is attached to both end surfaces of this fired body 7 and baked. A ceramic capacitor element 3 having a notch 4 approximately at the center of its surface as shown in FIG. 3(d) is obtained.

さらにこの切れ込み4に、第3図(a)に示すような常
温ではその形状とほぼ同一形状を有し実装時の加熱では
変形せず、かつ約3 0 0 ’C以上では第3図(b
)に示すように真ん中でおおよそ直角まで曲がるような
形状を記憶させたニッケルチタン系またはステンレス系
の形状記憶合金5をはめこみ接着させることにより、第
1図(a〉,(b)に示すような本発明の積層セラミッ
クコンデンサ素子3が得られる。
Furthermore, this notch 4 has almost the same shape at room temperature as shown in FIG.
) As shown in Figures 1(a) and 1(b), by fitting and bonding a nickel-titanium or stainless steel shape memory alloy 5 that memorizes the shape of bending to an approximately right angle in the middle, the shape shown in Figures 1(a) and (b) A multilayer ceramic capacitor element 3 of the present invention is obtained.

次に、本発明の作用について第5図(a),(b)を用
いて説明する。まず、第5図(a)に示すように、積層
セラミックコンデンサ素子3の表面のほぼ中央部の切れ
込み4に形状記憶合金5がはめ込まれており、基板8に
実装された後、もしショートが発生した場合、過電流に
よる発熱のためセラミック素体が加熱され、形状記憶合
金5が変形し、コンデンサ素子3を基板から押し上げ、
切れ込み4よりセラミック素体を完全に分断7 してしまうことにより電気的にオープン状態を作り出し
、積層セラミックコンデンサの損傷および付近の電子部
品、延てはプリント基板を焼損させることを防止するこ
とができる。
Next, the operation of the present invention will be explained using FIGS. 5(a) and 5(b). First, as shown in FIG. 5(a), a shape memory alloy 5 is fitted into a notch 4 at approximately the center of the surface of the multilayer ceramic capacitor element 3, and after it is mounted on a substrate 8, if a short circuit occurs. In this case, the ceramic element is heated due to heat generated by the overcurrent, the shape memory alloy 5 is deformed, and the capacitor element 3 is pushed up from the substrate.
By completely dividing the ceramic body through the notch 4, an electrically open state is created, which prevents damage to the multilayer ceramic capacitor and burnout of nearby electronic components and even the printed circuit board. .

第4図(a),(b’)は本発明の他の実施例に使用す
る形状記憶合金の斜視図で、第4図(a)は常温におけ
る形状、第4図(b)は300℃以上での形状を示して
いる。工法は概ね第1の実施例と同様であるが切れ込み
4にねじれの特性を記憶した形状記憶合金51を挿入し
たもので、熱による変位力をさらに大きくし確実に効果
を発揮するという利点がある。
Figures 4(a) and (b') are perspective views of shape memory alloys used in other embodiments of the present invention; Figure 4(a) is the shape at room temperature, and Figure 4(b) is the shape at 300°C. The shape shown above is shown. The construction method is generally the same as the first embodiment, but a shape memory alloy 51 that memorizes the torsion characteristics is inserted into the notch 4, which has the advantage of further increasing the displacement force due to heat and ensuring the effect is exerted. .

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、積層セラミックコ
ンデンサ素子表面のほぼ中央部の切れ込みに形状記憶合
金がはめ込まれており、基板へ実装された後、もしショ
ートが発生した場合、過電流による発熱のためセラミッ
ク素体が加熱され、形状記憶合金が変形しコンデンサ素
子を基板から押し上げ、切れ込みよりセラミック素体を
完全に8 分断してしまうことにより電気的にオープン状態を作り
出し、積層セラミックコンデンサの損傷および付近の電
子部品、延ではプリント基板を焼損させることを防止す
るという効果がある。
As explained above, according to the present invention, the shape memory alloy is fitted into the notch in the approximate center of the surface of the multilayer ceramic capacitor element, and if a short circuit occurs after it is mounted on the board, heat generation due to overcurrent will occur. As a result, the ceramic body is heated, the shape memory alloy is deformed, the capacitor element is pushed up from the substrate, and the ceramic body is completely divided through the notch, creating an electrical open state and damaging the multilayer ceramic capacitor. It also has the effect of preventing nearby electronic components, especially printed circuit boards, from burning out.

また、このような非常に優れた効果を備えているにもか
かわらず、従来の積層セラミックコンデンサと形状は全
く変わらす供給、実装等の取り扱いについても、従来の
長所を損なうことなくそのまま維持している。
In addition, despite having such excellent effects, the shape is completely different from that of conventional multilayer ceramic capacitors, and the handling of supply, mounting, etc. has been maintained without compromising the conventional advantages. There is.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a>.(b)は本発明のー・実施例の積層セラ
ミックコンデンサを示す図で第1図(a)は斜視図、第
1図(b)は断面図、第2図(a)〜(d)は本発明の
一実施例の製造工程を示す図で、第2図(a).(b)
はそれぞれ、積層体を切断、切れ込みを形成する工程の
断面図および斜視図、第2図(C)は切断、切れ込み形
或後のコンデンサ素子の断面図、第2図(d)は焼成後
外部電極を形成した後の斜視図、第3図(a)9 (b)は本発明の一実施例の積層セラミックコンデンサ
の一部品、形状記憶合金の斜視図で、第3図(a>は常
温での形状第3図(b)は約300℃以上での形状を示
す図、第4図(a).(b)は本発明の他の実施例の積
層セラミックコンデンサの一部品、形状記憶合金の斜視
図で第4図(a)は常温での形状第4図(b)は約30
0℃以上での形状を示す図、第5図(a),(b)は本
発明の積層セラミックコンデンサの効果を示す断面図で
第5図(a)は通常に実装された状態第5図(b)はシ
ョート不良が発生した時の状態を示す図、第6図は従来
の積層セラミックコンデンサの一例の断面図である。 1,11・・・内部電極、2,12・・・外部電極、3
・・・コンデンサ素子、4・・・切れ込み、5,51・
・・形状記憶合金、6・・・積層体、7・・・焼成体、
8・・・基板、21・・・切断刃、22・・・切断位置
、41・・・切れ込み位置。
1(a>.(b) is a diagram showing a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 1(a) is a perspective view, FIG. 1(b) is a sectional view, and FIG. 2(a) is a perspective view. a) to (d) are diagrams showing the manufacturing process of an embodiment of the present invention, and Fig. 2(a).(b)
are respectively a cross-sectional view and a perspective view of the process of cutting the laminate and forming the notches, FIG. 2(C) is a cross-sectional view of the capacitor element after cutting and forming the notches, and FIG. 3(a) and 9(b) are perspective views of a shape memory alloy, which is a part of a multilayer ceramic capacitor according to an embodiment of the present invention, and FIG. 3(a) is a perspective view after forming electrodes. Figure 3 (b) is a diagram showing the shape at temperatures above about 300°C, and Figures 4 (a) and (b) are parts of a multilayer ceramic capacitor according to another embodiment of the present invention, a shape memory alloy. Figure 4 (a) is a perspective view of the shape at room temperature. Figure 4 (b) is approximately 30 mm.
5(a) and 5(b) are cross-sectional views showing the effects of the multilayer ceramic capacitor of the present invention, and FIG. 5(a) shows the state when it is normally mounted. (b) is a diagram showing a state when a short-circuit failure occurs, and FIG. 6 is a cross-sectional view of an example of a conventional multilayer ceramic capacitor. 1, 11...inner electrode, 2,12...external electrode, 3
... Capacitor element, 4 ... Notch, 5,51.
... Shape memory alloy, 6... Laminated body, 7... Sintered body,
8... Board, 21... Cutting blade, 22... Cutting position, 41... Notch position.

Claims (3)

【特許請求の範囲】[Claims] 1.誘電体セラミックシートを介して相対する内部電極
層を交互に積層埋設し両端に内部電極が交互に露出する
よう切断し焼結させて一体化した後、前記内部電極と電
気的に接続した外部電極を付設したコンデンサにおいて
、前記コンデンサの表面のほぼ中央部の電極の無い部分
に、前記外部電極とほぼ平行に設けられた切れ込みと、
前記切れ込みにはめ込まれた常温ではその切れ込みの形
状とほぼ同一形状を有し、かつ約300℃以上では大き
く変形する特性を有する形状記憶合金とを有することを
特徴とする積層セラミックコンデンサ。
1. Internal electrode layers facing each other are alternately laminated and buried through dielectric ceramic sheets, cut so that the internal electrodes are exposed alternately at both ends, and then sintered and integrated, and then external electrodes are electrically connected to the internal electrodes. a notch provided substantially parallel to the external electrode in a substantially central portion of the surface of the capacitor where there is no electrode;
A multilayer ceramic capacitor comprising: a shape memory alloy that is fitted into the notch and has substantially the same shape as the notch at room temperature, and has a characteristic of being significantly deformed at temperatures above about 300°C.
2.切れ込みの断面の形状が鋭角を有する形状であるこ
とを特徴とする特許請求の範囲第1項記載の積層セラミ
ックコンデンサ。
2. 2. The multilayer ceramic capacitor according to claim 1, wherein the cut has a cross-sectional shape having an acute angle.
3.コンデンサの表面のほぼ中央部の電極の無い部分に
外部電極とほぼ平行に切れ込みを形成する工程と、前記
切れ込みに常温では切れ込みとほぼ同一形状を有し、か
つ約300℃以上では大きく変形する特性を有する形状
記憶合金をはめ込む工程とを含むことを特徴とする積層
セラミックコンデンサの製造方法。
3. A process of forming a notch almost parallel to the external electrode in a part of the surface of the capacitor that has no electrodes in the center, and a characteristic that the notch has almost the same shape as the notch at room temperature, and is significantly deformed at temperatures above about 300°C. A method for manufacturing a multilayer ceramic capacitor, comprising the step of fitting a shape memory alloy having a shape memory alloy.
JP30403989A 1989-11-21 1989-11-21 Laminated ceramic capacitor and manufacture thereof Pending JPH03163810A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30403989A JPH03163810A (en) 1989-11-21 1989-11-21 Laminated ceramic capacitor and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30403989A JPH03163810A (en) 1989-11-21 1989-11-21 Laminated ceramic capacitor and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH03163810A true JPH03163810A (en) 1991-07-15

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JP30403989A Pending JPH03163810A (en) 1989-11-21 1989-11-21 Laminated ceramic capacitor and manufacture thereof

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140211368A1 (en) * 2013-01-25 2014-07-31 Murata Manufacturing Co., Ltd. Multilayer capacitor, taping multilayer capacitor series, and mounting structure of multilayer capacitor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140211368A1 (en) * 2013-01-25 2014-07-31 Murata Manufacturing Co., Ltd. Multilayer capacitor, taping multilayer capacitor series, and mounting structure of multilayer capacitor
CN103971931A (en) * 2013-01-25 2014-08-06 株式会社村田制作所 Multilayer Capacitor, Taping Multilayer Capacitor Series, And Mounting Structure Of Multilayer Capacitor
US9490071B2 (en) * 2013-01-25 2016-11-08 Murata Manufacturing Co., Ltd. Multilayer capacitor, taping multilayer capacitor series, and mounting structure of multilayer capacitor

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