JPH031635A - Transmission queue management equipment - Google Patents

Abstract

PURPOSE:To update transmission queue information and to quicken the processing by transferring information to one memory when confirmation of transmittal is received from a transmission opposite party at high speed and inverting the content of the destination. CONSTITUTION:Upon the receipt of R sets of transmittal confirmation information from a transmission destination I, when a CPU sets the destination number of opposite party to an I 12 and the number of opposite parties to an R 15, a CTL 10 reads the number of transmission queues from an N 19 and an N-R 26 calculates a difference between the numbers N and R. After the number is set to the head of the transmission queue of other high speed memory MB 3 than the high speed memory designated by a TBL 11, the number R receiving the transmittal confirmation is incremented sequentially by a C 14 and the result is inputted to a FIFO 4. Till the end of the transmission queue is detected, the content of the block number of the transmission queue is transferred sequentially, and the content of a memory selection table of the destination I is inverted after the end of transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transmission queue management device, and more particularly to a transmission queue management device that stores and manages block numbers of frames waiting to be transmitted for each of a plurality of destinations.

[Conventional technology]

Conventionally, when there are multiple communication destinations, a transmission waiting queue is configured for each destination, and software loads and takes out data from the transmission waiting queue by manipulating the chaining pointer of the connection of this transmission waiting queue. was.

[Problem to be solved by the invention]

In the conventional transmission queue management device described above, it is necessary to follow the connection pointer of the transmission queue, so when the transfer speed is high, the number of destinations is large, and the amount of communication is large, the software processing becomes difficult. There is a disadvantage that the transfer capacity decreases as the number increases.

An object of the present invention is to compile the information of the transmission waiting queue for each destination in a dedicated high-speed memory, and when there is a delivery confirmation, to fill the information in the transmission waiting queue by the number of delivery confirmations at the beginning. An object of the present invention is to provide a transmission queue management device that facilitates management and increases the processing ability of a processor for data communication.

[Means to solve the problem]

The transmission queue management device of the present invention includes a first transmission queue management device that stores block numbers of frames waiting to be transmitted for each of a plurality of destinations.
．． A second memory is connected to the first memory for each transmission destination.
．． a second memory selection table that stores which memory to select; a first register that stores the destination when a delivery confirmation is received from the destination; and a second memory that stores the number of delivery confirmations. a register, a write counter for filling the head of the destination's transmission waiting queue by the number of items for which delivery confirmation has been obtained, and an adder for adding the contents of the second register and the value of the write counter. , and a comparator for detecting the rear end of the transmission waiting queue.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In Figure 1, a transmission queue management device (hereinafter referred to as QMG)
)1, two sets of high-speed memories (hereinafter referred to as MA2 and MB3) that store information on the transmission waiting queue, and a first-in/first-out memory (hereinafter referred to as F IFO) 4.

QMGl includes a control unit (hereinafter referred to as CTL) 10, a memory selection table (hereinafter referred to as TBL) 11, a register (hereinafter referred to as I) 12 for storing destinations that have received delivery confirmation, and a destination to be loaded into a transmission waiting queue or referred to. A register that stores J (
Hereinafter J) 13 and a write counter (hereinafter C) when filling the transmission waiting queue to the top when receiving R delivery confirmations.
14, and a register (hereinafter referred to as R) 1 that stores R delivery confirmations.
5, and an adder for the read address (hereinafter referred to as R+C) when filling the transmission waiting queue to the top when delivery confirmation is received.
16, a register (hereinafter referred to as K) 17 that stores the number K from the beginning when referring to the contents of the transmission waiting queue, and a register 17 that stores the number K from the beginning when referring to the contents of the transmission waiting queue, and an address adder (hereinafter referred to as +R) 18 for referencing the contents of the transmission queue, and a counter for storing the number of queues waiting for transmission and outputting an address when loading a new block number of a transmission frame at the end of the queue waiting for transmission. (hereinafter referred to as N) 19 and a comparator for detecting the end of transfer when filling the transmission waiting queue to the head (hereinafter referred to as CMP)
20 and MA2. an upper address selector (hereinafter referred to as 5EL-) 21 for selecting an upper address to be input to MB3;
A lower address selector (hereinafter referred to as 5LB) 22 that selects a lower address to be input to A2, and a lower address selector (hereinafter referred to as 5LB) to select a lower address to be input to MB3.
23, a search counter (hereinafter referred to as 5) 24 for the transmission waiting queue for each destination, and a register (hereinafter referred to as 5A) 25 for storing the next destination to which the transmission waiting queue found in S24 is not 0. Subtractor (hereinafter referred to as N-R) 26
It consists of A signal 100 from the CPU is input to the internal bus 103 of the QMGI, and is sent to the MA via the data bus 101.
2゜MB3. Input to FIFO4. 5EL21 is C
112. by the selection signal from TLIO. JlB.

Select one of the outputs of S24 and send it to the address bus 102.
via MA2. Enter the upper address in MB3 and 5L
A22, 5LB23 is set to C14, R+C16, +R18, 17. by the selection signal from CTLlo. Select either the output of N19 or the head address of the transmission waiting queue and send MA2. Input the lower address in MB3.

FIG. 2 is a diagram showing an example of the memory configuration in the high-speed memory in FIG. 1, and FIG. 3 is a diagram for explaining the operation in FIG. 1 when a delivery confirmation is received from the transmission destination.

First, the CPU uses J to load the transmission queue.
After setting the destination number in IB and writing the block number of the frame not to be sent, CTLlo sends a selection signal to 5EL21 to output the contents of JIB, and stores it in the high-speed memory (here MA2) indicated by TBLll. The number of items waiting to be sent at the head of the destination sending queue is set to N1 once.
Set it to 9, increment N19, write the block number specified by the CPU to this position, set the value of N19 (number of items waiting to be sent) at the beginning of the transmission waiting queue, increment N19 again, and write the block number specified by the CPU to this position. Writes the data "FFFF" indicating the rear end. CTLIO increments the transmission destination in S24, searches for the number of waiting transmissions at the head of the transmission waiting queue of MA2 indicated by TBLII, and determines the number of waiting transmissions. When a destination is found that is not O and can be sent by the transmission permission/denial indication bit, this value is transferred to 5A25 and the CP
In FIG. 2, which shows the configuration of MA2 when requesting U to start sending, when the CPU receives R delivery confirmations from the sending destination ■, it sets this number to 112 and sets this number to 112. When set to R15, CTLIO first sets the number of queues at the head of the queue waiting for transmission to N1.
9, calculate the difference between the numbers N and R using N-R26, set this number at the head of the transmission waiting queue of a high-speed memory (i.e. MB3) different from the high-speed memory specified by TBLII, and then As shown in Figure 3, after reading out the number R of items whose delivery has been confirmed while incrementing C14 and putting them into FIFO4, the contents of the block number of the sending queue are read out until the end of the sending queue is detected. Sequentially transfer to the head of one transmission waiting queue, and finally, after transferring the end mark, this destination I
Inverts the contents of the memory selection table.

〔Effect of the invention〕

As explained above, the present invention configures a transmission waiting queue for each transmission destination on two sets of memories, and when R delivery confirmations are received from transmission destination I, a transmission waiting queue for each transmission destination is created from the other memory shown in the memory selection table. After high-speed transfer to the memory for the number of delivery confirmations to the beginning, the information in the transmission waiting queue can be updated by inverting the contents of destination I in the memory selection table, so the software can operate the chaining pointer. This has the effect of allowing processing to be performed much faster than conventional devices that process transmission queues.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of the memory configuration in the high-speed memory in FIG. 1, and FIG. 2 is a diagram for explaining the operation in FIG. 1. FIG. 1... Transmission queue management device (QMG), 2゜3
...High-speed memory (MA, MB), 4...First-in, first-out memory (F I FO), 10
...Control unit (CTL), 11...Memory selection table (TBL), 12.13, 15, 17.25...Register (I, J, R, SA), 14°19...・Counter (C, N), 16...Adder (R+Cm 18
... Address adder (K+R), 20... Comparator (CMP), 21... Upper address selector (SEL)
), 22.23...lower address selector (SLA,
5LB), 24... Search counter (S), 26...
- Subtractor (NR).

Claims (1)

[Claims] It is connected to first and second memories that store block numbers of frames waiting to be transmitted for each of a plurality of destinations, and stores which of the first and second memories to select for each destination. a memory selection table; a first register that stores the destination when a delivery confirmation is received from the destination; a second register that stores the number of delivery confirmations; A write counter for filling the head by the number of items whose delivery has been confirmed, an adder for adding the contents of the second register and the value of the write counter, and a comparison for detecting the rear end of the transmission waiting queue. A transmission queue management device comprising: