JPH03169121A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction of the circuit by preventing both a PMOS transistor(TR) and an NMOS TR at an output stage from being energized simultaneously at the time of changing over an input data. CONSTITUTION:A time difference is caused in the output change in a NAND gate circuit 1 fed to the gate of a PMOS TR 3 and the output change in a NOR gate circuit 2 fed to the gate of an NMOS TR 5, both the TRs fall into a nonenergized state and the output reaches a high impedance for the period. When the output of a 2-input NAND gate circuit 1 reaches '0', the PMOS TR 3 is energized to raise the level of a data output terminal OUT to logical '1'. Since the power level and ground level of other circuit on a same integrated circuit board are not fluctuated due to a large current flowing from a power supply to ground at the time of changing over the input data, the malfunction of the circuit due to the level fluctuation is evaded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an output buffer circuit, and particularly to a complementary MOS (
The present invention relates to an output buffer circuit using a transistor (hereinafter referred to as CMOS).

[Conventional technology]

Conventional output buffer circuits of this type are shown in Figures 4 and 5. In FIG. 4, VDD is a positive power supply, 90 is an inverter circuit, 40 is a P-channel MOS (hereinafter referred to as PMOS) transistor, and 60 is an N-channel MOS (hereinafter referred to as NM
(referred to as OS) transistor, D is the data input terminal, and O is the data input terminal.
UT is a data output terminal. Here, if the data input from the data input terminal D has a logical value of 1 (hereinafter referred to as "1"), the output of the inverter circuit 90 is inverted and has a logical value of O (hereinafter referred to as ``O''). Therefore, PMOS
Transistor 40 is conductive, NMOS transistor 6
0 becomes non-conductive, and the data output terminal OUT becomes at the level of the positive power supply VDD, that is, "1". When the data input terminal D is “0”, the output of the inverter circuit 90 is “1”.
''', and the PMOS transistor 40 becomes non-conductive.
The NMOS transistor 60 becomes conductive, and the data output terminal OUT becomes the ground level, that is, "0". In this way, the configuration is such that a signal having the same phase as the input data can be obtained as output data.

FIG. 5 shows a second conventional example, which includes a two-man powered NAND gate circuit 100, a two-man powered NOR gate circuit 200, an inverter circuit 15, a PMOS transistor 40, an NM
This is more important than the OS transistor 60. VDD is the positive power supply, D is the data input terminal, C is the control signal input terminal, OU
T is the data output terminal. Now, control signal input terminal C
If “1” is input to the inverter circuit l
The output of 5 is "O n". Here, "1" is input to the data input terminal D, and the output of the two-man power NAND gate circuit 100 and the output of the two-man power NOR gate circuit 200 both become "O". , the PMOS transistor 40 is in a conductive state and the NMOS transistor 60 is in a non-conductive state, and "1" is input to the data output terminal OUT.Furthermore, when "O I1" is input to the data input terminal D, the two-man power NAN
The outputs of the D gate circuit 100 and the two-man power NOR gate circuit 200 are each "'1", the PMOS transistor 40 is in a non-conducting state, the NM○S transistor 60 is in a conducting state, and the data output terminal OUT is "O". is output. On the other hand, when "On" is input to the control signal input terminal C, the output of the inverter circuit 15 becomes "1", and the output of the inverter circuit 15 becomes "1", regardless of whether the data input terminal D is "1" or "O".
The output of the human-powered NAND gate circuit 100 is fixed to "1", the output of the two-human powered NOR gate circuit 200 is also fixed to "0", and P
Both MOS transistor 40 and NMOS transistor 60 become non-conductive. In this case, the level of the data output terminal OUT is neither "1n" nor "0'', but is high.
The structure is such that it assumes an impedance state. [
[Problems to be Solved by the Invention] In the conventional output buffer circuit described above, the buffer section is configured in the process in which the level of the data input terminal D changes from "1" to "MO" or from "II O" to "1". PM to do
There is a momentary state in which both the OS transistor 40 and the NMOS transistor 60 are conductive. Generally, in this type of output buffer circuit, the PMOS transistor 40 and NMOS transistor 60 in the output stage have a gate width of If W is W and the gate length of the transistor is L, the ratio of W to L (hereinafter referred to as W/L) is often set to be large. When both the PMOS transistor and the NMOS transistor, which have a large W/L, that is, a small equivalent resistance component in the conductive state, and the NMOS transistor become conductive at the same time, a large current flows from the positive power supply VDD toward the ground. This current causes a voltage drop determined by the resistance of the ground wiring between the positive power supply VDD and the other circuits on the same integrated circuit board. This has the disadvantage that the circuit may malfunction due to the negative effect it has on the circuit. The object of the present invention is to
The object of the present invention is to provide an output buffer circuit in which both OS transistors do not become conductive at the same time. [Means for Solving the Problems] The output buffer circuit of the present invention includes a first logic circuit having an input terminal and a first node as inputs, and a second logic circuit having the input terminal and a second node as inputs. a logic circuit; a MOS transistor of one conductivity type having a source-drain path connected between the first node and an output terminal and a gate connected to the output terminal of the first logic circuit; and a source-drain path connected to the output terminal; a reverse conductivity type MOS transistor connected between a terminal and the second node and having a gate connected to an output terminal of the second logic circuit;
a first CMOS circuit whose input is the output terminal of the second logic circuit and whose output terminal is connected to the first node;
and a second CMOS circuit whose input is the output terminal of the logic circuit and whose output terminal is connected to the second node. [Example] Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram for explaining the first embodiment of the present invention. The NAND gate circuit has the data input terminal D and the first node 347 as inputs, and its output terminal is connected to the gate of the PMOS transistor 3. The connected NOR gate circuit 2 has the data input terminal D and the second node 568 as inputs, and its output terminal is connected to the gate of the NMOS transistor 5.The PMOS transistor 3 has its source-drain path connected to the gate of the NMOS transistor 5. Data output terminal OtJT and first node 347
NMOS transistor 5 is connected between its source and
A drain path connects the data output terminal OUT and the second node 568
The PMOS transistor 4 has its source train path connected between VDD and the first node 347, and its gate is connected to the output terminal of the NOR gate circuit 2, and the NMOS transistor 6 has its source train connected between the VDD and the first node 347. - The drain path is connected between GND and the second node 568, and the gate is connected to the output end of the NAND gate circuit 1. Further, the NMOS transistor 7 has its source-drain path connected between GND and the first node 347, and its gate connected to the NOR
The PMOS transistor 8 has its source-drain path connected between VDD and the second node 568 and its gate connected to the output terminal of the NAND gate circuit 1.
It is connected to the output terminal of. Note that in these circuit configurations, one CMOS circuit is formed by the PMOS transistor 4 and the NMOS transistor, and another CMOS circuit is formed by the NMOS transistor 6 and the PMOS transistor 8.
An S circuit is formed. The PMOS transistors 3 and 4 and the NMOS transistors 5 and 6 have a large W/L so that they can be driven sufficiently even when a small resistance or a large capacitance is attached as a load to the data output terminal OUT. On the other hand, the PMOS transistor 7 and the NMOS transistor 8 are not provided for the purpose of driving the load of the data output terminal OUT, but have a small W/L. First, if “0” is input to data input terminal D, 2
When the output of the human-powered NAND gate circuit 1 is "1", the PMOS transistors 3 and 8 are in a non-conducting state, and the NMOS transistor 6 is in a conducting state. In addition, two-man power NOR gate circuit 2
The output of is "1", NMOS transistors 5 and 7 are in a conductive state, and PMOS transistor 4 is in a non-conductive state,
“O” is output to the data output terminal OUT, and the circuit is stable. Here, the operation of each part when the level of the data input terminal D changes from "0" to "1" and then from "1" to "0" will be explained with reference to FIG.

When the level of the data input terminal D changes from "O" to "1", the output of the two-manual NOR gate circuit 2 first changes from "1" to "O" with a slight delay. Corresponding to this change, the NMOS transistor 5 becomes non-conductive, the NMOS transistor 7 constituting the CMOS circuit becomes non-conductive, and the PMOS transistor 4 becomes conductive, so that the potential of the l-th node 347 increases. It becomes "1" with a delay from the change in the output of the NOR gate circuit 2. Next, the first node 3
In response to the change in the potential of PMOS 47, the output of NAND gate circuit 1 is further delayed and changes from "O" to "1".
Transistor 3 becomes conductive. Note that these delays are caused by wiring resistance, transistor gate capacitance, etc. As is clear from these operations, there is a time difference between the change in the output of the NAND gate circuit 1 applied to the gate of the PMOS transistor 3 and the change in the output of the NOR gate circuit 2 applied to the gate of the NMOS transistor 5, and both transistors Both are in a non-conducting state, and the output is in a high impedance state during these periods. Next, two-person NAN
When the output of the D gate circuit 1 becomes "0", the PMOS transistor 3 becomes conductive and raises the level of the data output terminal OUT to "1". In this state, the data output terminal OU'r: is connected to the PMOS transistor 3 and There is a direct current path to VDD via 4, and a signal ``1'' in phase with the input data is obtained as output data.The output ``0'' of the two-man power NAND gate circuit 1 is also NMO
It acts to make the S transistor 6 non-conductive and the PMOS transistor 8 conductive, and sets the level of the second node 568 to "1", but the data input terminal D has already been set to "1".
Therefore, it does not affect the output of the two-man powered NOR gate circuit 2. Next, when the level of the data output terminal changes from "1" to "O", the output of the two-man NAND gate circuit 1 changes from "0" to "1" with a slight delay, and the PMOS transistor 3 becomes non-operational. It becomes conductive. Next, the PMOS transistor 8 constituting the CMOS circuit is in a non-conducting state, and the NMOS
Transistor 6 becomes conductive, and the potential at second node 568 becomes "O" with further delay. In response to this change in the second node 568, the output of the NOR gate circuit 2 is further delayed and changes from "O" to "1". Therefore,
Changes in the output of NAND gate circuit 1 and NOR gate circuit 2
There is a time difference between the output changes of the PMOS transistor 3 and the NMOS transistor 5, and both the PMOS transistor 3 and the NMOS transistor 5 are in a non-conducting state, that is, a high impedance state. Next, when the output of the two-way NOR gate circuit 2 becomes "1", the NMOS transistor 5 becomes conductive and the level of the data output terminal OUT falls to "O". In this state, the data output terminal OU
There is a direct current path from T to the ground via NMOS transistors 5 and 6, and a signal "O I+" in phase with the input data is obtained as output data. Two-man power NOR
The output "1" of the gate circuit 2 also acts to make the PMOS transistor 4 non-conductive and the NMOS transistor 7 conductive, thereby setting the level of the first node 347 to "0".
However, since the data input terminal D is already “O”, 2
It does not affect the output of the human-powered NAND gate circuit 1. In addition, PMOS transistor 8 and NMOS transistor 7
are used only to determine the levels of the second node 568 and the first node 347, respectively, and as mentioned above, W/L is small, the conduction current is small, and the integrated circuit board is unnecessarily It does not occupy the area above. In addition, when switching input data, high impedance control is achieved logically without using means such as delay circuits, so a high impedance state is reliably created and large currents from the positive power supply VDD to ground can be prevented. Furthermore, it is possible to switch the output level quickly without taking an unnecessarily long high impedance period. FIG. 3 is a circuit diagram for explaining the second embodiment of the present invention. The basic structure is the same as that shown in Fig. 1, but a control signal input terminal C and an inverter circuit 15 are added, and a NAN
The difference is that the D gate circuit 10 and the NOR gate circuit 20 are powered by three people. The level at control signal input terminal C is ゜“1”
”, the output of the inverter circuit 15 is “O”,
FIG. 3 is equivalent to FIG. 1 and operates in the same way, but when the level of the control signal input terminal C is "0", the output of the three-man power NAND gate circuit 10 is independent of the level of the data input terminal D. is "1", and the output of the three-man power NOR gate circuit 20 is "O", and the PMOS transistor 3 and NMOS
Transistor 5 is constantly turned off, and data output terminal OUT is fixed in a high impedance state. In this way, the present invention can also be applied to an output buffer circuit provided with an input signal of a control signal that controls whether or not to enable the output buffer circuit. [Effects of the Invention] As explained above, the output buffer circuit of the present invention connects the PMOS transistor and NMO transistor in the output stage when switching input data.
Since both S transistors do not become conductive at the same time, the power level and ground level of other circuits on the same integrated circuit board will not fluctuate due to the large current flowing from the power supply to ground when input data is switched. Therefore, it has the effect of preventing circuit malfunctions caused by this level fluctuation. Furthermore, since the output buffer circuit of the present invention performs the above-mentioned high-impedance control logically, it has the advantage that the output level can be switched at high speed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram for explaining the first embodiment of the present invention, FIG. 2 is an operation timing diagram for explaining FIG. 1,
FIG. 3 is a circuit diagram for explaining the second embodiment of the present invention, and FIGS. 4 and 5 are circuit diagrams of output buffers according to the prior art, respectively. 1,10.100...NAND gate circuit, 2,20
．． 200...NOR gate circuit, 15.90...Inverter circuit, 3.4, 8.40...P channel MO
S transistor, 5, 6, 7.60...N channel M
OS transistor, D...data input terminal, OUT/
...Data output terminal, C...Control signal input terminal, VD
D...Positive power supply.

Claims (1)

[Claims] 1. A first logic circuit whose inputs are an input terminal and a first node; a second logic circuit whose inputs are the input terminal and a second node; and a source/drain path that is connected to the first node. a MOS transistor of one conductivity type connected between output terminals and having a gate connected to the output terminal of the first logic circuit; a source/drain path connected between the output terminal and the second node and having the gate connected to the first logic circuit; a reverse conductivity type MOS transistor connected to the output terminal of the second logic circuit; and a first MOS transistor whose input terminal is the output terminal of the second logic circuit and whose output terminal is connected to the first node.
a CMOS circuit, and a second CMOS circuit whose input is the output terminal of the first logic circuit and whose output terminal is connected to the second node.
An output buffer circuit comprising an S circuit.