JPH03168857A - Direct memory access controller of pointer base - Google Patents

Abstract

PURPOSE: To effectively process data transfer by means of a process without interposing a host by always detecting whether a buffer memory is null or full when the host transfers data. CONSTITUTION: A direct memory access control part(DMAC) consists of a host interface 11, a priority deciding device 15 and a buffer interface 12. This DMAC can detect whether the buffer memory is called or not by the host and a disk when a data transferring process is started and can transfer data when erroneous data is detected and corrected. Thereby the DMAC can effectively process data transfer without the interference of the host 1 to improve the performance of a host system 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) This invention relates to a pointer-based direct memory access (DMA) device that is used in a programmable disk controller. Controls the operating cycle of the ring memory buffer so that transfers (or data transfers) of different sizes and speeds occur without interference from the processing unit.

BACKGROUND OF THE INVENTION In standard computer systems, mass storage hosts are commonly utilized to store data that is often transferred to or from the host system. In such data transfers between transfers, the operations are either host sleep disk cycles or host read disk cycles.Furthermore, to suit the different data transfer characteristics of both host and disk, buffer memory is It is used to temporarily hold data during a process.

For example, during a host read disk cycle, data recorded on the disk magnetic medium is sent first to the buffer memory from the disk controller without sensing, and then to the buffer memory when the host is ready to receive the data. Transferred to ST. During the host 1-logged disk cycle, data coming from the host is first sent to the buffer memory, then to the disk 41 controller, and then enters the disk.

In either direction of the data transfer cycle, disk Il
The illtmit device's direct memory access (DMA) controller is used to control all related transfer operations. First of all, while the host U calls the buffer memory in units of data bytes, reading or writing data to the disks is done in units of sectors (eg, 512 bytes). Therefore, the DMA controller must ensure that the host, on the one hand, checks whether the memory is empty or full when data is to be transferred, and that there is a complete sector of data to write to disk. It won't happen. The DMA tlIl tll must also ensure that there is complete sector space available in the buffer memory for the data to be read from the disk.

Additionally, the DMA controller allows the host and disk controller to access specific buffer memory locations so that data can be transferred to or from buffer memory. - Generates an address signal that needs to be transferred from memory. In general, the DMA illumination device must prevent the host from reading data back from the disk when certain errors occur and are not corrected.

There are many ways to interface a buffer 7 array with a host and a mass storage device. For example, US Pat. No. 3,851,335@ discloses a simple add/subtract counter that tracks data transfers into and out of a buffer. On read operations, the counter is decremented, but inputs and reads that occur at the same time have no effect on the counter.

This is far too simple a device to address the problems that complex DMA tall controllers must solve.

U.S. Pat. No. 4,723,233 discloses a number of registers indicating starting and ending addresses defining a transfer area on the disk, a storage location counter pointing to the area being called, and a storage location counter after reaching the ending address. and an update circuit that sets DMA fill to the first address.
tll i5! is disclosed. The purpose of this method is to
The goal is to reduce the loss of speed of transfer.

Some commercial disk υ11I devices have different DMA
The implementation of illumination functions is also well known. For example, Adaptec In
C. )'s disk controller (Arc-610) incorporates a DMA controller with write access, read access, and stop pointers. What is the actual use of the first two pointers? - Depends on port and direction of data transfer. The stop pointer is
It is used to control data transfer between the host and buffer 7. In this method, the transfer control processing is performed by the host, which tends to degrade the performance of the host.

Other known designs of DMA controllers are those manufactured by Standard Microsystems (standardHiCr).
Disk controller (OSyStQIS Corp-)
95C02). In this device, DM A II
The IIII processor has been upgraded to the level of a microbrochure, including many internal registers, counters, state machines, and an ALU (arithmetic logic unit). The various counters include an offset counter that tracks the empty/full condition of buffer 7 and an auxiliary offset counter that tracks the number of error-free data bytes remaining in the buffer. DM A! , II till
Although IlltIII allows the transfer of disk data without host intervention, IlltIII itself requires a lot of additional hardware and is complicated to operate.

SUMMARY OF THE INVENTION The object of the invention is, on the one hand, to provide efficient DMA all I1Il Il functionality with minimal hardware requirements, and on the other hand, to provide an efficient DMA all I1I IlIl capability with minimal hardware requirements and, on the other hand, to provide a step-by-step data processing system that increases the amount of host and disk data. is to overcome the task of complex buffer management when buffers differ in terms of size and transfer speed.

The present invention provides a buffer 7 memory address that is called during the process of data transfer between the host and the disk.
It uses multiple primary pointers.

Two additional pointers with unique content are designated by predetermined relationships with the two primary pointers.

As the data transfer progresses, these pointers are changed in content according to predetermined operating rules.
are compared to generate a flag signal that activates the port.

This arrangement allows the DMA controller to detect whether the buffer memory is empty or full whenever the host is to transfer data. Enables the disk to detect when it starts receiving full sector data from or transferring data to the buffer memory when space for sectors of data or blank sectors, respectively, is available. Become. D M A I
The I1 controller can accommodate different data transfer sizes and transfer good data when erroneous data is thereby corrected.

According to the present invention, DMA t. The II 611 m handles data transfers in an automatic and efficient process without host intervention. The predetermined operating rules described above also prevent data overrun conditions in the buffer memory. Preferred embodiments of the invention are described in detail below with reference to the accompanying drawings.

For the purpose of clearly explaining the preferred embodiment of the present invention, the main blocks that make up the disk ill II device will be briefly introduced.

The functions of the disk t,+1a device can be thought of as a serial data transfer controller responsible for transferring data to and from the disk and a buffer management controller responsible for transferring data to and from the buffer memory.

The architecture of the disc controller designed by the inventors of the present invention as shown in FIG. 1 shows the building blocks and the relationships therebetween.

In FIG. 1, the system structure of a disk-based computer system is shown.

There are several functional blocks interposed between the host 1 and the disk drive 2 that are interconnected. Random access memory (RAM) buffer 4 is a disk-based mt
Data to be transferred between the host 1 and the disk drive 2 through the controller (WDC) 3 is temporarily held. disk f.
The controller 3 receives commands from the local microbe processor (LμP) 6 and performs all data transfers. In some system architectures, Direct Memory Access (DMA)! llt
ll device 5 is disc-based! It is included in ll vessel 3, and
It processes all data transfers under the control of μP 6 and disk controller 3. RAM Bano 74 is l) M
The host 1 and the disk illtll unit 3 are connected to each other by the address signal provided by the A mill
called by

The data pattern in this system includes both types of serial and parallel bit streams. Host 1, RAM buffer 4
The parallel data flowing between the disk controller 3 and the disk controller 3 differ in the unit of data transfer, which is a byte unit and a sector unit, respectively.

Encoder/decoder block 7 encodes data before it is written to the disk medium and decodes encoded data that is read from the disk medium.

The RAM buffer 74 stores byte-based and sector-based inputs and outputs to and from the host 1 and the disk controller 3, respectively.
Used to accommodate base data transfer. RAM
One embodiment of buffer 4 is dynamic RAM or static R
It can be implemented by utilizing a circular ring memory such as AM. If data transfers to and from the ring memory are subject to proper tI11 control of the disk controller 3, the size of the RAM buffer 4 is virtually unlimited? can be managed.

The disk controller 3 of FIG. 1 will now be briefly described.

It includes a local processor (L.μP) interface 10, a host interface 11, a buffer interface 12, and a peripheral 8M device interface 13.
, sequencer RAM 14, priority determiner 15, first-in first-out memory (FIFO) 16, error correction code/station 1l
1 redundancy checker (ECC/CRC) 1 7, clock system 1
1I unit 18, and serializer/deserializer 19a, 19b
1 and the functional blocks shown in FIG. 2, such as an encoder/decoder 7.

The operation of the disk controller tII unit 3 can be easily pinned by observing the data transfer operation (disk read operation) from the disk drive 2 and the data transfer operation (disk write operation) to disk drive #7]B2. Can be done. In a disk read operation, data stored on a disk (not shown) is read and then sent to the decoder 7 to be decoded. The composite serial data bits are then converted into parallel data bytes via deserializer 19b. The data bytes are then calculated along with the data from sequence RAM 14 to find the correct data sector! ．． D. is determined and sent to the FCC/CRC block 17 for checking for errors that occurred during the readback process.

In a disk write operation, host interface 11 is initiated by sending a host cycle request to priority determiner 15 to transfer data to RAM buffer 4. Next, the data in RAM buffer 4 is P I
FI to priority decider 15 until F01 6 is full
It is fed into PIF016 by F I F O 1 6 which sends the FO cycle request. Whenever FIFO1 6 is blank, a FIFO Nicle request is sent again. At the same time, the data is also fed into the ECC/CRC1 7 to generate check bytes for each sector. P
The data byte in IF016 is first serialized by serializer 19a.
The parallel data bytes are channel encoded through an encoder 7 to produce the desired data channel coding formations such as MFM (Modified Frequency Modulation) and RLL (Run Length Limited) codes. Convert to a bit stream.

DISK CONTROLLER The relevant functional blocks of the disk a, 11111 device 3 of the present invention are briefly described with respect to FIG.

(a) LμP interface The block of the LμP interface 10 is configured by the disk controller 3 and its stored program.
1, which is another single-chip microcomputer connected to the local microcontroller 6 of FIG. When LLtP6 needs to call the register of disk control filter 3 or RAM buffer 74, it calls L
CS bin 101 of μP interface 10, ALE[
3 bin 102, ADO=7 port 107, RDB bin 1
04 or WRB bin 105 to set internal registers of the disk controller ilta and generate LμP cycle requests. The INT bin 106 of the LμP interface 10 is configured by the disk controller 3 to inform the Lμρ 6 of the occurrence of an event such as any FCC error in the ECC/CRC 17 or a sector IQ error detected in the sequencer RAM 14. Set. ADO-7 port 107 is LμP6
Sends and receives data and addresses to and from internal registers.

(b) Post interface host ●Interface 11 is a disk-based 611B
When requesting data to be transferred to or from a host], port HReq. A signal such as B signal 3715 is generated. As each byte of data is transferred or received by host 1, the port ACKl3
Signal 3714 is sent by host 1 to host interface 11 and is responsive as a handshaking signal in response to port entry Req-B signal M3715. The LOI signal 3718 sent by the host interface 11 latches the data with any external input/output data latching device (not shown) in case of data loss. BIEB signal 3716 and BOEB signal 37
17 controls the flow of data into and out of the RAM buffer 4.

(The C-face peripheral interface 13 receives the WG signal 1 which instructs the disk drive '!A2 to output a write current to the magnetic head of the disk drive 2 (during a disk write operation).
32 and <<during disk read operation)
Phase locking of the disk driver 2 to lock onto incoming coarse disk data being played from the disk.
It supplies an RG signal 131 that instructs the loop circuit. Peripheral interface 13 is connected to sequence RAM 14 and ECC/CRC 17.

(d) Sequencer RAM Sequencer RAM 14 coordinates the operational relationships between the various blocks of FIG. Sequencer RAM 14 is preferably constructed with an array of RAMs organized in multiple words, each of which is further organized in multiple bytes. Each byte represents a field in 45 sequential flow controls. By programming these fields of each word, all operational sequences between all building blocks in the Disk&+1 controller 3 can be performed in a well-known manner.

(e) ECC/CRC This block 17 consists of the selected F
Generate data check bytes (ECC decoding) in disk write operations with CC/CRC polynomials. When the disk controller 3 reads back the data, its polynomial is also sent to this block to check whether any errors are present. If an error is detected,
This block calculates the error location and error pattern, and then performs error correction (rEccJ *correct)
Issue an ECC error interrupt request to μP6.

mFIFo memory FIFO (first in, first out) memory 16 reconciles different transfer rates between disk 2 and host 1.
The size of memory 16 is limited to 16 bytes of memory.
, and also depends on the data transfer rate of the disk drive 2, the data transfer rate of the host 1, and the RAM buffer access rate.

(i) Clock controller clock controller 18 receives two independent clock inputs, the DMACLKI signal 181J3 and the RRC signal. DMACLK1 signal 181
R determines the speed of data transfer between the buffer interface 12 and the host interface 11.
AM buffer transfer clock.

The RRC signal 182 is the sequencer R8M operating clock that controls the speed of the sequence RAM 14, and
1: IFO transfer clock that controls the speed of data transfer between the FO memory 16 and the peripheral interface 13. Since these two clocks are independent, they are not slowed down by disk data rates slower than the host data rate.

The serializer 19a and the deserializer 19b convert parallel byte data to serial bitstream data and vice versa, respectively.

The encoder/decoder 7 converts the data into a desired data format before writing it to the disc, and also restores the data read from the disc to its original data format.

A preferred construction of encoder/decoder 7 is disclosed in co-pending US patent application Ser.

m buffer interface In FIG. 2, the buffer interface block 12 has a 16 bit buffer 7 memory address
A15-O(121) and 8-bit data edict BD
O-7 (1 22>, buffer corruption possible signal (B
WEB) 3719, and DMA clock signal (DMA
CLKO) 1 23 is generated. The structure and operation of buffer interface 12 is described below in conjunction with direct memory access unit 5 below.

Direct Memory Access The direct memory access controller (DMA) shown in FIG.
C) 5 is separated from three blocks: host interface 11, priority determiner 15, and buffer interface 12. These blocks include the invention of this application. The detailed structure of DMAC5 is explained below.

From FIG. 3(a), it can be seen that the DMA IQ 11+ device has four registers or pointers or host pointers.
HP)20. A disk pointer (DP) 21, a good data pointer (GP) 22, and a check pointer (C
P) Contains 23. The values of HP20 and DP21 supply the RAM buffer address 121 that the disk υ1111 unit 3 needs to access in Tj if it is the host 1, respectively. During a disk read operation, GP22 points to the highest address of the last FCC modified block (sector) of data.

In the event of a disk damaging operation, it is the final EGC of the data.
Points to the lowest address of a coded block (sector). According to the present invention, the value of CP23 is smaller than the value of HP20 by 1
It is fixed to one sector (for example, 512 bytes).

1-I P 2 0 is preferably a 16-bit counter. The output of HP20 is driven by a three-state buffer 7 (not shown) and received at terminals OE24 and EC25, respectively.
It is preferable that it be controlled by an "increment" signal. CP2
The structure of 3 is similar. GP22 is GL28 and OE2
9 and 16-bit data latches that receive ``latch'' and ``enable'' signals at 9 and 9, respectively. DP21 also said “
16 controlled by “enable” and “increment” signals
It is a bit counter. Both outputs of HP20 and DP21 are 16-bit latch address signals (BA15-O) connected to RAM buffer 74.

The latch 32 uses the address buffer 33 to transfer the address signal 121 to the RAM buffer? The address signal 12 received from either HP 20 or DP 21 before being sent to
Latch 1.

The DMA controller 5 further includes a comparator 34, one side of which is connected to H P 2 0 and D P 2 1, and the other side connected to CP 23 and GP 22. As explained below, during data transfer operations,
The DMA controller 5 selects which comparison operations are to be performed in different data transfer cycles for each zjc interface 20.
2 1. 22. Drives 23 OEga children.

The output at the CPEQ terminal 35 of the comparator 34 is extracted by the port state determiner 36 and sent to the sequencer RAM.
It generates control flag signals including a start port D signal 38 sent to the host 14 and a stop port D signal 39 that together with the host 1 control the data transfer. Both the start port D signal 38 and the stop port H 3 9 play a critical role in this data transfer arrangement, which will be explained in detail below.

Several DMAs that can call RAM buffer 4
There is a channel. For example, in FIFO Nicle, the data is increased by the amount of PIFO 16 and RAM buffer 4. During this cycle, R A M Bano 7.
Address (BA15-0) 121 is the content of DP21. FIFO cycles have highest priority over the Buffer 7 bus.

The other low priority DMA channel is the host cycle where puff data is transferred to and from the host. During the host cycle, RAM buffer address 1
21 is the content of HP20.

The functions of transfer cycle priority and transfer direction control of the RAM buffer 4 are performed by a cycle and direction control Ma unit 37 in the DMA device controller 5.

Figure 3(b) shows HPG241, GPL281, CPEQ
351, shows one embodiment of port state determiner 36, where initial state set 361 and CPDP 301 are input signals generated according to a predetermined operating rule or sequence described below. HTD362 indicates the direction of data transfer in either a host write disk cycle or a host read disk cycle. In the following, the port D disk controller 3 is shown, and the port mouth is the host 1. The port DCy signal 363 is a port D request signal 3711 which is a transfer request signal from the disk controller 3.
2 shows a transfer cycle of port D initiated by . Conventional AND gates 2411-2415 and NOR gates 2811-2814 generate the desired stop port input signal 39 and stop port D signal 38 according to a predetermined operating rule or sequence described below. received or generated by port status determiner 36. Various timings of E book and iljll
The l signals are shown in FIGS. 9a to 9S, of which FIGS. 9b to 9j show those obtained during a disk write operation, and FIGS. Figure 9S shows what is obtained during a disk read operation.

FIG. 3(C) shows the cycle and direction 11ltller 37.
The structure of It is basically a DMA that generates a timing sequence according to a predetermined operating rule or order below.
The timing generator 371 warns. The DMA timing generator 371 receives the stop port}-1 signal 39 and the port D request signal 3711, thereby causing the DMA
Transfer clock XC3 7 1 3 (7) IJli with clock frequency equal to half of ACLK1 signal 181
Receive port cy signal 3712 and port o
cy signal 363 is generated.

DMA timing generator 371 also receives port HACKB signal 3714, which is DMAtlIltII.
This is an initial procedure signal for a port request 83715 between the device 5 and the host 1. The DMA timing generator 371 then outputs the HPGP 241, HPINC 251, DPOU
T261, DPING271, GPL281, CPDP
301, CPINC311, ALE321, 81EB3
716, 80EB3717, LOI3718, BWEB
3719 and a port request 83715 as well as a direction control signal.

Cycles and directions! The various timing and ill control signals described above that are received and generated by the 11tll generator 37 (or timing generator 371) are shown in FIGS. 7a-7n, of which FIGS. 7th
Figure d represents the received signal.

The various timing and tI signals received or generated by the cycle and direction controller 37 and which directly affect disk read and write operations.
The Il control signals are shown in FIGS. 8a to 80, of which FIGS. 8b to 8i are used during a disk write operation (H
FIGS. 8j to 8o show what is obtained when TD=1), and FIGS. 8j to 8o show what is obtained when TD=0.

In order to correlate the timing of FIGS. 7, 8 and 9 to one U, they each include a timing diagram for clock signal XC (i.e. FIG. 7b, FIG. 8a and FIG. 9a). I'm here.

The operation of DMA IIIll Iller 5 is based on an internal DMA clock generated from the DMACLK1 signal mentioned above.

From FIG. 4, it is shown that the internal DMA clock creates four working stages, namely working stages 0-3. DM
During the A cycle, all bytes are transferred from rebuffer 4 to buffer 4 in one working phase, which does not necessarily start with working stage fflO.

In actual operation, the comparison of HP20 and GP22 is always carried out in working phases O and 1, while the comparison of DP21 and CP23 is always carried out during the increase in the value of HP20 in working phases 2 and 3. An increase in CP23 is accompanied by an increase in H P 2 0 in working stages 0 and 1.

Once the above-mentioned DMA controller 5 is provided, starting from the initial conditions created by the local processor LμP6, the host 1
It is possible to automatically perform data transfer between the LμP 6 and the disk-1 controller 3 without interference from the LμP 6. The initial state and values required for operation are determined by the port state determiner 36.
Initial state set 361, HP20, GP22, D
Contains the initial contents of PI and CP23. To transfer any data, [μP6 must calculate a transfer count (bytes) that initializes a stop counter (not shown). Whenever a data byte is transferred to or from host 1, such a stop counter counts down by one until it reaches zero, which stops the host transfer.

D M A t. ll In order to explain the detailed operation of the 611 device, Fig. 5(a) to Fig. 5(+)) and Fig. 6(
It is necessary to proceed with two separate operations: a host write disk cycle and a host read disk cycle as shown in FIG. 6(0).

Host input/output disk cycles are shown in Figures 5(a) to 5.
Reference will now be made to FIG. 9(p) and FIGS. 9a to 9j.

In the host write disk cycle, FIG. 5(a)
is the initial state r l-I P 2 1, DP21, GP2
2 points to the same position, CP23 is smaller than HP20 1
This indicates the location of one sector (for example, 512 bytes). 9th
As shown in the timing diagram of Figure 0, hour 1m display t5a
Then, signal stop port 139 is set to O to enable port-to-port transfer. Start port 038 is set to O to inhibit port D forwarding. Figure 5(b) shows host 1
indicates that when the host starts transferring data to buffer 4, the values of HP20 and CP23 are incremented with each byte of data transferred from the host.

FIG. 5<C) shows that after one sector of data has been transferred from the host 1, the value of CP23 becomes equal to the value of DP21, so that the starting port D38 is at the point of time indication t5c. is set to 1 to indicate that port D is enabled, as shown in the timing diagram.

FIG. 5(d) shows . When port D begins to transfer data to disk, it indicates that the value of DP21 is incremented with each byte of data transferred to disk.

Figure 5(e) shows that there is less than one complete sector (for example, 512 bytes) of data in buffer 4.
P21 eventually caught up with CP23, resulting in a starting bow of 1.
- 0 3 8 is shown at time t5e in the tying diagram of Figure 9j.
It is set to O as shown in .

FIG. 5(f) shows that the starting port D38 is not activated, but only the starting port D38 is activated at the beginning of each sector transfer.
8, indicating that port D will continue to transfer data to the disk until one complete sector of data has been transferred.

FIG. 5 (l indicates that after one complete sector of data has been transferred to the disk, G22 is set immediately on DP21 and port D checks the status of starting port 038. Since port D data transfer is now stopped.

Figures 5(h) and 5(i) show that when there is now more than one sector of data in buffer 4, port D is enabled by setting start port D to 1. show.

FIG. 5(j) shows that HP 20 catches up with GP 22 once buffer 4 is finally full. There is no room for host data. Therefore, as shown in the timing diagram of FIG. 9q, at time t5j, the stop port H
39 is set to 1. Since disk data transfer rates are relatively slow, buffer 74 is fully filled.

Figure 5(k) shows that the GP2
2 cannot be updated. Portro is therefore still unusable.

FIG. 5(1) shows that GP 22 is updated because the last block of data in buffer 4 has finally been processed by ECC/CRC 1 7. FIG. Therefore, as shown in the timing diagram of FIG. 9, at time t51,
Stop port 839 is set to 0 and port H starts transferring again.

FIG. 5(m) and FIG. 5(n) show the stop port H=0
and 1m indicates that the starting port D=1, so port 1 and port D are active.

FIG. 5(0) shows that when starting port D38 is set to O, only DP21 catches up with CP23. On the one hand, port DP21 is still transferring the last sector of data.

FIG. 5(p) shows that buffer 4 is blank. All pointers and flags are the same as their initial state.

The host read disk cycle is shown in Figures 6(a) to 6.
FIG. 9(0) and FIGS. 9k to 9S will now be described.

FIG. 6(a) shows the initial state} IP20, GP22, D
P21 points to the same position, and CP23 points to one sector as P201. : Indicates a position that is not satisfied.

Stop port H39 is set to 1 to disable port [11 forwarding. As shown in FIG. 9S, the time te
a, start port D38 is set to 1, and port D
enable transfer.

FIG. 6(b) shows port D beginning to transfer disk data to buffer 4. FIG. DP21 is incremented as each byte of data is transferred from disk.

Figure 6(C) shows that after one sector of data has been transferred from the disk and the ECC has been modified, the value of GP22 is D.
P21 is updated to be equal to the value of P21, and then the value of FIG.
As shown in , at time t6C, the stop port opening 39 becomes O.
is set to indicate that the port is enabled.

FIG. 6(d) shows that after stop port 1 is set to O, start port D is set to 1, so that both port D and port mouth are enabled.

Section 6tJ(e) is a modified EC that can be transferred to the host.
HP20 eventually catches up with GP22, representing the absence of C, and thus at time 6, as shown in Figure 9p.
e indicates that the stop port 139 is set to 1.

Figures 6(f) and 6(9) show that more than one sector of data has been transferred to buffer 4, but one sector of data preceding GP21 is also not EGG modified. Therefore, GP22 cannot be updated, indicating that the port mouth is still unavailable.

FIG. 6(h) shows that one sector has now been FCC corrected,
Therefore, GP22 is updated to the sector boundary before DP21 (before the next unmodified sector), and then stop port 39 is set to O to indicate that port H is enabled.

FIG. 6(i) shows that DP21 catches up with CP23, representing less than one full sector (e.g. 512 bytes) of buffer space storing disk data, and thus FIG. As shown in FIG. 3, it is shown that the start port D38 is set to O at time t61.

FIG. 6(j) shows that after one sector of data has been transferred to buffer 4, starting port D38 is examined and port D is disabled. Since the last transferred sector of data has been ECCM corrected, GP22 is updated to DP21.

FIG. 6(k) shows that while there is enough space for 1@ sector of disk data, CP23 has caught up with DP21 and thus port D is enabled, i.e. starting port D38 is the 9th Time t6 in Figure S
Set to 1 at k.

Figures 6(l), 6(m) and 6(n) show that when stop port 10 and start port D = 1, port H and port D are both active. Show.

Figure 6 (0>) shows that when HP20 catches up with GP22,
Stop port H to indicate that Bano 74 is blank.
39 is set to 1. All pointers and flags are the same as their initial state.

The above operating rules can be generalized as follows:
During the initialization stage, all devices inside the DMAC 5 are set to the initial plane.

Whenever a data transfer is completed, the +m chain pointer is incremented to determine whether to then activate the port status determiner 36 which generates or reverses the start port 03B or stop port signals. compared to All of these operating rules apply to host write disk cycles and host read disk cycles.

The operation of the DMA IIll controller 5 having such a structure is as follows.
In cooperation with other blocks of disk-based me, the host 14
．． and the desired function of data transfer between the disk 2 and the disk 2.

Due to the minimum hardware requirements, the DMA controller 5 is able to detect whether the buffer memory 4 is called by the host 1 and the disk 2 as soon as the data transfer process begins. i! III I1l m 5
may transfer data when erroneous data is detected and corrected.

Therefore, the DMAill controller 5 can effectively handle data transfers without interference from the local processor 6 and the host 1, thus improving the performance of the host system 1.

Although the invention has been described with respect to particular embodiments, those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit of the invention as set forth and the scope of the claims.

[Brief explanation of the drawing]

FIG. 1 is a main building block diagram of a disk-based computer system including the disk controller of the present invention, FIG. 2 is a functional block diagram of the disk controller of the present invention, and FIGS. 3(C) to FIG. 3(C) are ifill diagrams of the preferred embodiment of the present invention, and FIG. 4 is a graph diagram showing divisions of clock signals. 5(a) to 5(p) are detailed diagrams of the operation of the inventive pointer during a host read disk cycle; FIGS. 6(a) to 6(0)
7(a) to 7(n) are detailed illustrations of the operation of the pointer of the present invention during a host write disk cycle; FIGS. FIGS. 8a through 8o are simultaneous timing diagrams of another set of signals received or generated by the cycle and direction control of FIG. Of these, FIG. 8 d to FIG. 8 1 are obtained during a disk write operation, and FIG. 8 j to 8 O are obtained during a disk read operation. a
9S to 9S are timing diagrams of simultaneous occurrences of signals received and generated by the port status determiner of FIG. 3B, of which FIGS. FIG. 9 is a diagram showing the tying diagram obtained during the process of working on a disc, and in which FIGS. Explanation of symbols: 1...Host: 2...Disk drive; 3...Disk controller; 4...R
A M buffer; 5...DMAC (direct memory access tljlMI unit); 6...Lμp
(h4 part microbe O processor); 7...Encoder/decoder

Claims (1)

[Scope of Claims] (1) In a direct memory access controller that controls access by a host and a disk device to a buffer memory, data transfer between the buffer memory and the host and disk device is performed when the data is and a disk device and processed by an error correction device, the direct memory access controller is controlled by first and second signals, respectively, during separate disk read and write cycles, and the direct memory access controller: (A) The following, namely (1) host access address HP to the buffer memory, (2) disk device access address DP to the buffer memory, (3) address CP subtracted by a predetermined amount from the address HP. , (4) a pointer device for providing an address GP in the buffer memory of a data block of a predetermined size processed by the error correction device; (B) comparing HP with GP and DP with CP; (C) in response to said comparison device, whenever HP and GP are equal and whenever DP and CP are equal, said first and second
(D) the following: (1) the address GP in the pointer device whenever the error correction device processes one data block of the predetermined size; (2) incrementing the addresses HP and DP in the pointer device by the predetermined amount whenever a data unit is transferred between the buffer memory and the host and disk device; (3) start data transfer if currently stopped;
or a cycle and direction control device that stops data transfer, if currently underway, between the buffer memory and the host and disk device in response to a change in state of each one of the first and second signals; A direct memory controller comprising: (2) The disk device has a plurality of data sectors, the size of the data block is equal to the size of one sector, and the address CP is equal to the address HP.
smaller than the size of one disk sector,
A direct memory controller according to claim 1, characterized in that: 3. A direct memory controller according to claim 1, wherein said error correction device processes said data during said reading and writing by correcting errors in said data. A direct memory controller according to claim 1, further comprising: (4) a local processor for setting the initial contents of a pointer device and the states of said first and second signals. (5) The initial content is set to HP=GP=DP, CP=HP-sector size+1, and the first
and a second signal as inactive and active, respectively, and as active and inactive, respectively, during a host write disk cycle. vessel. (6) The inactive state of the first signal allows the host to transfer one byte of data into and out of the buffer memory, and the active state of the second signal allows the host to transfer one byte of data into and out of the buffer memory.
5. A direct memory controller according to claim 4, wherein the memory is capable of transferring one sector of data to and from the disk device. (7) The direct memory access controller according to claim 1, wherein the size of the buffer memory is equal to the size of a plurality of sectors of the disk device. (8) In a method for controlling access to a buffer memory of a host and a disk device, data transfer between the buffer memory and the host and disk device is such that data is transferred between the host and the disk and errors occur. Whenever processed by a modification device, the first and second
The methods, each controlled by a signal, include (A) in each pointer register: (1) the host's access address to the buffer memory; (2) the disk device's access address to the buffer memory; 3) providing an address CP subtracted by a predetermined amount from the address HP; (4) an address GP in the buffer device of a data block of a predetermined size processed by the error correction device; (B) comparing HP to GP and DP to CP; and (C) determining the states of the first and second signals whenever HP and GP are equal and whenever DP and CP are equal. (D) whenever said error correction device processes one data block of said predetermined size, said address G
(E) increasing the addresses HP and DP to one data unit whenever a data unit is transferred between the buffer memory and the host and disk device; (F) starting data transfer if currently stopped;
or stopping a data transfer, if currently underway, between the buffer memory and the one of the host and disk devices whenever the state of each one of the first and second signals changes. A control method comprising: (9) (A) setting the first and second signals to be active so that HP=GP=DP;
and CP=HP before host read disk cycle
(B) setting the first and second signals to be inactive such that HP=GP=D; and 9. Direct memory access according to claim 8, further comprising an initial step of setting CP = HP - disk sector size + 1 before a host write disk cycle. How to control. (10) Transferring data between the host and the buffer memory includes: (A) incrementing HP by 1 after transferring one data byte; and (B) incrementing the first byte when HP is equal to GP. (C) setting the second signal to be active when CP is equal to DP; and (D) incrementing CP by one data byte. A control method comprising: (11) The steps of transferring sector data between a buffer memory and a disk device are (A) after one data byte is transferred to or from the buffer memory;
(B) setting said second signal to be inactive when CP is equal to DP; and (C) incrementing P by one; (C) setting said second signal to be inactive when one block of data in a buffer memory GP to DP when processed by correction device
9. A method for controlling direct memory access according to claim 8, comprising the steps of: setting .